CN103036219B - Low-voltage micro-grid comprehensive protection method - Google Patents
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Abstract
本发明涉及一种低压微电网综合保护方法，用以解决传统保护方法不适应于微电网的问题。本发明的方法能够适应于微电网孤岛运行模式以及并网运行模式，该保护方案可以通过逻辑功能实现，有效解决了微电网在这两种操作模式下的保护问题，该保护方案不需要通信链路，与传统的自适应保护装置有明显的区别。其突出特点是保护的有效性在很大程度上是独立故障电流水平、微电网运行模式以及分布式发电单元容量大小和类型，只与两种运行模式下不同的参数设置有关。本发明的方法不仅能够实现单相保护，还能够实现三相保护，提高了电力能源供应的安全性。
The invention relates to a comprehensive protection method for a low-voltage micro-grid, which is used to solve the problem that the traditional protection method is not suitable for the micro-grid. The method of the present invention can be adapted to the island operation mode and the grid-connected operation mode of the microgrid, and the protection scheme can be realized through logic functions, effectively solving the protection problem of the microgrid under these two operation modes, and the protection scheme does not require a communication link The road is obviously different from the traditional adaptive protection device. Its outstanding feature is that the effectiveness of the protection is largely independent of the fault current level, microgrid operation mode, and distributed generation unit capacity size and type, and is only related to the different parameter settings in the two operation modes. The method of the invention can realize not only single-phase protection, but also three-phase protection, thereby improving the safety of electric energy supply.
Description
Technical field
The present invention relates to micro-electric network protection field, particularly a kind of micro-electric network protection method.
Background technology
For electric power system, micro-electrical network is similar to an independently control unit, and wherein each micro-power supply has that simply to pull out be plugging function.A simple micro-electric network composition as shown in Figure 1.Main electrical network connects the open connection bus of micro-electrical network by QF, passes through respectively QF1, QF2 connexon bus 1 and primary and secondary line 2 on public connection bus.On primary and secondary line 1 and primary and secondary line 2, connect micro-power supply (DR1, DR2, DR3) and load.
The structure of micro-electrical network has proposed some special requirements to relaying protection.Tradition power distribution network is mostly radial pattern, end non-transformer, and owing to there being micro-power supply, the electric current of flowing through on protective device may be for two-way.Once micro-electrical network islet operation, capacity of short circuit has large variation, has affected the normal operation of original some protective relaying device.Change the mode of original single distributed power generation access electrical network, forming one of original intention of micro-electrical network is to maintain as much as possible some important loads in the time of electric network fault, can normally move and not make its power failure, these important loads are often to voltage-sensitive, working voltage does not change excessive, overlong time, must adopt some QA switches, to replace the slower switch of original relative action for this reason.The problems referred to above all may make traditional protective device and strategy no longer be adapted to micro-electrical network, so must propose the new protection that is applicable to micro-electrical network and control strategy.
Explanation of nouns: distributed power generation DG (distributed generation) refers to specific demand for meeting terminal use, be connected near small power generation system user's side.Micro-power supply, distributed power source DR (Distributed Resource) refers to the association system (DR=DG+ES) of distributed power generation and energy storage device ES (Energy Storage).
Summary of the invention
The object of this invention is to provide the micro-electric network synthetic guard method of a kind of low pressure, be not suitable for the problem of micro-electrical network in order to solve traditional protection method.
For achieving the above object, the solution of the present invention is: the micro-electric network synthetic guard method of low pressure, and for the arbitrary circuit breaker in micro-electrical network, step is as follows:
1) gather: gather three-phase voltage, the three-phase current signal of circuit breaker, obtain negative sequence voltage V2 by negative phase-sequence measuring component and zero sequence measuring component, negative-sequence current I2 and zero-sequence current I0;
2) signal logic processing: described negative sequence voltage V2 and negative-sequence current I2 obtain negative zero sequence direction logical signal PDU_L through power direction measuring unit PDU, and each phase current signal obtains transient state overcurrent protection logical signal AOC_L, BOC_L, the COC_L of corresponding phase by transient state overcurrent measuring unit TOCU; The electric current of arbitrary phase gets or obtains direction logical signal PDU_La, PDU_Lb, the PDU_Lc of corresponding phase after power direction measuring unit PDU with negative zero sequence direction logical signal PDU_L with voltage; Each phase voltage signal obtains under voltage logical signal UVU_La, UVU_Lb, the UVU_Lc of corresponding phase through under voltage protection unit UVU;
Transient state overcurrent protection logical signal AOC_L, BOC_L, COC_L and interface enable signal IE phase or obtain the first logical signal PDU_La1, PDU_Lb1, the PDU_Lc1 of corresponding phase, transient state overcurrent protection logical signal AOC_L, BOC_L, COC_L postpone through TD_IOC and under voltage logical signal UVU_La, UVU_Lb, the UVU_Lc of corresponding phase get or obtain the second logical signal PDU_La2, PDU_Lb2, PDU_Lc2;
The first logical signal PDU_La1, PDU_Lb1, PDU_Lc1, the second logical signal PDU_La2, PDU_Lb2, PDU_Lc2 and direction logical signal PDU_La, PDU_Lb, PDU_Lc phase with, then postpone to obtain the 3rd logical signal PDU_La3, PDU_Lb3, PDU_Lc3 through TD_IF;
After direction logical signal PDU_La, PDU_Lb, PDU_Lc negate and the second logical signal PDU_La2, PDU_Lb2, PDU_Lc2 phase with, then postpone to obtain the 4th logical signal PDU_La4, PDU_Lb4, PDU_Lc4 through TD_IR;
3) when islet operation, if the 3rd logical signal PDU_La3, PDU_Lb3, PDU_Lc3, in the 4th logical signal PDU_La4, PDU_Lb4, PDU_Lc4, any is 1, and interface enable signal IE is 0, and correspondence trips mutually;
4) while being incorporated into the power networks, each phase current signal obtains the 5th logical signal PDU_La5, PDU_Lb5, PDU_Lc5 by inverse-time overcurrent protection element, the 5th logical signal PDU_La5, PDU_Lb5, PDU_Lc5 and direction logical signal PDU_La, PDU_Lb, PDU_Lc phase with, then postpone to obtain the 6th logical signal PDU_La6, PDU_Lb6, PDU_Lc6 through TD_GF; After direction logical signal PDU_La, PDU_Lb, PDU_Lc negate and the 5th logical signal PDU_La5, PDU_Lb5, PDU_Lc5 phase with, then postpone to obtain the 7th logical signal PDU_La7, PDU_Lb7, PDU_Lc7 through TD_GR; While being incorporated into the power networks, if the 6th logical signal PDU_La6, PDU_Lb6, PDU_Lc6, in the 7th logical signal PDU_La7, PDU_Lb7, PDU_Lc7, any is 1, and interface enable signal IE is 0, and correspondence trips mutually;
5) each phase current signal postpones to obtain the 8th logical signal PDU_La8, PDU_Lb8, PDU_Lc8 through TD_HIF after by high impedance protection component, the 8th logical signal PDU_La8, PDU_Lb8, PDU_Lc8 and direction logical signal PDU_La, PDU_Lb, PDU_Lc get and obtain the 9th logical signal PDU_La9, PDU_Lb9, PDU_Lc9, if the 9th logical signal PDU_La9, PDU_Lb9, PDU_Lc9 are 1, and interface enable signal IE is 0, and correspondence trips mutually; It is isolated island module forward direction time delay module that TD_IF postpones, and it is the backward time delay module of isolated island module that TD_IR postpones, and it is grid-connected module forward direction time delay module that TD_GF postpones, and it is the backward time delay module of grid-connected module that TD_GR postpones.
The one or three phase logic signal is got or obtained to the 3rd, the 4th, the 6th, the 7th and the 9th logical signal of each phase;
Negative-sequence current I2 and zero-sequence current I0 get or obtain the two or three phase logic signal TP_L2 by the signal after transient state overcurrent measuring unit TOCU respectively, the transient state overcurrent protection logical signal AOC_L of each phase, BOC_L, COC_L get or obtain the three or three phase logic signal TP_L3, and direction logical signal PDU_La, PDU_Lb, PDU_Lc and the negative zero sequence direction logical signal PDU_L of each phase get or obtain the four or three phase logic signal PDU_Labc;
Second, third and the four or three phase logic signal get with, then postpone to obtain the five or three phase logic signal TP_Lm through TD_TF, after the four or three phase logic signal negate and first, second three phase logic signal get with, then postpone to obtain the six or three phase logic signal TP_Ln through TD_TR;
Three-phase voltage signal obtains the seven or three phase logic signal after by neutral point voltage offset measurement unit NVS;
If any is 1 for the five or three phase logic signal TP_Lm, the six or three phase logic signal TP_Ln, three-phase tripping operation; If the seven or three phase logic signal and interface enable signal IE are 1 simultaneously, three-phase tripping operation; If the one or three phase logic signal and interface enable signal IE are 1 simultaneously, three-phase tripping operation;
It is three-phase module forward direction time delay module that TD_TF postpones, and it is the backward time delay module of three-phase module that TD_TR postpones.
If main electrical network three-phase voltage signal Vabc-grid is synchronizeed with the three-phase voltage signal Vabc of grid-connected circuit breaker, grid-connected breaker closing.
Method of the present invention can be adapted to micro-electrical network islet operation pattern and the pattern that is incorporated into the power networks; this protection scheme can be realized by logic function; efficiently solve the protection problem of micro-electrical network under these two kinds of operator schemes; this protection scheme does not need communication link, has obvious difference with traditional self-adaptive protector.Its outstanding feature is that the validity of protection is independent failure levels of current, micro-operation of power networks pattern and distributed power generation cell capability size and type to a great extent, only arranges relevant from parameters different under two kinds of operational modes.Method of the present invention not only can realize single phasing protection, can also realize three-phase protective, has improved the fail safe of electric power energy supply.
Brief description of the drawings
Fig. 1 is a kind of micro-configuration of power network.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described in detail.
Micro-electrical network as shown in Figure 1, main electrical network connects a micro-electrical network by transformer, and rapid static switch connects a bus of main electrical network and micro-electrical network, and this bus connects respectively two strip buses by QF1, QF2, is equipped with micro-power supply and respective load on primary and secondary line.Rapid static switch is for isolated island/grid-connected switching, and QF1, QF2 are used for excising/dropping into micro-power supply and load on corresponding primary and secondary line.Rapid static switch, QF1, QF2 all arrange protective device on the spot, three-phase voltage, the electric current of in-site collecting respective circuit breakers below.Protective device adopts micro-chip processor to process Information Monitoring, and circuit breaker trip is controlled in output.
For arbitrary circuit breaker, its guard method for protective device comprises:
Gather: gather three-phase voltage, the three-phase current signal of circuit breaker, obtain negative sequence voltage (V2) by negative phase-sequence measuring component and zero sequence measuring component, negative-sequence current (I2) and zero-sequence current (I0);
Signal logic processing: described negative sequence voltage (V2) and negative-sequence current (I2) obtain negative zero sequence direction logical signal (PDU_L) through power direction measuring unit (PDU), and each phase current signal obtains the transient state overcurrent protection logical signal (AOC_L, BOC_L, COC_L) of corresponding phase by transient state overcurrent measuring unit (TOCU); The electric current of arbitrary phase gets or obtains the direction logical signal (PDU_La, PDU_Lb, PDU_Lc) of corresponding phase after power direction measuring unit (PDU) with negative zero sequence direction logical signal (PDU_L) with voltage; Each phase voltage signal obtains the under voltage logical signal (UVU_La, UVU_lb, UVU_Lc) of corresponding phase through under voltage protection unit (UVU);
Mutually or obtain first logical signal (PDU_La1, PDU_Lb1, PDU_Lc1) of corresponding phase, transient state overcurrent protection logical signal (AOC_L, BOC_L, COC_L) postpones through TD_IOC and the second logical signal (PDU_La2, PDU_Lb2, PDU_Lc2) is got or obtained to the under voltage logical signal (UVU_La, UVU_lb, UVU_Lc) of corresponding phase for transient state overcurrent protection logical signal (AOC_L, BOC_L, COC_L) and interface enable signal (IE);
The first logical signal (PDU_La1, PDU_Lb1, PDU_Lc1), the second logical signal (PDU_La2, PDU_Lb2, PDU_Lc2) and direction logical signal (PDU_La, PDU_Lb, PDU_Lc) with, then postpone to obtain the 3rd logical signal (PDU_La3, PDU_Lb3, PDU_Lc3) through TD_IF;
After direction logical signal (PDU_La, PDU_Lb, PDU_Lc) negate and the second logical signal (PDU_La2, PDU_Lb2, PDU_Lc2) with, then obtain the 4th logical signal (PDU_La4, PDU_Lb4, PDU_Lc4) through TD_IR delay;
Protection is divided into single phasing protection and three-phase protective, and single phasing protection comprises islet operation protection, the protection of being incorporated into the power networks, high impedance protection.
When islet operation, if the 3rd logical signal (PDU_La3, PDU_Lb3, PDU_Lc3), in the 4th logical signal (PDU_La4, PDU_Lb4, PDU_Lc4), any is 1, and interface enable signal (IE) is 0, and correspondence trips mutually;
While being incorporated into the power networks, each phase current signal obtains the 5th logical signal (PDU_La5, PDU_Lb5, PDU_Lc5) by inverse-time overcurrent protection element, the 5th logical signal (PDU_La5, PDU_Lb5, PDU_Lc5) and direction logical signal (PDU_La, PDU_Lb, PDU_Lc) with, then postpone to obtain the 6th logical signal (PDU_La6, PDU_Lb6, PDU_Lc6) through TD_GF; After direction logical signal (PDU_La, PDU_Lb, PDU_Lc) negate and the 5th logical signal (PDU_La5, PDU_Lb5, PDU_Lc5) with, then obtain the 7th logical signal (PDU_La7, PDU_Lb7, PDU_Lc7) through TD_GR delay; While being incorporated into the power networks, if the 6th logical signal (PDU_La6, PDU_Lb6, PDU_Lc6), in the 7th logical signal (PDU_La7, PDU_Lb7, PDU_Lc7), any is 1, and interface enable signal (IE) is 0, and correspondence trips mutually;
High impedance protection: each phase current signal postpones to obtain the 8th logical signal (PDU_La8, PDU_Lb8, PDU_Lc8) through TD_HIF after by high impedance protection component, the 8th logical signal (PDU_La8, PDU_Lb8, PDU_Lc8) and direction logical signal (PDU_La, PDU_Lb, PDU_Lc) are got and are obtained the 9th logical signal (PDU_La9, PDU_Lb9, PDU_Lc9), if the 9th logical signal (PDU_La9, PDU_Lb9, PDU_Lc9) is 1, and interface enable signal (IE) is 0, and correspondence trips mutually;
Three-phase protective: the one or three phase logic signal is got or obtained to the 3rd, the 4th, the 6th, the 7th and the 9th logical signal of each phase;
The two or three phase logic signal (TP_L2) is got or obtained respectively to negative-sequence current (I2) and zero-sequence current (I0) by the signal after transient state overcurrent measuring unit (TOCU), the three or three phase logic signal (TP_L3) is got or obtained to the transient state overcurrent protection logical signal (AOC_L, BOC_L, COC_L) of each phase, and the four or three phase logic signal (PDU_Labc) is got or obtained to direction logical signal (PDU_La, PDU_Lb, PDU_Lc) and the negative zero sequence direction logical signal (PDU_L2) of each phase;
Second, third and the four or three phase logic signal get with, then postpone to obtain the five or three phase logic signal (TP_Lm) through TD_TF, after the four or three phase logic signal negate and first, second three phase logic signal get with, then postpone to obtain the six or three phase logic signal (TP_Ln) through TD_TR;
Three-phase voltage signal obtains the seven or three phase logic signal after by neutral point voltage offset measurement element (NVS);
If any is 1 for the five or three phase logic signal (TP_Lm), the six or three phase logic signal (TP_Ln), three-phase tripping operation; If the seven or three phase logic signal and interface enable signal (IE) they are 1 simultaneously, three-phase tripping operation; If the one or three phase logic signal and interface enable signal (IE) they are 1 simultaneously, three-phase tripping operation.
And network interface: if the three-phase voltage signal (Vabc) that main electrical network three-phase voltage signal (Vabc-grid) and rapid static switch gather synchronize, grid-connected circuit breaker, i.e. rapid static switch closure in Fig. 1.
Power direction measuring unit (PDU), the physical significance of its output is the flow of power direction of measuring on feeder line.Transient state overcurrent measuring unit (TOCU), the physical significance of its output is to measure transient state momentary excess current on feeder line.Under voltage protection unit (UVU), its physical significance is to measure low-voltage landing on feeder line.Interface enable signal IE be control the whole protected location control signal of whether working (with logic level 1 for effectively or 0 be invalid representation).High impedance protected location changes high impedance fault measuring unit into, and its physical significance is the electric current while measuring high impedance fault.It is isolated island module forward direction time delay module that TD_IF postpones, it is the backward time delay module of isolated island module that TD_IR postpones, it is grid-connected module forward direction time delay module that TD_GF postpones, it is the backward time delay module of grid-connected module that TD_GR postpones, it is three-phase module forward direction time delay module that TD_TF postpones, and it is the backward time delay module of three-phase module that TD_TR postpones.Various measuring units and module all belong to ordinary skill in the art means above, so do not repeat them here.
Claims (3)
1. the micro-electric network synthetic guard method of low pressure, is characterized in that, for the arbitrary circuit breaker in micro-electrical network, step is as follows:
1) gather: gather three-phase voltage, the three-phase current signal of circuit breaker, obtain negative sequence voltage V2 by negative phase-sequence measuring component and zero sequence measuring component, negative-sequence current I2 and zero-sequence current I0;
2) signal logic processing: described negative sequence voltage V2 and negative-sequence current I2 obtain negative zero sequence direction logical signal PDU_L through power direction measuring unit PDU, and each phase current signal obtains transient state overcurrent protection logical signal AOC_L, BOC_L, the COC_L of corresponding phase by transient state overcurrent measuring unit TOCU; The electric current of arbitrary phase gets or obtains direction logical signal PDU_La, PDU_Lb, the PDU_Lc of corresponding phase after power direction measuring unit PDU with negative zero sequence direction logical signal PDU_L with voltage; Each phase voltage signal obtains under voltage logical signal UVU_La, UVU_Lb, the UVU_Lc of corresponding phase through under voltage protection unit UVU;
Transient state overcurrent protection logical signal AOC_L, BOC_L, COC_L and interface enable signal IE phase or obtain the first logical signal PDU_La1, PDU_Lb1, the PDU_Lc1 of corresponding phase, transient state overcurrent protection logical signal AOC_L, BOC_L, COC_L postpone through TD_IOC and under voltage logical signal UVU_La, UVU_Lb, the UVU_Lc of corresponding phase get or obtain the second logical signal PDU_La2, PDU_Lb2, PDU_Lc2;
The first logical signal PDU_La1, PDU_Lb1, PDU_Lc1, the second logical signal PDU_La2, PDU_Lb2, PDU_Lc2 and direction logical signal PDU_La, PDU_Lb, PDU_Lc phase with, then postpone to obtain the 3rd logical signal PDU_La3, PDU_Lb3, PDU_Lc3 through TD_IF;
After direction logical signal PDU_La, PDU_Lb, PDU_Lc negate and the second logical signal PDU_La2, PDU_Lb2, PDU_Lc2 phase with, then postpone to obtain the 4th logical signal PDU_La4, PDU_Lb4, PDU_Lc4 through TD_IR;
3) when islet operation, if the 3rd logical signal PDU_La3, PDU_Lb3, PDU_Lc3, in the 4th logical signal PDU_La4, PDU_Lb4, PDU_Lc4, any is 1, and interface enable signal IE is 0, and correspondence trips mutually;
4) while being incorporated into the power networks, each phase current signal obtains the 5th logical signal PDU_La5, PDU_Lb5, PDU_Lc5 by inverse-time overcurrent protection element, the 5th logical signal PDU_La5, PDU_Lb5, PDU_Lc5 and direction logical signal PDU_La, PDU_Lb, PDU_Lc phase with, then postpone to obtain the 6th logical signal PDU_La6, PDU_Lb6, PDU_Lc6 through TD_GF; After direction logical signal PDU_La, PDU_Lb, PDU_Lc negate and the 5th logical signal PDU_La5, PDU_Lb5, PDU_Lc5 phase with, then postpone to obtain the 7th logical signal PDU_La7, PDU_Lb7, PDU_Lc7 through TD_GR; While being incorporated into the power networks, if the 6th logical signal PDU_La6, PDU_Lb6, PDU_Lc6, in the 7th logical signal PDU_La7, PDU_Lb7, PDU_Lc7, any is 1, and interface enable signal IE is 0, and correspondence trips mutually;
5) each phase current signal postpones to obtain the 8th logical signal PDU_La8, PDU_Lb8, PDU_Lc8 through TD_HIF after by high impedance protection component, the 8th logical signal PDU_La8, PDU_Lb8, PDU_Lc8 and direction logical signal PDU_La, PDU_Lb, PDU_Lc get and obtain the 9th logical signal PDU_La9, PDU_Lb9, PDU_Lc9, if the 9th logical signal PDU_La9, PDU_Lb9, PDU_Lc9 are 1, and interface enable signal IE is 0, and correspondence trips mutually; It is isolated island module forward direction time delay module that TD_IF postpones, and it is the backward time delay module of isolated island module that TD_IR postpones, and it is grid-connected module forward direction time delay module that TD_GF postpones, and it is the backward time delay module of grid-connected module that TD_GR postpones.
2. the micro-electric network synthetic guard method of low pressure according to claim 1, is characterized in that:
The one or three phase logic signal is got or obtained to the 3rd, the 4th, the 6th, the 7th and the 9th logical signal of each phase;
Negative-sequence current I2 and zero-sequence current I0 get or obtain the two or three phase logic signal TP_L2 by the signal after transient state overcurrent measuring unit TOCU respectively, the transient state overcurrent protection logical signal AOC_L of each phase, BOC_L, COC_L get or obtain the three or three phase logic signal TP_L3, and direction logical signal PDU_La, PDU_Lb, PDU_Lc and the negative zero sequence direction logical signal PDU_L of each phase get or obtain the four or three phase logic signal PDU_Labc;
Second, third and the four or three phase logic signal get with, then postpone to obtain the five or three phase logic signal TP_Lm through TD_TF, after the four or three phase logic signal negate and first, second three phase logic signal get with, then postpone to obtain the six or three phase logic signal TP_Ln through TD_TR;
Three-phase voltage signal obtains the seven or three phase logic signal after by neutral point voltage offset measurement unit NVS;
If any is 1 for the five or three phase logic signal TP_Lm, the six or three phase logic signal TP_Ln, three-phase tripping operation; If the seven or three phase logic signal and interface enable signal IE are 1 simultaneously, three-phase tripping operation; If the one or three phase logic signal and interface enable signal IE are 1 simultaneously, three-phase tripping operation;
It is three-phase module forward direction time delay module that TD_TF postpones, and it is the backward time delay module of three-phase module that TD_TR postpones.
3. the micro-electric network synthetic guard method of low pressure according to claim 1, is characterized in that: if main electrical network three-phase voltage signal Vabc-grid synchronize with the three-phase voltage signal Vabc of grid-connected circuit breaker, grid-connected breaker closing.
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| CN103354354B (en) * | 2013-06-26 | 2016-03-02 | 国家电网公司 | Be applicable to impedance protecting method and the device of micro-capacitance sensor |
| CN104836214B (en) * | 2015-04-17 | 2016-02-17 | 国家电网公司 | A Coordinated Comprehensive Protection Method Based on Distributed Generation Grid-connected Transition Operation Mode |
| CN108110738B (en) * | 2017-12-19 | 2019-06-04 | 北京天诚同创电气有限公司 | Method, relay and system for micro-capacitance sensor protection |
| CN112152190B (en) * | 2019-06-28 | 2023-11-03 | 北京天诚同创电气有限公司 | Micro-grid interphase short-circuit fault protection method and system |
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