CN103034238B

CN103034238B - Automatic navigation flight control system based on cross-flow fan

Info

Publication number: CN103034238B
Application number: CN201210591012.7A
Authority: CN
Inventors: 陈云; 胡琦逸; 邹洪波; 孔亚广; 赵晓东
Original assignee: Hangzhou Dianzi University
Current assignee: Hangzhou Dianzi University
Priority date: 2012-12-28
Filing date: 2012-12-28
Publication date: 2015-01-28
Anticipated expiration: 2032-12-28
Also published as: CN103034238A

Abstract

The invention relates to an automatic navigation flight control system based on a cross-flow fan. The system comprises a power supply module, a microprocessor module, a body posture control module, a flight height detecting module, a digital compass module, a wireless data receiving and dispatching module, a GPS (Global Positioning System) positioning and navigating module, a serial port/SWD (Supersonic Wave Drive) debugging interface circuit and a signal input/output interface, wherein the body posture control module, the flight height detecting module, the digital compass module, the GPS positioning and navigating module and the wireless data receiving and dispatching module are connected with the microprocessor module through serial buses; and the power supply module provides a working power supply to the microprocessor module, the body posture control module, the flight height detecting module, the wireless data receiving and dispatching module, the serial port/SWD debugging interface circuit and a body state indication circuit. The system integrates the functions of body posture control, flight height detection, wireless receiving and dispatching and the like; and the body flight has reliable stability and controllability.

Description

Based on the self-navigation flight control system of cross flow fan

Technical field

The invention belongs to signal detection technique field, relate to a kind of four-axle aircraft automatic navigation control system for cross flow fan.

Background technology

Cross flow fan, also known as crossflow fan, it is the special blower fan of a class, impeller is multi-blade type, oval tubular, there is forward multiple wing shape blade, the air-flow have that structure is simple, volume is little, producing steadily, dynamic pressure coefficient comparatively high, be recently widely used in the occasion of the low pressure ventilation such as household electrical appliance and air-conditioning equipment ventilation.Cross flow fan has multinomial advantage compared to rotor as type of drive: because axial length is unrestricted, can need the length selecting arbitrarily impeller, motivation of adjustment according to different uses; Permeate gas stream impeller flow, by the effect of blade twice power, thus can reach farther; Without turbulent flow, air-out is even; Blade can be protected in air channel, also prevents blade in-flight from hurting sb.'s feelings; Four axle rotor crafts have non-linear, strong coupling, very complexity and the series of characteristics such as special dynamics and flight attitude, the problems such as the elastic deformation of rotor, vibration, fuselage spin can be caused, and cross flow fan stable go out wind characteristic, make the impact of these problems no longer obvious.

Current external many colleges and universities, research institution and commercial undertaking mainly carry out research intensive in a large number and exploration to multi-rotor aerocraft and application thereof, but are main mainly with four axle rotor crafts; And domestic, all rarely have about multi-rotor aerocraft report in scientific research or commercial field, say nothing of based on cross flow fan as power-actuated four-axle aircraft.Although there are some relative complete functions on the market, the flying vehicles control plate of technology maturation, but be the many rotors four-axle aircraft for model airplane fan also, wherein mostly use low cost, coarse sensor, be difficult to the precision and the reliability that reach professional inertial guidance unit, thus external force resistance disturbance, handling etc. in cannot meet actual requirement.Meanwhile, these products often do not possess or only possess very simple navigate mode, and remote manual control only can be used in the visual range of naked eyes to control flight, and potential commercial value and practical value are also developed far away.

Summary of the invention

The deficiency of functional development and support such as the present invention is directed to the unmanned self-navigation of aircraft that existing flight control system drives cross flow fan, cruise, make a return voyage, provide a kind of four-axle aircraft automatic navigation control system for cross flow fan.

The technical scheme that technical solution problem of the present invention adopts is:

The present invention includes power supply module, microprocessor module, fuselage gesture stability module, flying height detection module, digital compass module, wireless data transceiver module, GPS positioning navigation module, serial ports/SWD debug i/f circuit and signal input/output interface.Fuselage gesture stability module, flying height detection module, digital compass module, GPS positioning navigation module are connected with microprocessor module by universal serial bus with wireless data transceiver module; Power supply module is microprocessor module, fuselage gesture stability module, flying height detection module, radio receiving transmitting module, serial ports/SWD debug i/f circuit and fuselage state indicating circuit provide working power.

Described power supply module comprises+5V Power convert mu balanced circuit, analog power switch voltage-stabilizing circuit, digital power conversion mu balanced circuit, electric quantity detecting circuit, fuselage state indicating circuit and filtering antijamming circuit.

Described+5V Power convert mu balanced circuit comprises the first switching type power supply conversion chip U1, the first Schottky Rectifier D1, the first stabilizing inducatnce L1, the first resistance R1, the second resistance R2, the 9th electric capacity C9, the tenth electric capacity C10, the 11 electric capacity C11 and the 12 electric capacity C12; + VIN the end of the first switching type power supply conversion chip U1 is connected with driving power PVCC; The GND of the first switching type power supply conversion chip U1 is connected with power supply ground PGND; First switching type power supply conversion chip U1's hold and be connected with power supply ground PGND; One end of first Schottky Rectifier D1 is held with the OUT of the first switching type power supply conversion chip U1 and is connected, and the other end is connected with power supply ground PGND; One end of first stabilizing inducatnce L1 is held with the OUT of the first switching type power supply conversion chip U1 and is connected, and the other end is connected with+5V; First resistance R1 one end is connected with+5V, and the other end is held with the FB of the first switching type power supply conversion chip U1 and is connected; Second resistance R2 one end is connected with power supply ground PGND, and the other end is held with the FB of the first switching type power supply conversion chip U1 and is connected; 9th electric capacity R9 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; Tenth electric capacity R10 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; 11 electric capacity R11 one end is connected with+5V, and the other end is connected with power supply ground PGND; 12 electric capacity R12 one end is connected with+5V, and the other end is connected with power supply ground PGND.

The model of described first switching type power supply conversion chip U1 is LM2596-ADJ, and the model of the first Schottky Rectifier D1 is SS34.

Described analog power switch voltage-stabilizing circuit comprises the second linear voltage and regulates chip U3, the second electric capacity C2, the 6th electric capacity C6, the 7th electric capacity C7, the 8th electric capacity C8 and the 4th resistance R4; Second linear voltage regulates the VIN of chip U3 end to be connected with+5V; Second linear voltage regulates the GND of chip U3 end to be connected with AGND in analog; Second linear voltage regulates the VOUT of chip U3 end to be connected with analog power AVCC; The positive pole of the second electric capacity C2 is connected with+5V, and negative pole is connected with AGND in analog; One end of 6th electric capacity C6 is connected with+5V, and the other end is connected with AGND in analog; One end of 7th electric capacity C7 is connected with analog power AVCC, and the other end is connected with AGND in analog; One end of 8th electric capacity C8 is connected with analog power AVCC, and the other end is connected with AGND in analog; 4th resistance R4 one end and power supply ground PGND is connected, and the other end is connected with AGND in analog.

Described digital power conversion mu balanced circuit comprises the first linear voltage-regulation chip U2, the first electric capacity C1, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5 and the 3rd resistance R3; The VIN end of the first linear voltage-regulation chip U2 is connected with+5V; The GND end of the first linear voltage-regulation chip U2 is connected with digitally DGND; The VOUT end of the first linear voltage-regulation chip U2 is connected with digital power DVCC; The positive pole of the first electric capacity C1 is connected with+5V, and negative pole is connected with digitally DGND; One end of 3rd electric capacity C3 is connected with+5V, and the other end is connected with digitally DGND; One end of 4th electric capacity C4 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 5th electric capacity C5 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 3rd resistance R3 is connected with power supply ground PGND, and the other end is connected with digitally DGND.

Described first linear voltage-regulation chip U2 and the second linear voltage regulate the model of chip U3 to be LM1117-3.3.

Described electric quantity detecting circuit comprises the 23 resistance R23, the 24 resistance R24; 24 resistance R24 one end is connected with driving power PVCC, and the other end is held with the VBAT-CH of first microprocessor U4 and is connected; 23 resistance R23 one end is held with the VBAT-CH of first microprocessor U4 and is connected, and the other end is connected with power supply ground PGND.

Described fuselage state indicating circuit comprises the first hummer LS1, the first triode Q1, the first light emitting diode DS1, the second light emitting diode DS2, the 3rd light emitting diode DS3, the 11 resistance R11, the 12 resistance R12, the 13 resistance R13 and the 14 resistance R14; The positive pole of the first hummer is connected with analog power AVCC, and negative pole is connected with the collector of the first triode Q1; One end of 14 resistance R14 is connected with the base stage of the first triode Q1, and the other end is held with the BELL of first microprocessor U4 and is connected; The emitter of the first triode Q1 is connected with AGND in analog; One end of 11 resistance R11 is connected with+5V power supply, and the other end is connected with the positive pole of the first light emitting diode DS1; The negative pole of the first light emitting diode DS1 is connected with power supply ground PGND; One end of 12 resistance R12 is connected with digital power DVCC, and the other end is connected with the positive pole of the second light emitting diode DS2; The negative pole of the second light emitting diode DS2 is held with the LED1 of first microprocessor U3 and is connected; One end of 13 resistance R13 is connected with analog power AVCC, and the other end is connected with the positive pole of the 3rd light emitting diode DS3; The negative pole of the 3rd light emitting diode DS3 is held with the LED2 of first microprocessor U4 and is connected.The model of described first triode Q1 is 8050.

Described filtering antijamming circuit comprises the 18 electric capacity C18, the 19 electric capacity C19, the 20 electric capacity C20, the 21 electric capacity C21, the 22 electric capacity C22, the 23 electric capacity C23, the 24 electric capacity C24 and the 25 electric capacity C25; One end of 18 electric capacity C18 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 19 electric capacity C19 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 20 electric capacity C20 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 20 electric capacity C20 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 21 electric capacity C21 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 22 electric capacity C22 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 23 electric capacity C23 is connected with analog power AVCC, and the other end is connected with AGND in analog; One end of 24 electric capacity C24 is connected with analog power AVCC, and the other end is connected with AGND in analog; One end of 25 electric capacity C25 is connected with analog power AVCC, and the other end is connected with AGND in analog.

Described microprocessor module comprises first microprocessor U4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 13 electric capacity C13, the 14 electric capacity C14, the 15 electric capacity C15, the 16 electric capacity C16, the 17 electric capacity C17, the first crystal oscillator Y1, the second crystal oscillator Y2, the first button S1 and the first reserve battery BT1; One end of 5th resistance R5 is connected with digital power DVCC, and the other end is connected with the NSRT of first microprocessor U4; One end of 7th resistance R7 is connected with digitally DGND, and the other end is connected with the BOOT1 of first microprocessor U4; 8th resistance R8 one end is connected with digitally DGND, and the other end is connected with the BOOT0 of first microprocessor U4; 6th resistance R6 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; 16 electric capacity C16 one end is connected with the OSC-OUT of first microprocessor U4, and the other end is connected with digitally DGND; 17 electric capacity C17 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with digitally DGND; 15 electric capacity C15 one end is connected with the NSRT of first microprocessor U4, and the other end is connected with digitally DGND; 13 electric capacity C13 one end is connected with the OSC32-OUT of first microprocessor U4, and the other end is connected with digitally GDND; 14 electric capacity C14 is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with digitally DGND; First crystal oscillator Y1 one end is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with the OSC32-OUT of first microprocessor U4; Second crystal oscillator Y2 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; First button S1 one end is connected with the NSRT of first microprocessor U4, and the other end is connected with digitally DGND; First reserve battery BT1 one end is connected with the VBAT of first microprocessor U4, and the other end is connected with digitally DGND; VDD_1 ~ the VDD_4 of first microprocessor U4 is connected with digital power DVCC; The VDDA end of first microprocessor U4 is connected with analog power AVCC; The VSSA end of first microprocessor U4 is connected with AGND in analog; VSS_1 ~ VSS_4 end of first microprocessor U4 is connected with digitally DGND.The model of described first microprocessor U4 is STM32F101RBT6.

Described fuselage gesture stability module comprises fuselage three axis angular rate detection module and fuselage three axial rake detection module.

Fuselage three axis angular rate detection module comprises the first angular velocity detection unit U5, the 26 electric capacity C26 and the 27 electric capacity C27; The VDDIO end of the first angular velocity detection unit U5 is connected with digital power DVCC; The SCL/SPC end of the first angular velocity detection unit U5 is held with the Gyro-SPC of first microprocessor U4 and is connected; The SDA/SDI/SDO end of the first angular velocity detection unit U5 is held with the Gyro-SDI of first microprocessor U4 and is connected; The SDO/SA0 end of the first angular velocity detection unit U5 is held with the Gyro-SDO of first microprocessor U4 and is connected; The CS end of the first angular velocity detection unit U5 is held with the Gyro-CS of first microprocessor U4 and is connected; The DR/INT2 end of the first angular velocity detection unit U5 is held with the Gyro-DR of first microprocessor U4 and is connected; 8 ~ No. 12 pins of the first angular velocity detection unit U5 are RESERVED end, are connected with digitally DGND; The GND end of the first angular velocity detection unit U5 is connected with digitally DGND; No. 15 pins of the first angular velocity detection unit U5 are that RESERVED end is connected with digital power DVCC; The vdd terminal of the first angular velocity detection unit U5 is connected with digital power DVCC; 26 electric capacity C26 one end is connected with digital power DVCC, and the other end is connected with digitally DGND; 27 electric capacity C27 one end is connected with digital power DVCC, and the other end is connected with digitally DGND.The model of described first angular velocity detection unit U5 is L3G4200D.

Fuselage three axial rake detection module comprises the first inclination angle acceleration detecting unit U6; The 5V end of the first inclination angle acceleration detecting unit U6 is connected with+5V power supply; The GND end of the first inclination angle acceleration detecting unit U6 is connected with AGND in analog; Xout end, the Yout end of the first inclination angle acceleration detecting unit U6 are connected with Acce-Z with Acce-X, Acce-Y of first microprocessor U4 respectively with Zout end; The SL end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS2 of first microprocessor U4; The 0G end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-0G of first microprocessor U4; The ST end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS1 of first microprocessor U4; The GS end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-MODE of first microprocessor U4.

Described flying height detection module comprises the first digital gas pressure sensor U7, the 15 resistance R15 and the 16 resistance R16; 15 resistance R15 one end is connected with digital power DVCC, and the other end is connected with the Altimeter-SDA of the first digital gas pressure sensor U7; 16 resistance R16 one end is connected with digital power DVCC, and the other end is connected with the Altimeter-SCL of the first digital gas pressure sensor U7; The GND end of the first digital gas pressure sensor U7 is connected with digitally DGND; The EOC end of the first digital gas pressure sensor U7 is connected with the Altimeter-EOC of first microprocessor U4; The VDDA end of the first digital gas pressure sensor U7 is connected with analog power AVCC; The VDDD end of the first digital gas pressure sensor U7 is connected with digital power DVCC; The XCLR end of the first digital gas pressure sensor U7 is connected with the Altimeter-XCLR of first microprocessor U4; The NC end of the first digital gas pressure sensor U7 is unsettled.The model of described first digital gas pressure sensor U7 is BMP085.

Described digital compass module comprises the one or three number of axle word magnetoresistive transducer U8, the 17 resistance R17, the 18 resistance R18, the 29 electric capacity C29, the 30 electric capacity C30, the 31 electric capacity C31 and the 32 electric capacity C32; One end of 17 resistance is connected with digital power DVCC, and the other end is held with the Cmps-SCL of first microprocessor U4 and is connected; One end of 18 resistance is connected with digital power DVCC, and the other end is held with the Cmps-SDA of first microprocessor U4 and is connected; One end of 29 electric capacity C29 is held with the SETP of the one or three number of axle word magnetoresistive transducer U8 and is connected, and the other end is held with the SETC of the one or three number of axle word magnetoresistive transducer U8 and is connected; One end of 30 electric capacity C30 is held with the CI of the one or three number of axle word magnetoresistive transducer U8 and is connected, the other end be digitally connected; 31 electric capacity C31 one end is connected with the VDDIO of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with digitally DGND; One end of 32 electric capacity C32 is connected with the VDD of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with digitally DGND; The vdd terminal of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The VDDIO end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The SI end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; All GND end of the one or three number of axle word magnetoresistive transducer U8 is all connected with digitally DGND.The model of described one or three number of axle word magnetoresistive transducer U8 is HMC5883L.

Described GPS positioning navigation module comprises a GPS integrated chip U9, 19 resistance R19, 20 resistance R20, 21 resistance R21, 22 resistance R22, 33 electric capacity C33, 34 electric capacity C34, 35 electric capacity C35, 36 electric capacity C36, 37 electric capacity C37, second inductance L 2, 3rd inductance L 3, 4th light emitting diode DS4, second Schottky Rectifier D2, 3rd Schottky Rectifier D3, second reserve battery BT2 and the first ceramic antenna E1, one end of 19 resistance R19 is connected with the PPS of a GPS integrated chip U9, and the other end is connected with the 4th light emitting diode DS4, one end of 4th light emitting diode DS4 is connected with the 19 resistance R19, and the other end is connected with digitally DGND, one end of 20 resistance is connected with the TXA of a GPS integrated chip U9, and the other end is held with the PA3 of first microprocessor U4 and is connected, one end of 21 resistance R21 is connected with the DXA of a GPS integrated chip U9, and the other end is held with the PA2 of first microprocessor U4 and is connected, one end of 22 resistance R22 is connected with the positive pole of the second reserve battery BT2, and the other end is held with the VBAT of a GPS integrated chip U9 and is connected, one end of 33 electric capacity C33 is held with the PA3 of first microprocessor U4 and is connected, and the other end is connected with digitally DGND, one end of 34 electric capacity is held with the PA2 of first microprocessor U4 and is connected, and the other end is connected with digitally DGND, one end of 35 electric capacity C35 is held with the VCC of a GPS integrated chip U9 and is connected, and the other end is connected with one end of the second inductance L 2, one end of second inductance L 2 is connected with the 35 electric capacity C35, the other end be digitally connected, one end of 36 electric capacity C6 is held with the VCC of a GPS integrated chip U9 and is connected, and the other end is connected with one end of the second inductance L 2, one end of 3rd inductance L 3 is held with the VCC of a GPS integrated chip U9 and is connected, and the other end is connected with digital power DVCC, one end of 37 electric capacity C37 is connected with digital power DVCC, and the other end is connected with digitally DGND, the RF_IN end of the one GPS integrated chip U9 is connected with the first ceramic antenna E1, all GND end of the one GPS integrated chip U9 is all connected with digitally DGND, the positive pole of the second Schottky Rectifier D2 is held with the VBAT of a GPS integrated chip U9 and is connected, and negative pole is connected with the positive pole of the second reserve battery BT2, the negative pole of the second reserve battery BT2 is connected with digitally DGND, the positive pole of the 3rd Schottky Rectifier D3 is held with the VBAT of a GPS integrated chip U9 and is connected, and negative pole is held with the VCC of a GPS integrated chip U9 and is connected, all NC ends of the one GPS integrated chip U9 are all unsettled.The model of a described GPS integrated chip U9 is VK2525.

Described radio receiving transmitting module comprises the first high speed wireless data receiving and transmitting integrated module JP1; 1 end of the first high speed wireless data receiving and transmitting integrated module JP1 is connected with digitally DGND; 2 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with digital power DVCC; 3 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CE of first microprocessor U4; 4 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CSN of first microprocessor U4; 5 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-SCK of first microprocessor U4; 6 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MOSI of first microprocessor U4; 7 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MISO of first microprocessor U4; 8 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-IRQ of first microprocessor U4.Acp chip model in described first high speed wireless data receiving and transmitting integrated module JP1 is nRF24L01.

Described serial ports/SWD debug i/f circuit comprises first serial debugging interface JP2, a SWD debugging interface JP3; 1 end of first serial debugging interface JP2 is connected with+5V power supply; 2 ends of first serial debugging interface JP2 are held with the UART1-TX of first microprocessor U4 and are connected; 3 ends of first serial debugging interface JP2 are held with the UART1-RX of first microprocessor U4 and are connected; 4 ends of first serial debugging interface JP2 are connected with digitally DGND; 1 end of the one SWD debugging interface U5 is connected with digital power DVCC; 2 ends of the one SWD debugging interface JP3 are held with the SWDIO of first microprocessor U4 and are connected; 3 ends of the one SWD debugging interface JP3 are held with the SWDCLK of first microprocessor U4 and are connected; 4 ends of the one SWD debugging interface JP3 are connected with digitally DGND.

Described signal input/output interface comprises remote signal input interface, four-way throttle signal output interface and function conversion keys circuit.

Described remote signal input interface comprises the first remote signal input interface JP8; 1 end of the first remote signal input interface JP8 is connected with digitally DGND; 2 ends of the first remote signal input interface JP8 are connected with+5V power supply; 3 ends of the first remote signal input interface JP8 are connected with the Rev-PPM of first microprocessor U3.

Described four-way throttle signal output interface comprises the first signal output interface JP4, secondary signal output interface JP5, the 3rd signal output interface JP6 and the 4th signal output interface JP7; 1 end of the first signal output interface JP4 is connected with the PWM-CH1 of first microprocessor U4; 3 ends of secondary signal output interface JP4 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP4 are unsettled; 1 end of secondary signal output interface JP5 is connected with the PWM-CH2 of first microprocessor U4; 3 ends of secondary signal output interface JP5 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP5 are unsettled; 1 end of the 3rd signal output interface JP6 is connected with the PWM-CH3 of first microprocessor U4; 3 ends of the 3rd signal output interface JP6 are connected with power supply ground DGND; 2 ends of the 3rd signal output interface JP6 are unsettled; 1 end of the 4th signal output interface JP7 is connected with the PWM-CH4 of first microprocessor U4; 3 ends of the 4th signal output interface JP7 are connected with power supply ground DGND; 2 ends of the 4th signal output interface JP7 are unsettled.

Described function conversion keys circuit comprises the 9th resistance R9, the tenth resistance R10, second switch button S2 and the 3rd switch key S3; One end of 9th resistance R9 is held with the KEY1 of first micro-U4 of process and is connected, and the other end is connected with the second button S2; One end of second button S2 is connected with the 9th resistance R9, and the other end is connected with digitally DGND; One end of tenth resistance R10 is held with the KEY2 of first micro-U4 of process and is connected, and the other end is connected with the 3rd button 3; One end of 3rd button S3 is connected with the tenth resistance R10, and the other end is connected with digitally DGND.

The present invention has following beneficial effect relative to prior art: the present invention integrates the functions such as fuselage gesture stability, flying height detection, wireless receiving and dispatching, and body flight has reliability and stability and handling.In conjunction with corresponding upper computer software, can realize perfect man-machine interaction, monitor Flight Condition Data in real time, adjustment aircraft parameters, and retain general extension interface, functional module is transplanted easy, has stronger task ductility.

Accompanying drawing explanation

Fig. 1 is the present invention's each module work schematic flow sheet schematic diagram;

Fig. 2 is power supply module circuit diagram;

Fig. 3 is microprocessor module circuit diagram;

Fig. 4 is fuselage gesture stability module circuit diagram;

Fig. 5 is flying height detection module circuit diagram;

Fig. 6 is digital compass circuit diagram;

Fig. 7 is GPS positioning navigation module circuit diagram;

Fig. 8 is wireless data transceiver module circuit diagram;

Fig. 9 is serial ports/SWD debug i/f circuit figure;

Figure 10 is signal input/output interface circuit figure.

Embodiment

Below in conjunction with accompanying drawing, the invention will be further described.

As shown in Figure 1, the present embodiment comprises power supply module, microprocessor module, fuselage gesture stability module, flying height detection module, digital compass module, wireless data transceiver module, GPS positioning navigation module, serial ports/SWD debug i/f circuit and signal input/output interface.

Specific works process of the present invention is: angular velocity, the data such as inclination angle acceleration and flying height of fuselage gesture stability module, flying height detection module Real-time Collection fuselage three axis deliver to microprocessor by universal serial bus, and these data are using as main flight inertia feedback information; Digital compass and GPS positioning navigation module gather the flight position feedback informations such as course, speed, coordinate, also deliver to microprocessor by universal serial bus.Flight inertia feedback information utilizes kalman filter method process to merge, obtain the best output estimation value in a certain moment, pid control algorithm is adopted to carry out closed-loop control to fuselage state, the each passage PWM motor drive signal of final signal output interface generation through adjusting, to electron speed regulator input end, realizes fuselage attitude, stabilized flight controls; Utilize flight position feedback information, microprocessor change of flight attitude, along prearranged heading flight, realize automatic cruising, make a return voyage; Wireless data transceiver module timed sending flight condition information, and predetermined protocol order can be accepted, change of flight device pid control parameter and control aircraft temporarily hover, make a return voyage immediately.

As shown in Figure 2, power supply module comprises+5V Power convert mu balanced circuit, analog power switch voltage-stabilizing circuit, digital power conversion mu balanced circuit, electric quantity detecting circuit, fuselage state indicating circuit and filtering antijamming circuit.

+ 5V Power convert mu balanced circuit comprises the first switching type power supply conversion chip U1, the first Schottky Rectifier D1, the first stabilizing inducatnce L1, the first resistance R1, the second resistance R2, the 9th electric capacity C9, the tenth electric capacity C10, the 11 electric capacity C11 and the 12 electric capacity C12; + VIN the end of the first switching type power supply conversion chip U1 is connected with driving power PVCC; The GND of the first switching type power supply conversion chip U1 is connected with power supply ground PGND; First switching type power supply conversion chip U1's hold and be connected with power supply ground PGND; One end of first Schottky Rectifier D1 is held with the OUT of the first switching type power supply conversion chip U1 and is connected, and the other end is connected with power supply ground PGND; One end of first stabilizing inducatnce L1 is held with the OUT of the first switching type power supply conversion chip U1 and is connected, and the other end is connected with+5V; First resistance R1 one end is connected with+5V, and the other end is held with the FB of the first switching type power supply conversion chip U1 and is connected; Second resistance R2 one end is connected with power supply ground PGND, and the other end is held with the FB of the first switching type power supply conversion chip U1 and is connected; 9th electric capacity R9 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; Tenth electric capacity R10 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; 11 electric capacity R11 one end is connected with+5V, and the other end is connected with power supply ground PGND; 12 electric capacity R12 one end is connected with+5V, and the other end is connected with power supply ground PGND.

The model of the first switching type power supply conversion chip U4 selected by the present invention is LM2596-ADJ, can bear the direct current input of 4.5 ~ 40V, and adjustable output is+5V, for receiver, serial ports etc. provide power supply.The model of the first Schottky Rectifier D1 is SS54, and for rectification, switching speed is fast, and forward voltage drop is low, and the maximum electric current that bears is 5A, and oppositely withstand voltage is 40V, can play protection circuit, prevents the effect of transshipping.

Analog power switch voltage-stabilizing circuit comprises the second linear voltage and regulates chip U3, the second electric capacity C2, the 6th electric capacity C6, the 7th electric capacity C7, the 8th electric capacity C8 and the 4th resistance R4; Second linear voltage regulates the VIN of chip U3 end to be connected with+5V; Second linear voltage regulates the GND of chip U3 end to be connected with AGND in analog; Second linear voltage regulates the VOUT of chip U3 end to be connected with analog power AVCC; The positive pole of the second electric capacity C2 is connected with+5V, and negative pole is connected with AGND in analog; One end of 6th electric capacity C6 is connected with+5V, and the other end is connected with AGND in analog; One end of 7th electric capacity C7 is connected with analog power AVCC, and the other end is connected with AGND in analog; One end of 8th electric capacity C8 is connected with analog power AVCC, and the other end is connected with AGND in analog; 4th resistance R4 one end and power supply ground PGND is connected, and the other end is connected with AGND in analog.

Digital power conversion mu balanced circuit comprises the first linear voltage-regulation chip U2, the first electric capacity C1, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5 and the 3rd resistance R3; The VIN end of the first linear voltage-regulation chip U2 is connected with+5V; The GND end of the first linear voltage-regulation chip U2 is connected with digitally DGND; The VOUT end of the first linear voltage-regulation chip U2 is connected with digital power DVCC; The positive pole of the first electric capacity C1 is connected with+5V, and negative pole is connected with digitally DGND; One end of 3rd electric capacity C3 is connected with+5V, and the other end is connected with digitally DGND; One end of 4th electric capacity C4 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 5th electric capacity C5 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 3rd resistance R3 is connected with power supply ground PGND, and the other end is connected with digitally DGND.

The linear voltage-regulation chip U2 of selected by the present invention first and the second linear voltage regulate the model of chip U3 to be LM1117-3.3.

Adopt independently 5V/3.3V to be separated mu balanced circuit, both prevented undesired signal from scurrying into, and also digital power had been separated with analog power, ensure that supply voltage is stablized.

Electric quantity detecting circuit comprises the 23 resistance R23, the 24 resistance R24; 24 resistance R24 one end is connected with driving power PVCC, and the other end is held with the VBAT-CH of first microprocessor U4 and is connected; 23 resistance R23 one end is held with the VBAT-CH of first microprocessor U4 and is connected, and the other end is connected with power supply ground PGND.

Due to lithium battery power supply voltage, actually during Full Charge Capacity be about 24V, be substantially about 20V close to during zero electricity, therefore by electric resistance partial pressure, microprocessor can obtain battery electric quantity situation, and is unlikely to burn chip and circuit.

Fuselage state indicating circuit comprises the first hummer LS1, the first triode Q1, the first light emitting diode DS1, the second light emitting diode DS2, the 3rd light emitting diode DS3, the 11 resistance R11, the 12 resistance R12, the 13 resistance R13 and the 14 resistance R14; The positive pole of the first hummer is connected with analog power AVCC, and negative pole is connected with the collector of the first triode Q1; One end of 14 resistance R14 is connected with the base stage of the first triode Q1, and the other end is held with the BELL of first microprocessor U4 and is connected; The emitter of the first triode Q1 is connected with AGND in analog; One end of 11 resistance R11 is connected with+5V power supply, and the other end is connected with the positive pole of the first light emitting diode DS1; The negative pole of the first light emitting diode DS1 is connected with power supply ground PGND; One end of 12 resistance R12 is connected with digital power DVCC, and the other end is connected with the positive pole of the second light emitting diode DS2; The negative pole of the second light emitting diode DS2 is held with the LED1 of first microprocessor U3 and is connected; One end of 13 resistance R13 is connected with analog power AVCC, and the other end is connected with the positive pole of the 3rd light emitting diode DS3; The negative pole of the 3rd light emitting diode DS3 is held with the LED2 of first microprocessor U4 and is connected.

Filtering antijamming circuit comprises the 18 electric capacity C18, the 19 electric capacity C19, the 20 electric capacity C20, the 21 electric capacity C21, the 22 electric capacity C22, the 23 electric capacity C23, the 24 electric capacity C24 and the 25 electric capacity C25; One end of 18 electric capacity C18 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 19 electric capacity C19 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 20 electric capacity C20 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 20 electric capacity C20 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 21 electric capacity C21 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 22 electric capacity C22 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 23 electric capacity C23 is connected with analog power AVCC, and the other end is connected with AGND in analog; One end of 24 electric capacity C24 is connected with analog power AVCC, and the other end is connected with AGND in analog; One end of 25 electric capacity C25 is connected with analog power AVCC, and the other end is connected with AGND in analog.

Filter capacitor is placed in micro processor leg limit, nearby ground connection, filtering low-and high-frequency noise, and reducing simulation part affects with numerical portion.

As shown in Figure 3, microprocessor module comprises first microprocessor U4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 13 electric capacity C13, the 14 electric capacity C14, the 15 electric capacity C15, the 16 electric capacity C16, the 17 electric capacity C17, the first crystal oscillator Y1, the second crystal oscillator Y2, the first button S1 and the first reserve battery BT1; One end of 5th resistance R5 is connected with digital power DVCC, and the other end is connected with the NSRT of first microprocessor U4; One end of 7th resistance R7 is connected with digitally DGND, and the other end is connected with the BOOT1 of first microprocessor U4; 8th resistance R8 one end is connected with digitally DGND, and the other end is connected with the BOOT0 of first microprocessor U4; 6th resistance R6 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; 16 electric capacity C16 one end is connected with the OSC-OUT of first microprocessor U4, and the other end is connected with digitally DGND; 17 electric capacity C17 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with digitally DGND; 15 electric capacity C15 one end is connected with the NSRT of first microprocessor U4, and the other end is connected with digitally DGND; 13 electric capacity C13 one end is connected with the OSC32-OUT of first microprocessor U4, and the other end is connected with digitally GDND; 14 electric capacity C14 is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with digitally DGND; First crystal oscillator Y1 one end is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with the OSC32-OUT of first microprocessor U4; Second crystal oscillator Y2 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; First button S1 one end is connected with the NSRT of first microprocessor U4, and the other end is connected with digitally DGND; First reserve battery BT1 one end is connected with the VBAT of first microprocessor U4, and the other end is connected with digitally DGND; VDD_1 ~ the VDD_4 of first microprocessor U4 is connected with digital power DVCC; The VDDA end of first microprocessor U4 is connected with analog power AVCC; The VSSA end of first microprocessor U4 is connected with AGND in analog; VSS_1 ~ VSS_4 end of first microprocessor U4 is connected with digitally DGND; The model of described first microprocessor U4 is STM32F101RBT6.

The model of the first microprocessor U4 selected by the present invention is STM32F101RBT6 is a microprocessor based on ARM Cortex-M3 kernel, this processor have 256K byte flash memory, 20K byte SRAM, 51 available I/O ports and low-power consumption design can be competent at real time multi-channel data sampling and process;

Fuselage gesture stability module comprises three axis angular rate detection modules and three axial rake detection modules;

As shown in Figure 4, three axis angular rate detection modules comprise the first angular velocity detection unit U5, the 26 electric capacity C26 and the 27 electric capacity C27; The VDDIO end of the first angular velocity detection unit U5 is connected with digital power DVCC; The SCL/SPC end of the first angular velocity detection unit U5 is held with the Gyro-SPC of first microprocessor U4 and is connected; The SDA/SDI/SDO end of the first angular velocity detection unit U5 is held with the Gyro-SDI of first microprocessor U4 and is connected; The SDO/SA0 end of the first angular velocity detection unit U5 is held with the Gyro-SDO of first microprocessor U4 and is connected; The CS end of the first angular velocity detection unit U5 is held with the Gyro-CS of first microprocessor U4 and is connected; The DR/INT2 end of the first angular velocity detection unit U5 is held with the Gyro-DR of first microprocessor U4 and is connected; 8 ~ No. 12 pins of the first angular velocity detection unit U5 are RESERVED end, are connected with digitally DGND; The GND end of the first angular velocity detection unit U5 is connected with digitally DGND; No. 15 pins of the first angular velocity detection unit U5 are that RESERVED end is connected with digital power DVCC; The vdd terminal of the first angular velocity detection unit U5 is connected with digital power DVCC; 26 electric capacity C26 one end is connected with digital power DVCC, and the other end is connected with digitally DGND; 27 electric capacity C27 one end is connected with digital power DVCC, and the other end is connected with digitally DGND.

Three axial rake detection modules comprise the first inclination angle acceleration detecting unit U6; The 5V end of the first inclination angle acceleration detecting unit U6 is connected with+5V power supply; The GND end of the first inclination angle acceleration detecting unit U6 is connected with AGND in analog; Xout end, the Yout end of the first inclination angle acceleration detecting unit U6 are connected with Acce-Z with Acce-X, Acce-Y of first microprocessor U4 respectively with Zout end; The SL end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS2 of first microprocessor U4; The 0G end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-0G of first microprocessor U4; The ST end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS1 of first microprocessor U4; The GS end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-MODE of first microprocessor U4.

The model of the first angular velocity detection unit U5 selected by the present invention is L3G4200D, provides three optional sampling angular velocity precision ± 250/500/2000 deg./sec., can start self-inspection.After angular velocity data signal exports, need first through Hi-pass filter, then amplify 10 times to operational amplifier.Finally, after low-pass filter process, each axial signal delivers to first microprocessor U3 respective input.

The model of the first inclination angle acceleration detecting unit U6 selected by the present invention is MMA7361; This inclination angle acceleration detecting unit is owing to carrying signal condition low-pass filter, and without the need to external unit, sampling output pin can directly be connected to first microprocessor U4, therefore uses very easy.Before work, software merit rating selects high sensitivity pattern, first carries out the detection of 0g freely falling body after startup.Timer-controlled self-inspection and temperature compensation in operational process.

As shown in Figure 5, flying height detection module comprises the first digital gas pressure sensor U7, the 15 resistance R15 and the 16 resistance R16; 15 resistance R15 one end is connected with digital power DVCC, and the other end is connected with the Altimeter-SDA of the first digital gas pressure sensor U7; 16 resistance R16 one end is connected with digital power DVCC, and the other end is connected with the Altimeter-SCL of the first digital gas pressure sensor U7; The GND end of the first digital gas pressure sensor U7 is connected with digitally DGND; The EOC end of the first digital gas pressure sensor U7 is connected with the Altimeter-EOC of first microprocessor U4; The VDDA end of the first digital gas pressure sensor U7 is connected with analog power AVCC; The VDDD end of the first digital gas pressure sensor U7 is connected with digital power DVCC; The XCLR end of the first digital gas pressure sensor U7 is connected with the Altimeter-XCLR of first microprocessor U4; The NC end of the first digital gas pressure sensor U7 is unsettled.The model of the digital gas pressure sensor U10 selected by the present invention is BMP085, and this sensor, by I2C bus transfer barometric information, can obtain aircraft current flight height through simple conversion.

As shown in Figure 6, digital compass module comprises the one or three number of axle word magnetoresistive transducer U8, the 17 resistance R17, the 18 resistance R18, the 29 electric capacity C29, the 30 electric capacity C30, the 31 electric capacity C31 and the 32 electric capacity C32; One end of 17 resistance is connected with digital power DVCC, and the other end is held with the Cmps-SCL of first microprocessor U4 and is connected; One end of 18 resistance is connected with digital power DVCC, and the other end is held with the Cmps-SDA of first microprocessor U4 and is connected; One end of 29 electric capacity C29 is held with the SETP of the one or three number of axle word magnetoresistive transducer U8 and is connected, and the other end is held with the SETC of the one or three number of axle word magnetoresistive transducer U8 and is connected; One end of 30 electric capacity C30 is held with the CI of the one or three number of axle word magnetoresistive transducer U8 and is connected, the other end be digitally connected; 31 electric capacity C31 one end is connected with the VDDIO of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with digitally DGND; One end of 32 electric capacity C32 is connected with the VDD of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with digitally DGND; The vdd terminal of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The VDDIO end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The SI end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; All GND end of the one or three number of axle word magnetoresistive transducer U8 is all connected with digitally DGND.

The model of the one or three number of axle word magnetoresistive transducer U8 that the present invention adopts is HMC5883L, it is a high integration module, for locking flight course, carry three axle magnetoresistive transducers, amplifier, autodegauss driver, 12 ADC can control this module and reach 1 ° ~ 2 ° in strong magnetic field circumstance precision, can deviation calibration, clever lightness is high, good reliability.Have desirable low-voltage power supply and ultralow Consumption, save aircraft work power consumption, applicable aircraft battery is powered.

As shown in Figure 7, described GPS positioning navigation module comprises a GPS integrated chip U9, the 19 resistance R19, the 20 resistance R20, the 21 resistance R21, the 22 resistance R22, the 33 electric capacity C33, the 34 electric capacity C34, the 35 electric capacity C35, the 36 electric capacity C36, the 37 electric capacity C37, the second inductance L 2, the 3rd inductance L 3, the 4th light emitting diode DS4, the second Schottky Rectifier D2, the 3rd Schottky Rectifier D3, the second reserve battery BT2 and the first ceramic antenna E1; One end of 19 resistance R19 is held with the PPS of a GPS integrated chip U9 and is connected, and the other end is connected with the 4th light emitting diode DS4; One end of 4th light emitting diode DS4 is connected with the 19 resistance R19, and the other end is connected with digitally DGND; One end of 20 resistance is connected with the TXA of a GPS integrated chip U9, and the other end is held with the PA3 of first microprocessor U4 and is connected; One end of 21 resistance R21 is connected with the DXA of a GPS integrated chip U9, and the other end is held with the PA2 of first microprocessor U4 and is connected; One end of 22 resistance R22 is connected with the positive pole of the second reserve battery BT2, and the other end is held with the VBAT of a GPS integrated chip U9 and is connected; One end of 33 electric capacity C33 is held with the PA3 of first microprocessor U4 and is connected, and the other end is connected with digitally DGND; One end of 34 electric capacity is held with the PA2 of first microprocessor U4 and is connected, and the other end is connected with digitally DGND; One end of 35 electric capacity C35 is held with the VCC of a GPS integrated chip U9 and is connected, and the other end is connected with one end of the second inductance L 2; One end of second inductance L 2 is connected with the 35 electric capacity C35, the other end be digitally connected; One end of 36 electric capacity C6 is held with the VCC of a GPS integrated chip U9 and is connected, and the other end is connected with one end of the second inductance L 2; One end of 3rd inductance L 3 is held with the VCC of a GPS integrated chip U9 and is connected, and the other end is connected with digital power DVCC; One end of 37 electric capacity C37 is connected with digital power DVCC, and the other end is connected with digitally DGND; The RF_IN end of the one GPS integrated chip U9 is connected with the first ceramic antenna E1; All GND end of the one GPS integrated chip U9 is all connected with digitally DGND; The positive pole of the second Schottky Rectifier D2 is held with the VBAT of a GPS integrated chip U9 and is connected, and negative pole is connected with the positive pole of the second reserve battery BT2; The negative pole of the second reserve battery BT2 is connected with digitally DGND; The positive pole of the 3rd Schottky Rectifier D3 is held with the VBAT of a GPS integrated chip U9 and is connected, and negative pole is held with the VCC of a GPS integrated chip U9 and is connected; All NC ends of the one GPS integrated chip U9 are all unsettled.

The model of the one GPS integrated chip U9 is VK1613, adopt SiRF third generation high sensitivity, low power consumption chip StarIII, built-in ARM7TDMI CPU, search and computing satellite signals ability stronger, support the wide pressure power supply of 3V ~ 5V, operating temperature range is large, height above sea level is used to be less than 18000 meters, precision is 2.2 meters of circumference errors, possesses the ability of quick position and tracking 20 satellites, get final product accurate positioning aircraft in conjunction with digital compass, provide accurate position data, as elements of a fix information, present satellites information, three-dimensional velocity information.

As shown in Figure 8, radio receiving transmitting module comprises the first high speed wireless data receiving and transmitting integrated module JP1; 1 end of the first high speed wireless data receiving and transmitting integrated module JP1 is connected with digitally DGND; 2 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with digital power DVCC; 3 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CE of first microprocessor U4; 4 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CSN of first microprocessor U4; 5 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-SCK of first microprocessor U4; 6 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MOSI of first microprocessor U4; 7 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MISO of first microprocessor U4; 8 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-IRQ of first microprocessor U4.

Acp chip model in the first high speed wireless data receiving and transmitting integrated module JP1 selected by the present invention is nRF24L01.This chip uses SPI interface and processor communication, adopts Enhanced ShockBurst technology, and supports 2Mbps high-speed transfer, and reliable communication distance can reach about 600 meters farthest.And only at control microcomputer end, single-chip microcomputer need be used to communicate with equal modules and get final product real-time reception, bidding protocol can use RS232/RS485 form, and command mode is with reference to conventional AT order.

As shown in Figure 9, serial ports/SWD debug i/f circuit comprises first serial debugging interface JP2, a SWD debugging interface JP3; 1 end of first serial debugging interface JP2 is connected with+5V power supply; 2 ends of first serial debugging interface JP2 are held with the UART1-TX of first microprocessor U4 and are connected; 3 ends of first serial debugging interface JP2 are held with the UART1-RX of first microprocessor U4 and are connected; 4 ends of first serial debugging interface JP2 are connected with digitally DGND; 1 end of the one SWD debugging interface U5 is connected with digital power DVCC; 2 ends of the one SWD debugging interface JP3 are held with the SWDIO of first microprocessor U4 and are connected; 3 ends of the one SWD debugging interface JP3 are held with the SWDCLK of first microprocessor U4 and are connected; 4 ends of the one SWD debugging interface JP3 are connected with digitally DGND.

The present invention adopts SWD interface can on-line debugging aircraft, and programming program is to first microprocessor U3, to save IO resource for the input of each road sampling module signal.And the serial ports 1 of the STM32 reserved, data observation and the Function Extension of being convenient to debug process need to use.

As shown in Figure 10, signal input/output interface comprises remote signal input interface, four-way throttle signal output interface and function conversion keys circuit.

Remote signal input interface comprises the first remote signal input interface JP8; 1 end of the first remote signal input interface JP8 is connected with digitally DGND; 2 ends of the first remote signal input interface JP8 are connected with+5V power supply; 3 ends of the first remote signal input interface JP8 are connected with the Rev-PPM of first microprocessor U3.

Four-way throttle signal output interface comprises the first signal output interface JP4, secondary signal output interface JP5, the 3rd signal output interface JP6 and the 4th signal output interface JP7; 1 end of the first signal output interface JP4 is connected with the PWM-CH1 of first microprocessor U4; 3 ends of secondary signal output interface JP4 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP4 are unsettled; 1 end of secondary signal output interface JP5 is connected with the PWM-CH2 of first microprocessor U4; 3 ends of secondary signal output interface JP5 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP5 are unsettled; 1 end of the 3rd signal output interface JP6 is connected with the PWM-CH3 of first microprocessor U4; 3 ends of the 3rd signal output interface JP6 are connected with power supply ground DGND; 2 ends of the 3rd signal output interface JP6 are unsettled; 1 end of the 4th signal output interface JP7 is connected with the PWM-CH4 of first microprocessor U4; 3 ends of the 4th signal output interface JP7 are connected with power supply ground DGND; 2 ends of the 4th signal output interface JP7 are unsettled.

Function conversion keys circuit comprises the 9th resistance R9, the tenth resistance R10, second switch button S2 and the 3rd switch key S3; One end of 9th resistance R9 is held with the KEY1 of first micro-U4 of process and is connected, and the other end is connected with the second button S2; One end of second button S2 is connected with the 9th resistance R9, and the other end is connected with digitally DGND; One end of tenth resistance R10 is held with the KEY2 of first micro-U4 of process and is connected, and the other end is connected with the 3rd button 3; One end of 3rd button S3 is connected with the tenth resistance R10, and the other end is connected with digitally DGND.

When aircraft system mode is self-navigation pattern, first microprocessor U4 processes in real time, merge each sensing data, directly outputs to each road electron speed regulator by four-way throttle signal output interface and changes motor speed, control aircraft course; When aircraft system mode switches to Non-follow control, the remote signal of PPM modulation is input to microprocessor U4 by the first remote signal input interface JP8, after first microprocessor process, output to each road electron speed regulator with PWM drive singal by four-way throttle signal output interface, thus change brushless motor speed increase or reduce.

Finally illustrate, only more than describe that unrestricted its comprises scope in order to technical scheme of the present invention to be described, namely technical scheme of the present invention modified or equivalent to replace, and not departing from its object and scope, all should be covered by the middle of right of the present invention.

Claims

1. based on the self-navigation flight control system of cross flow fan, comprise power supply module, microprocessor module, fuselage gesture stability module, flying height detection module, digital compass module, wireless data transceiver module, GPS positioning navigation module, serial ports/SWD debug i/f circuit and signal input/output interface, it is characterized in that: fuselage gesture stability module, flying height detection module, digital compass module, GPS positioning navigation module are connected with microprocessor module by universal serial bus with wireless data transceiver module; Power supply module is microprocessor module, fuselage gesture stability module, flying height detection module, radio receiving transmitting module, serial ports/SWD debug i/f circuit and fuselage state indicating circuit provide working power;

Described power supply module comprises+5V Power convert mu balanced circuit, analog power switch voltage-stabilizing circuit, digital power conversion mu balanced circuit, electric quantity detecting circuit, fuselage state indicating circuit and filtering antijamming circuit;

Described+5V Power convert mu balanced circuit comprises the first switching type power supply conversion chip U1, the first Schottky Rectifier D1, the first stabilizing inducatnce L1, the first resistance R1, the second resistance R2, the 9th electric capacity C9, the tenth electric capacity C10, the 11 electric capacity C11 and the 12 electric capacity C12; + VIN the end of the first switching type power supply conversion chip U1 is connected with driving power PVCC; The GND of the first switching type power supply conversion chip U1 is connected with power supply ground PGND; First switching type power supply conversion chip U1's hold and be connected with power supply ground PGND; One end of first Schottky Rectifier D1 is held with the OUT of the first switching type power supply conversion chip U1 and is connected, and the other end is connected with power supply ground PGND; One end of first stabilizing inducatnce L1 is held with the OUT of the first switching type power supply conversion chip U1 and is connected, and the other end is connected with+5V; First resistance R1 one end is connected with+5V, and the other end is held with the FB of the first switching type power supply conversion chip U1 and is connected; Second resistance R2 one end is connected with power supply ground PGND, and the other end is held with the FB of the first switching type power supply conversion chip U1 and is connected; 9th electric capacity R9 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; Tenth electric capacity R10 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; 11 electric capacity R11 one end is connected with+5V, and the other end is connected with power supply ground PGND; 12 electric capacity R12 one end is connected with+5V, and the other end is connected with power supply ground PGND;

The model of described first switching type power supply conversion chip U1 is LM2596-ADJ, and the model of the first Schottky Rectifier D1 is SS34;

Described analog power switch voltage-stabilizing circuit comprises the second linear voltage and regulates chip U3, the second electric capacity C2, the 6th electric capacity C6, the 7th electric capacity C7, the 8th electric capacity C8 and the 4th resistance R4; Second linear voltage regulates the VIN of chip U3 end to be connected with+5V; Second linear voltage regulates the GND of chip U3 end to be connected with AGND in analog; Second linear voltage regulates the VOUT of chip U3 end to be connected with analog power AVCC; The positive pole of the second electric capacity C2 is connected with+5V, and negative pole is connected with AGND in analog; One end of 6th electric capacity C6 is connected with+5V, and the other end is connected with AGND in analog; One end of 7th electric capacity C7 is connected with analog power AVCC, and the other end is connected with AGND in analog; One end of 8th electric capacity C8 is connected with analog power AVCC, and the other end is connected with AGND in analog; 4th resistance R4 one end and power supply ground PGND is connected, and the other end is connected with AGND in analog;

Described digital power conversion mu balanced circuit comprises the first linear voltage-regulation chip U2, the first electric capacity C1, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5 and the 3rd resistance R3; The VIN end of the first linear voltage-regulation chip U2 is connected with+5V; The GND end of the first linear voltage-regulation chip U2 is connected with digitally DGND; The VOUT end of the first linear voltage-regulation chip U2 is connected with digital power DVCC; The positive pole of the first electric capacity C1 is connected with+5V, and negative pole is connected with digitally DGND; One end of 3rd electric capacity C3 is connected with+5V, and the other end is connected with digitally DGND; One end of 4th electric capacity C4 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 5th electric capacity C5 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 3rd resistance R3 is connected with power supply ground PGND, and the other end is connected with digitally DGND;

Described first linear voltage-regulation chip U2 and the second linear voltage regulate the model of chip U3 to be LM1117-3.3;

Described electric quantity detecting circuit comprises the 23 resistance R23, the 24 resistance R24; 24 resistance R24 one end is connected with driving power PVCC, and the other end is held with the VBAT-CH of first microprocessor U4 and is connected; 23 resistance R23 one end is held with the VBAT-CH of first microprocessor U4 and is connected, and the other end is connected with power supply ground PGND;

Described fuselage state indicating circuit comprises the first hummer LS1, the first triode Q1, the first light emitting diode DS1, the second light emitting diode DS2, the 3rd light emitting diode DS3, the 11 resistance R11, the 12 resistance R12, the 13 resistance R13 and the 14 resistance R14; The positive pole of the first hummer is connected with analog power AVCC, and negative pole is connected with the collector of the first triode Q1; One end of 14 resistance R14 is connected with the base stage of the first triode Q1, and the other end is held with the BELL of first microprocessor U4 and is connected; The emitter of the first triode Q1 is connected with AGND in analog; One end of 11 resistance R11 is connected with+5V power supply, and the other end is connected with the positive pole of the first light emitting diode DS1; The negative pole of the first light emitting diode DS1 is connected with power supply ground PGND; One end of 12 resistance R12 is connected with digital power DVCC, and the other end is connected with the positive pole of the second light emitting diode DS2; The negative pole of the second light emitting diode DS2 is held with the LED1 of first microprocessor U3 and is connected; One end of 13 resistance R13 is connected with analog power AVCC, and the other end is connected with the positive pole of the 3rd light emitting diode DS3; The negative pole of the 3rd light emitting diode DS3 is held with the LED2 of first microprocessor U4 and is connected;

The model of described first triode Q1 is 8050;

Described filtering antijamming circuit comprises the 18 electric capacity C18, the 19 electric capacity C19, the 20 electric capacity C20, the 21 electric capacity C21, the 22 electric capacity C22, the 23 electric capacity C23, the 24 electric capacity C24 and the 25 electric capacity C25; One end of 18 electric capacity C18 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 19 electric capacity C19 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 20 electric capacity C20 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 20 electric capacity C20 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 21 electric capacity C21 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 22 electric capacity C22 is connected with digital power DVCC, and the other end is connected with digitally DGND; One end of 23 electric capacity C23 is connected with analog power AVCC, and the other end is connected with AGND in analog; One end of 24 electric capacity C24 is connected with analog power AVCC, and the other end is connected with AGND in analog; One end of 25 electric capacity C25 is connected with analog power AVCC, and the other end is connected with AGND in analog;

Described microprocessor module comprises first microprocessor U4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 13 electric capacity C13, the 14 electric capacity C14, the 15 electric capacity C15, the 16 electric capacity C16, the 17 electric capacity C17, the first crystal oscillator Y1, the second crystal oscillator Y2, the first button S1 and the first reserve battery BT1; One end of 5th resistance R5 is connected with digital power DVCC, and the other end is connected with the NSRT of first microprocessor U4; One end of 7th resistance R7 is connected with digitally DGND, and the other end is connected with the BOOT1 of first microprocessor U4; 8th resistance R8 one end is connected with digitally DGND, and the other end is connected with the BOOT0 of first microprocessor U4; 6th resistance R6 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; 16 electric capacity C16 one end is connected with the OSC-OUT of first microprocessor U4, and the other end is connected with digitally DGND; 17 electric capacity C17 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with digitally DGND; 15 electric capacity C15 one end is connected with the NSRT of first microprocessor U4, and the other end is connected with digitally DGND; 13 electric capacity C13 one end is connected with the OSC32-OUT of first microprocessor U4, and the other end is connected with digitally GDND; 14 electric capacity C14 is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with digitally DGND; First crystal oscillator Y1 one end is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with the OSC32-OUT of first microprocessor U4; Second crystal oscillator Y2 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; First button S1 one end is connected with the NSRT of first microprocessor U4, and the other end is connected with digitally DGND; First reserve battery BT1 one end is connected with the VBAT of first microprocessor U4, and the other end is connected with digitally DGND; VDD_1 ~ the VDD_4 of first microprocessor U4 is connected with digital power DVCC; The VDDA end of first microprocessor U4 is connected with analog power AVCC; The VSSA end of first microprocessor U4 is connected with AGND in analog; VSS_1 ~ VSS_4 end of first microprocessor U4 is connected with digitally DGND;

The model of described first microprocessor U4 is STM32F101RBT6;

Described fuselage gesture stability module comprises fuselage three axis angular rate detection module and fuselage three axial rake detection module;

Fuselage three axis angular rate detection module comprises the first angular velocity detection unit U5, the 26 electric capacity C26 and the 27 electric capacity C27; The VDDIO end of the first angular velocity detection unit U5 is connected with digital power DVCC; The SCL/SPC end of the first angular velocity detection unit U5 is held with the Gyro-SPC of first microprocessor U4 and is connected; The SDA/SDI/SDO end of the first angular velocity detection unit U5 is held with the Gyro-SDI of first microprocessor U4 and is connected; The SDO/SA0 end of the first angular velocity detection unit U5 is held with the Gyro-SDO of first microprocessor U4 and is connected; The CS end of the first angular velocity detection unit U5 is held with the Gyro-CS of first microprocessor U4 and is connected; The DR/INT2 end of the first angular velocity detection unit U5 is held with the Gyro-DR of first microprocessor U4 and is connected; 8 ~ No. 12 pins of the first angular velocity detection unit U5 are RESERVED end, are connected with digitally DGND; The GND end of the first angular velocity detection unit U5 is connected with digitally DGND; No. 15 pins of the first angular velocity detection unit U5 are that RESERVED end is connected with digital power DVCC; The vdd terminal of the first angular velocity detection unit U5 is connected with digital power DVCC; 26 electric capacity C26 one end is connected with digital power DVCC, and the other end is connected with digitally DGND; 27 electric capacity C27 one end is connected with digital power DVCC, and the other end is connected with digitally DGND;

The model of described first angular velocity detection unit U5 is L3G4200D;

Fuselage three axial rake detection module comprises the first inclination angle acceleration detecting unit U6; The 5V end of the first inclination angle acceleration detecting unit U6 is connected with+5V power supply; The GND end of the first inclination angle acceleration detecting unit U6 is connected with AGND in analog; Xout end, the Yout end of the first inclination angle acceleration detecting unit U6 are connected with Acce-Z with Acce-X, Acce-Y of first microprocessor U4 respectively with Zout end; The SL end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS2 of first microprocessor U4; The 0G end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-0G of first microprocessor U4; The ST end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS1 of first microprocessor U4; The GS end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-MODE of first microprocessor U4;

Described flying height detection module comprises the first digital gas pressure sensor U7, the 15 resistance R15 and the 16 resistance R16; 15 resistance R15 one end is connected with digital power DVCC, and the other end is connected with the Altimeter-SDA of the first digital gas pressure sensor U7; 16 resistance R16 one end is connected with digital power DVCC, and the other end is connected with the Altimeter-SCL of the first digital gas pressure sensor U7; The GND end of the first digital gas pressure sensor U7 is connected with digitally DGND; The EOC end of the first digital gas pressure sensor U7 is connected with the Altimeter-EOC of first microprocessor U4; The VDDA end of the first digital gas pressure sensor U7 is connected with analog power AVCC; The VDDD end of the first digital gas pressure sensor U7 is connected with digital power DVCC; The XCLR end of the first digital gas pressure sensor U7 is connected with the Altimeter-XCLR of first microprocessor U4; The NC end of the first digital gas pressure sensor U7 is unsettled;

The model of described first digital gas pressure sensor U7 is BMP085;

Described digital compass module comprises the one or three number of axle word magnetoresistive transducer U8, the 17 resistance R17, the 18 resistance R18, the 29 electric capacity C29, the 30 electric capacity C30, the 31 electric capacity C31 and the 32 electric capacity C32; One end of 17 resistance is connected with digital power DVCC, and the other end is held with the Cmps-SCL of first microprocessor U4 and is connected; One end of 18 resistance is connected with digital power DVCC, and the other end is held with the Cmps-SDA of first microprocessor U4 and is connected; One end of 29 electric capacity C29 is held with the SETP of the one or three number of axle word magnetoresistive transducer U8 and is connected, and the other end is held with the SETC of the one or three number of axle word magnetoresistive transducer U8 and is connected; One end of 30 electric capacity C30 is held with the CI of the one or three number of axle word magnetoresistive transducer U8 and is connected, the other end be digitally connected; 31 electric capacity C31 one end is connected with the VDDIO of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with digitally DGND; One end of 32 electric capacity C32 is connected with the VDD of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with digitally DGND; The vdd terminal of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The VDDIO end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The SI end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; All GND end of the one or three number of axle word magnetoresistive transducer U8 is all connected with digitally DGND;

The model of described one or three number of axle word magnetoresistive transducer U8 is HMC5883L;

Described GPS positioning navigation module comprises a GPS integrated chip U9, 19 resistance R19, 20 resistance R20, 21 resistance R21, 22 resistance R22, 33 electric capacity C33, 34 electric capacity C34, 35 electric capacity C35, 36 electric capacity C36, 37 electric capacity C37, second inductance L 2, 3rd inductance L 3, 4th light emitting diode DS4, second Schottky Rectifier D2, 3rd Schottky Rectifier D3, second reserve battery BT2 and the first ceramic antenna E1, one end of 19 resistance R19 is connected with the PPS of a GPS integrated chip U9, and the other end is connected with the 4th light emitting diode DS4, one end of 4th light emitting diode DS4 is connected with the 19 resistance R19, and the other end is connected with digitally DGND, one end of 20 resistance is connected with the TXA of a GPS integrated chip U9, and the other end is held with the PA3 of first microprocessor U4 and is connected, one end of 21 resistance R21 is connected with the DXA of a GPS integrated chip U9, and the other end is held with the PA2 of first microprocessor U4 and is connected, one end of 22 resistance R22 is connected with the positive pole of the second reserve battery BT2, and the other end is held with the VBAT of a GPS integrated chip U9 and is connected, one end of 33 electric capacity C33 is held with the PA3 of first microprocessor U4 and is connected, and the other end is connected with digitally DGND, one end of 34 electric capacity is held with the PA2 of first microprocessor U4 and is connected, and the other end is connected with digitally DGND, one end of 35 electric capacity C35 is held with the VCC of a GPS integrated chip U9 and is connected, and the other end is connected with one end of the second inductance L 2, one end of second inductance L 2 is connected with the 35 electric capacity C35, the other end be digitally connected, one end of 36 electric capacity C6 is held with the VCC of a GPS integrated chip U9 and is connected, and the other end is connected with one end of the second inductance L 2, one end of 3rd inductance L 3 is held with the VCC of a GPS integrated chip U9 and is connected, and the other end is connected with digital power DVCC, one end of 37 electric capacity C37 is connected with digital power DVCC, and the other end is connected with digitally DGND, the RF_IN end of the one GPS integrated chip U9 is connected with the first ceramic antenna E1, all GND end of the one GPS integrated chip U9 is all connected with digitally DGND, the positive pole of the second Schottky Rectifier D2 is held with the VBAT of a GPS integrated chip U9 and is connected, and negative pole is connected with the positive pole of the second reserve battery BT2, the negative pole of the second reserve battery BT2 is connected with digitally DGND, the positive pole of the 3rd Schottky Rectifier D3 is held with the VBAT of a GPS integrated chip U9 and is connected, and negative pole is held with the VCC of a GPS integrated chip U9 and is connected, all NC ends of the one GPS integrated chip U9 are all unsettled,

The model of a described GPS integrated chip U9 is VK2525;

Described radio receiving transmitting module comprises the first high speed wireless data receiving and transmitting integrated module JP1; 1 end of the first high speed wireless data receiving and transmitting integrated module JP1 is connected with digitally DGND; 2 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with digital power DVCC; 3 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CE of first microprocessor U4; 4 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CSN of first microprocessor U4; 5 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-SCK of first microprocessor U4; 6 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MOSI of first microprocessor U4; 7 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MISO of first microprocessor U4; 8 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-IRQ of first microprocessor U4;

Acp chip model in described first high speed wireless data receiving and transmitting integrated module JP1 is nRF24L01;

Described serial ports/SWD debug i/f circuit comprises first serial debugging interface JP2, a SWD debugging interface JP3; 1 end of first serial debugging interface JP2 is connected with+5V power supply; 2 ends of first serial debugging interface JP2 are held with the UART1-TX of first microprocessor U4 and are connected; 3 ends of first serial debugging interface JP2 are held with the UART1-RX of first microprocessor U4 and are connected; 4 ends of first serial debugging interface JP2 are connected with digitally DGND; 1 end of the one SWD debugging interface U5 is connected with digital power DVCC; 2 ends of the one SWD debugging interface JP3 are held with the SWDIO of first microprocessor U4 and are connected; 3 ends of the one SWD debugging interface JP3 are held with the SWDCLK of first microprocessor U4 and are connected; 4 ends of the one SWD debugging interface JP3 are connected with digitally DGND;

Described signal input/output interface comprises remote signal input interface, four-way throttle signal output interface and function conversion keys circuit;

Described remote signal input interface comprises the first remote signal input interface JP8; 1 end of the first remote signal input interface JP8 is connected with digitally DGND; 2 ends of the first remote signal input interface JP8 are connected with+5V power supply; 3 ends of the first remote signal input interface JP8 are connected with the Rev-PPM of first microprocessor U3;

Described four-way throttle signal output interface comprises the first signal output interface JP4, secondary signal output interface JP5, the 3rd signal output interface JP6 and the 4th signal output interface JP7; 1 end of the first signal output interface JP4 is connected with the PWM-CH1 of first microprocessor U4; 3 ends of secondary signal output interface JP4 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP4 are unsettled; 1 end of secondary signal output interface JP5 is connected with the PWM-CH2 of first microprocessor U4; 3 ends of secondary signal output interface JP5 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP5 are unsettled; 1 end of the 3rd signal output interface JP6 is connected with the PWM-CH3 of first microprocessor U4; 3 ends of the 3rd signal output interface JP6 are connected with power supply ground DGND; 2 ends of the 3rd signal output interface JP6 are unsettled; 1 end of the 4th signal output interface JP7 is connected with the PWM-CH4 of first microprocessor U4; 3 ends of the 4th signal output interface JP7 are connected with power supply ground DGND; 2 ends of the 4th signal output interface JP7 are unsettled;