CN203025564U

CN203025564U - Automatic navigation flight control system based on cross-flow fan

Info

Publication number: CN203025564U
Application number: CN 201220747247
Authority: CN
Inventors: 陈云; 胡琦逸; 邹洪波; 孔亚广; 赵晓东
Original assignee: Hangzhou Dianzi University
Current assignee: Hangzhou Dianzi University
Priority date: 2012-12-28
Filing date: 2012-12-28
Publication date: 2013-06-26
Anticipated expiration: 2022-12-28

Abstract

The utility model relates to an automatic navigation flight control system based on a cross-flow fan. The automatic navigation flight control system based on the cross-flow fan comprises a power supply module, a micro processor module, a machine body posture control module, a flight height detection module, a digital compass module, a wireless data receiving and dispatching module, a GPS (global positioning system) positioning navigation module, a serial port/SWD (supersonic wave drive) debugging interface circuit and a signal input/output interface. The machine posture control module, the flight height detection module, the digital compass module, the GPS navigation module and the wireless data receiving and dispatching module are connected with the micro processing module through a serial bus; and the power supply module provides operating power supply for the micro processor module, the machine body posture control module, the flight height detection module, the wireless receiving and dispatching module, the serial port/SWD debugging interface circuit and a machine body state indicating circuit. The automatic navigation flight control system based on the cross-flow fan integrates the machine body posture control, the flight height detection, wireless receiving and dispatching and the like, and the machine body flight has reliable stability and compatibility.

Description

A kind of self-navigation flight control system based on cross flow fan

Technical field

The utility model belongs to the signal detection technique field, relates to a kind of four-axle aircraft automatic navigation control system for cross flow fan.

Background technology

Cross flow fan, claim again crossflow fan, it is a special blower fan of class, impeller is multi-blade type, oval tubular, has forward multiple wing shape blade, have simple in structure, volume is little, the air-flow that produces steadily, the dynamic pressure coefficient is than high, recently is widely used in the occasion of the low pressure ventilations ventilations such as household electrical appliance and air-conditioning equipment.Cross flow fan has multinomial advantage than rotor as type of drive: because axial length is unrestricted, can select arbitrarily according to different use needs the length of impeller, motivation of adjustment; The permeate gas stream impeller flows, and is subjected to the effect of twice power of blade, thereby the energy reach is farther; Without turbulent flow, air-out is even; Blade can be protected in the air channel, prevents that also blade is hurted sb.'s feelings in-flight; The series of characteristics such as that four axle rotor crafts have is non-linear, strong coupling, very complicated and special dynamics and flight attitude, the problem such as elastic deformation, vibration, fuselage spin that can cause rotor, and stablizing of cross flow fan wind characteristic, makes the impact of these problems no longer obvious.

External many colleges and universities, research institution and commercial undertaking mainly carry out a large amount of intensive research and explorations to multi-rotor aerocraft and application thereof at present, but are main mainly with four axle rotor crafts; And domestic, all rarely have about the multi-rotor aerocraft report at scientific research or commercial field, say nothing of based on cross flow fan as power-actuated four-axle aircraft.Although some relative complete functions occurred on the market, the aircraft control panel of technology maturation, but be the many rotors four-axle aircraft for the model airplane fan also, wherein mostly use low-cost, coarse sensor, be difficult to reach precision and the reliability of professional inertial guidance unit, thereby can't satisfy actual requirement at external force resistance disturbance, the aspect such as handling.Simultaneously, these products often do not possess or only possess very simple navigate mode, only can use remote manual control to control flight in the visual range of naked eyes, and potential commercial value and practical value also are developed far away.

Summary of the invention

The deficiency of the unmanned self-navigation of aircraft that the utility model drives cross flow fan for existing flight control system, functional development and the support such as cruise, make a return voyage provides a kind of four-axle aircraft automatic navigation control system for cross flow fan.

The technical scheme that the utility model technical solution problem adopts is:

The utility model comprises power supply module, microprocessor module, fuselage attitude control module, flying height detection module, digital compass module, wireless data transceiver module, GPS positioning navigation module, serial ports/SWD debug i/f circuit and signal input/output interface.Fuselage attitude control module, flying height detection module, digital compass module, GPS positioning navigation module are connected universal serial bus and are connected with microprocessor module with wireless data transceiver module; The power supply module is that microprocessor module, fuselage attitude control module, flying height detection module, radio receiving transmitting module, serial ports/SWD debug i/f circuit and fuselage state indicating circuit provide working power.

Described power supply module comprises+5V power supply switch voltage-stabilizing circuit, analog power switch voltage-stabilizing circuit, digital power conversion mu balanced circuit, electric quantity detecting circuit, fuselage state indicating circuit and filtering antijamming circuit.

Described+5V power-switching circuit comprises the first switching type power supply conversion chip U1, the first Schottky Rectifier D1, the first stabilizing inducatnce L1, the first resistance R 1, the second resistance R 2, the 9th capacitor C 9, the tenth capacitor C 10, the 11 capacitor C 11 and the 12 capacitor C 12; The first switching type power supply conversion chip U1+VIN end is connected with driving power PVCC; The GND of the first switching type power supply conversion chip U1 is connected with power supply ground PGND; The first switching type power supply conversion chip U1's / OFF end is connected with power supply ground PGND; The end of the first Schottky Rectifier D1 is connected with the OUT end of the first switching type power supply conversion chip U1, and the other end is connected with power supply ground PGND; The OUT end of the end of the first stabilizing inducatnce L1 and the first switching type power supply conversion chip U1 is connected, and the other end is connected with+5V; The first resistance R 1 one ends are connected with+5V, and the other end is connected with the FB end of the first switching type power supply conversion chip U1; The second resistance R 2 one ends are connected with power supply ground PGND, and the other end is connected with the FB end of the first switching type power supply conversion chip U1; The 9th electric capacity R9 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; The tenth electric capacity R10 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; The 11 electric capacity R11 one end is connected with+5V, and the other end is connected with power supply ground PGND; The 12 electric capacity R12 one end is connected with+5V, and the other end is connected with power supply ground PGND.

The model of described the first switching type power supply conversion chip U1 is LM2596-ADJ, and the model of the first Schottky Rectifier D1 is SS34.

Described analog power change-over circuit comprises the second linear voltage adjusting chip U3, the second capacitor C 2, the 6th capacitor C 6, the 7th capacitor C 7, the 8th capacitor C 8 and the 4th resistance R 4; The VIN end that the second linear voltage is regulated chip U3 is connected with+5V; The GND end that the second linear voltage is regulated chip U3 is connected with simulation ground AGND; The VOUT end that the second linear voltage is regulated chip U3 is connected with analog power AVCC; The positive pole of the second capacitor C 2 is connected with+5V, and negative pole is connected with simulation ground AGND; One end of the 6th capacitor C 6 is connected with+5V, and the other end is connected with simulation ground AGND; One end of the 7th capacitor C 7 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; One end of the 8th capacitor C 8 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; The 4th resistance R 4 one ends are connected with power supply ground PGND, and the other end is connected with simulation ground AGND.

Described digital power conversion circuit comprises the first linear voltage-regulation chip U2, the first capacitor C 1, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5 and the 3rd resistance R 3; The VIN of the first linear voltage-regulation chip U2 end is connected with+5V; The GND of the first linear voltage-regulation chip U2 end is connected with DGND digitally; The VOUT end of the first linear voltage-regulation chip U2 is connected with digital power DVCC; The positive pole of the first capacitor C 1 is connected with+5V, and negative pole is connected with DGND digitally; One end of the 3rd capacitor C 3 is connected with+5V, and the other end is connected with DGND digitally; One end of the 4th capacitor C 4 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 5th capacitor C 5 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 3rd resistance R 3 is connected with power supply ground PGND, and the other end is connected with DGND digitally.

The model that the described first linear voltage-regulation chip U2 and the second linear voltage are regulated chip U3 is LM1117-3.3.

Described electric quantity detecting circuit comprises the 23 resistance R 23, the 24 resistance R 24; The 24 resistance R 24 1 ends are connected with driving power PVCC, and the other end is connected with the VBAT-CH end of first microprocessor U4; The 23 resistance R 23 1 ends are connected with the VBAT-CH end of first microprocessor U4, and the other end is connected with power supply ground PGND.

Described fuselage state indicating circuit comprises the first hummer LS1, the first triode Q1, the first light emitting diode DS1, the second light emitting diode DS2, the 3rd light emitting diode DS3, the 11 resistance R 11, the 12 resistance R 12, the 13 resistance R 13 and the 14 resistance R 14; The positive pole of the first hummer is connected with analog power AVCC, and negative pole is connected with the collector of the first triode Q1; One end of the 14 resistance R 14 is connected with the base stage of the first triode Q1, and the other end is connected with the BELL end of first microprocessor U4; The emitter of the first triode Q1 is connected with simulation ground AGND; One end of the 11 resistance R 11 is connected with+5V power supply, and the other end is connected with the positive pole of the first light emitting diode DS1; The negative pole of the first light emitting diode DS1 is connected with power supply ground PGND; One end of the 12 resistance R 12 is connected with digital power DVCC, and the other end is connected with the positive pole of the second light emitting diode DS2; The negative pole of the second light emitting diode DS2 is connected with the LED1 end of first microprocessor U3; One end of the 13 resistance R 13 is connected with analog power AVCC, and the other end is connected with the positive pole of the 3rd light emitting diode DS3; The negative pole of the 3rd light emitting diode DS3 is connected with the LED2 end of first microprocessor U4.The model of described the first triode Q1 is 8050.

Described filtering antijamming circuit comprises the 18 capacitor C 18, the 19 capacitor C 19, the 20 capacitor C 20, the 21 capacitor C 21, the 22 capacitor C 22, the 23 capacitor C 23, the 24 capacitor C 24 and the 25 capacitor C 25; One end of the 18 capacitor C 18 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 19 capacitor C 19 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 20 capacitor C 20 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 20 capacitor C 20 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 21 capacitor C 21 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 22 capacitor C 22 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 23 capacitor C 23 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; One end of the 24 capacitor C 24 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; One end of the 25 capacitor C 25 is connected with analog power AVCC, and the other end is connected with simulation ground AGND.

Described microprocessor module comprises first microprocessor U4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 13 capacitor C 13, the 14 capacitor C 14, the 15 capacitor C 15, the 16 capacitor C 16, the 17 capacitor C 17, the first crystal oscillator Y1, the second crystal oscillator Y2, the first button S1 and the first reserve battery BT1; One end of the 5th resistance R 5 is connected with digital power DVCC, and the other end is connected with the NSRT of first microprocessor U4; One end of the 7th resistance R 7 is connected with DGND digitally, and the other end is connected with the BOOT1 of first microprocessor U4; The 8th resistance R 8 one ends are connected with DGND digitally, and the other end is connected with the BOOT0 of first microprocessor U4; The 6th resistance R 6 one ends are connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; The 16 capacitor C 16 1 ends are connected with the OSC-OUT of first microprocessor U4, and the other end is connected with DGND digitally; The 17 capacitor C 17 1 ends are connected with the OSC-IN of first microprocessor U4, and the other end is connected with DGND digitally; The 15 capacitor C 15 1 ends are connected with the NSRT of first microprocessor U4, and the other end is connected with DGND digitally; The 13 capacitor C 13 1 ends are connected with the OSC32-OUT of first microprocessor U4, and the other end is connected with GDND digitally; The 14 capacitor C 14 is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with DGND digitally; The first crystal oscillator Y1 one end is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with the OSC32-OUT of first microprocessor U4; The second crystal oscillator Y2 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; The first button S1 one end is connected with the NSRT of first microprocessor U4, and the other end is connected with DGND digitally; The first reserve battery BT1 one end is connected with the VBAT of first microprocessor U4, and the other end is connected with DGND digitally; VDD_1～VDD_4 of first microprocessor U4 is connected with digital power DVCC; The VDDA end of first microprocessor U4 is connected with analog power AVCC; The VSSA end of first microprocessor U4 is connected with simulation ground AGND; The VSS_1 of first microprocessor U4～VSS_4 end is connected with DGND digitally.The model of described first microprocessor U4 is STM32F101RBT6.

Described fuselage attitude control module comprises fuselage three axis angular rate detection modules and fuselage three axial rake detection modules.

Fuselage three axis angular rate detection modules comprise the first angular velocity detection unit U5, the 26 capacitor C 26 and the 27 capacitor C 27; The VDDIO end of the first angular velocity detection unit U5 is connected with digital power DVCC; The SCL/SPC end of the first angular velocity detection unit U5 is connected with the Gyro-SPC end of first microprocessor U4; The SDA/SDI/SDO end of the first angular velocity detection unit U5 is connected with the Gyro-SDI end of first microprocessor U4; The SDO/SA0 end of the first angular velocity detection unit U5 is connected with the Gyro-SDO end of first microprocessor U4; The CS end of the first angular velocity detection unit U5 is connected with the Gyro-CS end of first microprocessor U4; The DR/INT2 end of the first angular velocity detection unit U5 is connected with the Gyro-DR end of first microprocessor U4; 8～No. 12 pins of the first angular velocity detection unit U5 are RESERVED end, are connected with DGND digitally; The GND of the first angular velocity detection unit U5 end is connected with DGND digitally; No. 15 pins of the first angular velocity detection unit U5 are that the RESERVED end is connected with digital power DVCC; The vdd terminal of the first angular velocity detection unit U5 is connected with digital power DVCC; The 26 capacitor C 26 1 ends are connected with digital power DVCC, and the other end is connected with DGND digitally; The 27 capacitor C 27 1 ends are connected with digital power DVCC, and the other end is connected with DGND digitally.The model of described the first angular velocity detection unit U5 is L3G4200D.

Fuselage three axial rake detection modules comprise the first inclination angle acceleration detecting unit U6; The 5V of the first inclination angle acceleration detecting unit U6 end is connected with+5V power supply; The GND end of the first inclination angle acceleration detecting unit U6 is connected with simulation ground AGND; The Xout end of the first inclination angle acceleration detecting unit U6, Yout end and Zout end are connected with Acce-Z with Acce-X, the Acce-Y of first microprocessor U4 respectively; The SL end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS2 of first microprocessor U4; The 0G end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-0G of first microprocessor U4; The ST end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS1 of first microprocessor U4; The GS end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-MODE of first microprocessor U4.

Described flying height detection module comprises the first digital gas pressure sensor U7, the 15 resistance R 15 and the 16 resistance R 16; The 15 resistance R 15 1 ends are connected with digital power DVCC, and the other end is connected with the Altimeter-SDA of the first digital gas pressure sensor U7; The 16 resistance R 16 1 ends are connected with digital power DVCC, and the other end is connected with the Altimeter-SCL of the first digital gas pressure sensor U7; The GND of the first digital gas pressure sensor U7 end is connected with DGND digitally; The EOC end of the first digital gas pressure sensor U7 is connected with the Altimeter-EOC of first microprocessor U4; The VDDA end of the first digital gas pressure sensor U7 is connected with analog power AVCC; The VDDD end of the first digital gas pressure sensor U7 is connected with digital power DVCC; The XCLR end of the first digital gas pressure sensor U7 is connected with the Altimeter-XCLR of first microprocessor U4; The NC end of the first digital gas pressure sensor U7 is unsettled.The model of described the first digital gas pressure sensor U7 is BMP085.

Described digital compass module comprises the one or three number of axle word magnetoresistive transducer U8, the 17 resistance R 17, the 18 resistance R 18, the 29 capacitor C 29, the 30 capacitor C 30, the 31 capacitor C 31 and the 32 capacitor C 32; One end of the 17 resistance is connected with digital power DVCC, and the other end is connected with the Cmps-SCL end of first microprocessor U4; One end of the 18 resistance is connected with digital power DVCC, and the other end is connected with the Cmps-SDA end of first microprocessor U4; One end of the 29 capacitor C 29 is connected with the SETP end of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with the SETC end of the one or three number of axle word magnetoresistive transducer U8; The CI end of one end of the 30 capacitor C 30 and the one or three number of axle word magnetoresistive transducer U8 is connected, the other end with digitally be connected; The 31 capacitor C 31 1 ends are connected with the VDDIO of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with DGND digitally; One end of the 32 capacitor C 32 is connected with the VDD of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with DGND digitally; The vdd terminal of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The VDDIO end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The SI end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; All GND end of the one or three number of axle word magnetoresistive transducer U8 all is connected with DGND digitally.The model of described the one or three number of axle word magnetoresistive transducer U8 is HMC5883L.

described GPS positioning navigation module comprises a GPS integrated chip U9, the 19 resistance R 19, the 20 resistance R 20, the 21 resistance R 21, the 22 resistance R 22, the 33 capacitor C 33, the 34 capacitor C 34, the 35 capacitor C 35, the 36 capacitor C 36, the 37 capacitor C 37, the second inductance L 2, the 3rd inductance L 3, the 4th light emitting diode DS4, the second Schottky Rectifier D2, the 3rd Schottky Rectifier D3, the second reserve battery BT2 and the first ceramic antenna E1, one end of the 19 resistance R 19 is connected with the PPS of a GPS integrated chip U9, and the other end is connected with the 4th light emitting diode DS4, the end of the 4th light emitting diode DS4 is connected with the 19 resistance R 19, and the other end is connected with DGND digitally, one end of the 20 resistance is connected with the TXA of a GPS integrated chip U9, and the other end is connected with the PA3 end of first microprocessor U4, one end of the 21 resistance R 21 is connected with the DXA of a GPS integrated chip U9, and the other end is connected with the PA2 end of first microprocessor U4, one end of the 22 resistance R 22 is connected with the positive pole of the second reserve battery BT2, and the other end is connected with the VBAT end of a GPS integrated chip U9, one end of the 33 capacitor C 33 and the PA3 of first microprocessor U4 end is connected, and the other end is connected with DGND digitally, one end of the 34 electric capacity and the PA2 of first microprocessor U4 end is connected, and the other end is connected with DGND digitally, one end of the 35 capacitor C 35 is connected with the VCC end of a GPS integrated chip U9, and the other end is connected with an end of the second inductance L 2, one end of the second inductance L 2 is connected with the 35 capacitor C 35, the other end with digitally be connected, one end of the 36 capacitor C 6 is connected with the VCC end of a GPS integrated chip U9, and the other end is connected with an end of the second inductance L 2, one end of the 3rd inductance L 3 is connected with the VCC end of a GPS integrated chip U9, and the other end is connected with digital power DVCC, one end of the 37 capacitor C 37 is connected with digital power DVCC, and the other end is connected with DGND digitally, the RF_IN end of the one GPS integrated chip U9 is connected with the first ceramic antenna E1, all GND end of the one GPS integrated chip U9 all is connected with DGND digitally, the positive pole of the second Schottky Rectifier D2 is connected with the VBAT end of a GPS integrated chip U9, and negative pole is connected with the positive pole of the second reserve battery BT2, the negative pole of the second reserve battery BT2 is connected with DGND digitally, the positive pole of the 3rd Schottky Rectifier D3 is connected with the VBAT end of a GPS integrated chip U9, and negative pole is connected with the VCC end of a GPS integrated chip U9, all NC ends of the one GPS integrated chip U9 are all unsettled.The model of a described GPS integrated chip U9 is VK2525.

Described radio receiving transmitting module comprises the first high speed wireless data receiving and transmitting integrated module JP1; 1 end of the first high speed wireless data receiving and transmitting integrated module JP1 is connected with DGND digitally; 2 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with digital power DVCC; 3 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CE of first microprocessor U4; 4 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CSN of first microprocessor U4; 5 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-SCK of first microprocessor U4; 6 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MOSI of first microprocessor U4; 7 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MISO of first microprocessor U4; 8 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-IRQ of first microprocessor U4.Acp chip model in described the first high speed wireless data receiving and transmitting integrated module JP1 is nRF24L01.

Described serial ports/SWD debug i/f circuit comprises first serial debugging interface JP2, a SWD debugging interface JP3; 1 end of first serial debugging interface JP2 is connected with+5V power supply; 2 ends of first serial debugging interface JP2 are connected with the UART1-TX of first microprocessor U4 end; 3 ends of first serial debugging interface JP2 are connected with the UART1-RX of first microprocessor U4 end; 4 ends of first serial debugging interface JP2 are connected with DGND digitally; 1 end of the one SWD debugging interface U5 is connected with digital power DVCC; 2 ends of the one SWD debugging interface JP3 are connected with the SWDIO of first microprocessor U4 end; 3 ends of the one SWD debugging interface JP3 are connected with the SWDCLK of first microprocessor U4 end; 4 ends of the one SWD debugging interface JP3 are connected with DGND digitally.

Described signal input/output interface comprises remote signal input interface, four-way throttle signal output interface and function conversion keys circuit.

Described remote signal input interface comprises the first remote signal input interface JP8; 1 end of the first remote signal input interface JP8 is connected with DGND digitally; 2 ends of the first remote signal input interface JP8 are connected with+5V power supply; 3 ends of the first remote signal input interface JP8 are connected with the Rev-PPM of first microprocessor U3.

Described four-way throttle signal output interface comprises first signal output interface JP4, secondary signal output interface JP5, the 3rd signal output interface JP6 and the 4th signal output interface JP7; 1 end of first signal output interface JP4 is connected with the PWM-CH1 of first microprocessor U4; 3 ends of secondary signal output interface JP4 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP4 are unsettled; 1 end of secondary signal output interface JP5 is connected with the PWM-CH2 of first microprocessor U4; 3 ends of secondary signal output interface JP5 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP5 are unsettled; 1 end of the 3rd signal output interface JP6 is connected with the PWM-CH3 of first microprocessor U4; 3 ends of the 3rd signal output interface JP6 are connected with power supply ground DGND; 2 ends of the 3rd signal output interface JP6 are unsettled; 1 end of the 4th signal output interface JP7 is connected with the PWM-CH4 of first microprocessor U4; 3 ends of the 4th signal output interface JP7 are connected with power supply ground DGND; 2 ends of the 4th signal output interface JP7 are unsettled.

Described function conversion keys circuit comprises the 9th resistance R 9, the tenth resistance R 10, second switch button S2 and the 3rd switch key S3; One end of the 9th resistance R 9 is connected with the KEY1 end of first little processing U4, and the other end is connected with the second button S2; The end of the second button S2 is connected with the 9th resistance R 9, and the other end is connected with DGND digitally; One end of the tenth resistance R 10 is connected with the KEY2 end of first little processing U4, and the other end is connected with the 3rd button 3; The end of the 3rd button S3 is connected with the tenth resistance R 10, and the other end is connected with DGND digitally.

The utility model has following beneficial effect with respect to prior art: the utility model integrates the functions such as the control of fuselage attitude, flying height detection, wireless receiving and dispatching, and body flight has reliability and stability and handling.In conjunction with corresponding upper computer software, can realize perfect man-machine interaction, the Real Time Monitoring Flight Condition Data is adjusted aircraft parameters, and keeps the general extension interface, and functional module is transplanted easy, has stronger task ductility.

Description of drawings

Fig. 1 is that each module workflow of the utility model illustrates intention;

Fig. 2 is the power supply module circuit diagram;

Fig. 3 is the microprocessor module circuit diagram;

Fig. 4 is fuselage attitude control module circuit diagram;

Fig. 5 is flying height detection module circuit diagram;

Fig. 6 is the digital compass circuit diagram;

Fig. 7 is GPS positioning navigation module circuit diagram;

Fig. 8 is the wireless data transceiver module circuit diagram;

Fig. 9 is serial ports/SWD debug i/f circuit figure;

Figure 10 is signal input/output interface circuit figure.

Embodiment

Below in conjunction with accompanying drawing, the utility model is further described.

As shown in Figure 1, the present embodiment comprises power supply module, microprocessor module, fuselage attitude control module, flying height detection module, digital compass module, wireless data transceiver module, GPS positioning navigation module, serial ports/SWD debug i/f circuit and signal input/output interface.

Specific works process of the present utility model is: fuselage attitude control module, the axial data such as angular velocity, inclination angle acceleration and flying height of flying height detection module Real-time Collection fuselage three are delivered to microprocessor by universal serial bus, and these data will be as main flight inertia feedback information; Digital compass and GPS positioning navigation module gather the flight position feedback informations such as course, speed, coordinate, also deliver to microprocessor by universal serial bus.Flight inertia feedback information utilizes the kalman filter method processing to merge, obtain the best output estimation value in a certain moment, adopt pid control algorithm to carry out closed-loop control to the fuselage state, each passage PWM motor drive signal of final signal output interface generation through adjusting realizes fuselage attitude, stabilized flight control to the electron speed regulator input end; Utilize the flight position feedback information, microprocessor change of flight attitude along prearranged heading flight, realizes automatic cruising, makes a return voyage; Wireless data transceiver module timed sending flight condition information, and can accept the predetermined protocol order, change of flight device pid control parameter and control aircraft and temporarily hover, make a return voyage immediately etc.

As shown in Figure 2, the power supply module comprises+5V power supply switch voltage-stabilizing circuit, analog power switch voltage-stabilizing circuit, digital power conversion mu balanced circuit, electric quantity detecting circuit, fuselage state indicating circuit and filtering antijamming circuit.

+ 5V power-switching circuit comprises the first switching type power supply conversion chip U1, the first Schottky Rectifier D1, the first stabilizing inducatnce L1, the first resistance R 1, the second resistance R 2, the 9th capacitor C 9, the tenth capacitor C 10, the 11 capacitor C 11 and the 12 capacitor C 12; The first switching type power supply conversion chip U1+VIN end is connected with driving power PVCC; The GND of the first switching type power supply conversion chip U1 is connected with power supply ground PGND; The first switching type power supply conversion chip U1's

/ OFF end is connected with power supply ground PGND; The end of the first Schottky Rectifier D1 is connected with the OUT end of the first switching type power supply conversion chip U1, and the other end is connected with power supply ground PGND; The OUT end of the end of the first stabilizing inducatnce L1 and the first switching type power supply conversion chip U1 is connected, and the other end is connected with+5V; The first resistance R 1 one ends are connected with+5V, and the other end is connected with the FB end of the first switching type power supply conversion chip U1; The second resistance R 2 one ends are connected with power supply ground PGND, and the other end is connected with the FB end of the first switching type power supply conversion chip U1; The 9th electric capacity R9 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; The tenth electric capacity R10 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; The 11 electric capacity R11 one end is connected with+5V, and the other end is connected with power supply ground PGND; The 12 electric capacity R12 one end is connected with+5V, and the other end is connected with power supply ground PGND.

The model of the first switching type power supply conversion chip U4 that the utility model is selected is LM2596-ADJ, can bear the direct current input of 4.5～40V, and adjustable being output as+5V, for receiver, serial ports etc. provides power supply.The model of the first Schottky Rectifier D1 is SS54, is used for rectification, and switching speed is fast, and forward voltage drop is low, and it is 5A that maximum is born electric current, and oppositely withstand voltage is 40V, can play holding circuit, prevents the effect of transshipping.

The analog power change-over circuit comprises the second linear voltage adjusting chip U3, the second capacitor C 2, the 6th capacitor C 6, the 7th capacitor C 7, the 8th capacitor C 8 and the 4th resistance R 4; The VIN end that the second linear voltage is regulated chip U3 is connected with+5V; The GND end that the second linear voltage is regulated chip U3 is connected with simulation ground AGND; The VOUT end that the second linear voltage is regulated chip U3 is connected with analog power AVCC; The positive pole of the second capacitor C 2 is connected with+5V, and negative pole is connected with simulation ground AGND; One end of the 6th capacitor C 6 is connected with+5V, and the other end is connected with simulation ground AGND; One end of the 7th capacitor C 7 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; One end of the 8th capacitor C 8 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; The 4th resistance R 4 one ends are connected with power supply ground PGND, and the other end is connected with simulation ground AGND.

The digital power conversion circuit comprises the first linear voltage-regulation chip U2, the first capacitor C 1, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5 and the 3rd resistance R 3; The VIN of the first linear voltage-regulation chip U2 end is connected with+5V; The GND of the first linear voltage-regulation chip U2 end is connected with DGND digitally; The VOUT end of the first linear voltage-regulation chip U2 is connected with digital power DVCC; The positive pole of the first capacitor C 1 is connected with+5V, and negative pole is connected with DGND digitally; One end of the 3rd capacitor C 3 is connected with+5V, and the other end is connected with DGND digitally; One end of the 4th capacitor C 4 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 5th capacitor C 5 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 3rd resistance R 3 is connected with power supply ground PGND, and the other end is connected with DGND digitally.

The model that the first linear voltage-regulation chip U2 that the utility model is selected and the second linear voltage are regulated chip U3 is LM1117-3.3.

Adopt independently 5V/3.3V to separate mu balanced circuit, both prevented that undesired signal from scurrying into, also digital power is separated with analog power, guarantee that supply voltage is stable.

Electric quantity detecting circuit comprises the 23 resistance R 23, the 24 resistance R 24; The 24 resistance R 24 1 ends are connected with driving power PVCC, and the other end is connected with the VBAT-CH end of first microprocessor U4; The 23 resistance R 23 1 ends are connected with the VBAT-CH end of first microprocessor U4, and the other end is connected with power supply ground PGND.

Due to lithium battery power supply voltage, the actual 24V that is about during Full Charge Capacity is about 20V during basic approaching zero electric weight, and therefore by electric resistance partial pressure, microprocessor can obtain the battery electric quantity situation, and is unlikely to burn chip and circuit.

The fuselage state indicating circuit comprises the first hummer LS1, the first triode Q1, the first light emitting diode DS1, the second light emitting diode DS2, the 3rd light emitting diode DS3, the 11 resistance R 11, the 12 resistance R 12, the 13 resistance R 13 and the 14 resistance R 14; The positive pole of the first hummer is connected with analog power AVCC, and negative pole is connected with the collector of the first triode Q1; One end of the 14 resistance R 14 is connected with the base stage of the first triode Q1, and the other end is connected with the BELL end of first microprocessor U4; The emitter of the first triode Q1 is connected with simulation ground AGND; One end of the 11 resistance R 11 is connected with+5V power supply, and the other end is connected with the positive pole of the first light emitting diode DS1; The negative pole of the first light emitting diode DS1 is connected with power supply ground PGND; One end of the 12 resistance R 12 is connected with digital power DVCC, and the other end is connected with the positive pole of the second light emitting diode DS2; The negative pole of the second light emitting diode DS2 is connected with the LED1 end of first microprocessor U3; One end of the 13 resistance R 13 is connected with analog power AVCC, and the other end is connected with the positive pole of the 3rd light emitting diode DS3; The negative pole of the 3rd light emitting diode DS3 is connected with the LED2 end of first microprocessor U4.

Filtering antijamming circuit comprises the 18 capacitor C 18, the 19 capacitor C 19, the 20 capacitor C 20, the 21 capacitor C 21, the 22 capacitor C 22, the 23 capacitor C 23, the 24 capacitor C 24 and the 25 capacitor C 25; One end of the 18 capacitor C 18 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 19 capacitor C 19 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 20 capacitor C 20 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 20 capacitor C 20 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 21 capacitor C 21 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 22 capacitor C 22 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 23 capacitor C 23 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; One end of the 24 capacitor C 24 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; One end of the 25 capacitor C 25 is connected with analog power AVCC, and the other end is connected with simulation ground AGND.

Filter capacitor is placed in the micro processor leg limit, ground connection nearby, and filtering low-and high-frequency noise, reducing the simulation part affects with numerical portion.

As shown in Figure 3, microprocessor module comprises first microprocessor U4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 13 capacitor C 13, the 14 capacitor C 14, the 15 capacitor C 15, the 16 capacitor C 16, the 17 capacitor C 17, the first crystal oscillator Y1, the second crystal oscillator Y2, the first button S1 and the first reserve battery BT1; One end of the 5th resistance R 5 is connected with digital power DVCC, and the other end is connected with the NSRT of first microprocessor U4; One end of the 7th resistance R 7 is connected with DGND digitally, and the other end is connected with the BOOT1 of first microprocessor U4; The 8th resistance R 8 one ends are connected with DGND digitally, and the other end is connected with the BOOT0 of first microprocessor U4; The 6th resistance R 6 one ends are connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; The 16 capacitor C 16 1 ends are connected with the OSC-OUT of first microprocessor U4, and the other end is connected with DGND digitally; The 17 capacitor C 17 1 ends are connected with the OSC-IN of first microprocessor U4, and the other end is connected with DGND digitally; The 15 capacitor C 15 1 ends are connected with the NSRT of first microprocessor U4, and the other end is connected with DGND digitally; The 13 capacitor C 13 1 ends are connected with the OSC32-OUT of first microprocessor U4, and the other end is connected with GDND digitally; The 14 capacitor C 14 is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with DGND digitally; The first crystal oscillator Y1 one end is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with the OSC32-OUT of first microprocessor U4; The second crystal oscillator Y2 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; The first button S1 one end is connected with the NSRT of first microprocessor U4, and the other end is connected with DGND digitally; The first reserve battery BT1 one end is connected with the VBAT of first microprocessor U4, and the other end is connected with DGND digitally; VDD_1～VDD_4 of first microprocessor U4 is connected with digital power DVCC; The VDDA end of first microprocessor U4 is connected with analog power AVCC; The VSSA end of first microprocessor U4 is connected with simulation ground AGND; The VSS_1 of first microprocessor U4～VSS_4 end is connected with DGND digitally; The model of described first microprocessor U4 is STM32F101RBT6.

The model of the first microprocessor U4 that the utility model is selected is that STM32F101RBT6 is a microprocessor based on ARM Cortex-M3 kernel, and this processor has the design of 256K byte flash memory, 20K byte SRAM, 51 available IO mouths and low-power consumption and can be competent at real-time multi-channel data sampling and process;

Fuselage attitude control module comprises three axis angular rate detection modules and three axial rake detection modules;

As shown in Figure 4, three axis angular rate detection modules comprise the first angular velocity detection unit U5, the 26 capacitor C 26 and the 27 capacitor C 27; The VDDIO end of the first angular velocity detection unit U5 is connected with digital power DVCC; The SCL/SPC end of the first angular velocity detection unit U5 is connected with the Gyro-SPC end of first microprocessor U4; The SDA/SDI/SDO end of the first angular velocity detection unit U5 is connected with the Gyro-SDI end of first microprocessor U4; The SDO/SA0 end of the first angular velocity detection unit U5 is connected with the Gyro-SDO end of first microprocessor U4; The CS end of the first angular velocity detection unit U5 is connected with the Gyro-CS end of first microprocessor U4; The DR/INT2 end of the first angular velocity detection unit U5 is connected with the Gyro-DR end of first microprocessor U4; 8～No. 12 pins of the first angular velocity detection unit U5 are RESERVED end, are connected with DGND digitally; The GND of the first angular velocity detection unit U5 end is connected with DGND digitally; No. 15 pins of the first angular velocity detection unit U5 are that the RESERVED end is connected with digital power DVCC; The vdd terminal of the first angular velocity detection unit U5 is connected with digital power DVCC; The 26 capacitor C 26 1 ends are connected with digital power DVCC, and the other end is connected with DGND digitally; The 27 capacitor C 27 1 ends are connected with digital power DVCC, and the other end is connected with DGND digitally.

Three axial rake detection modules comprise the first inclination angle acceleration detecting unit U6; The 5V of the first inclination angle acceleration detecting unit U6 end is connected with+5V power supply; The GND end of the first inclination angle acceleration detecting unit U6 is connected with simulation ground AGND; The Xout end of the first inclination angle acceleration detecting unit U6, Yout end and Zout end are connected with Acce-Z with Acce-X, the Acce-Y of first microprocessor U4 respectively; The SL end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS2 of first microprocessor U4; The 0G end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-0G of first microprocessor U4; The ST end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS1 of first microprocessor U4; The GS end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-MODE of first microprocessor U4.

The model of the first angular velocity detection unit U5 that the utility model is selected is L3G4200D, and three optional sampling angular velocity precision ± 250/500/2000 deg./sec. are provided, and can start self check.After the output of angular velocity data signal, need first pass through Hi-pass filter, then to 10 times of operational amplifier amplifications.At last, after low-pass filter was processed, each axial signal was delivered to first microprocessor U3 respective input.

The model of the first inclination angle acceleration detecting unit U6 that the utility model is selected is MMA7361; This inclination angle acceleration detecting unit need not external unit owing to carrying the signal condition low-pass filter, and the sampling output pin can directly be connected to first microprocessor U4, therefore uses very easy.Before work, the high sensitivity pattern is selected in the software configuration, first carries out the 0g freely falling body after startup and detects.Timer-controlled self-inspection and temperature compensation in operational process.

As shown in Figure 5, the flying height detection module comprises the first digital gas pressure sensor U7, the 15 resistance R 15 and the 16 resistance R 16; The 15 resistance R 15 1 ends are connected with digital power DVCC, and the other end is connected with the Altimeter-SDA of the first digital gas pressure sensor U7; The 16 resistance R 16 1 ends are connected with digital power DVCC, and the other end is connected with the Altimeter-SCL of the first digital gas pressure sensor U7; The GND of the first digital gas pressure sensor U7 end is connected with DGND digitally; The EOC end of the first digital gas pressure sensor U7 is connected with the Altimeter-EOC of first microprocessor U4; The VDDA end of the first digital gas pressure sensor U7 is connected with analog power AVCC; The VDDD end of the first digital gas pressure sensor U7 is connected with digital power DVCC; The XCLR end of the first digital gas pressure sensor U7 is connected with the Altimeter-XCLR of first microprocessor U4; The NC end of the first digital gas pressure sensor U7 is unsettled.The model of the digital gas pressure sensor U10 that the utility model is selected is BMP085, and this sensor passes through I ²C bus transfer barometric information can obtain aircraft current flight height through simple conversion.

As shown in Figure 6, the digital compass module comprises the one or three number of axle word magnetoresistive transducer U8, the 17 resistance R 17, the 18 resistance R 18, the 29 capacitor C 29, the 30 capacitor C 30, the 31 capacitor C 31 and the 32 capacitor C 32; One end of the 17 resistance is connected with digital power DVCC, and the other end is connected with the Cmps-SCL end of first microprocessor U4; One end of the 18 resistance is connected with digital power DVCC, and the other end is connected with the Cmps-SDA end of first microprocessor U4; One end of the 29 capacitor C 29 is connected with the SETP end of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with the SETC end of the one or three number of axle word magnetoresistive transducer U8; The CI end of one end of the 30 capacitor C 30 and the one or three number of axle word magnetoresistive transducer U8 is connected, the other end with digitally be connected; The 31 capacitor C 31 1 ends are connected with the VDDIO of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with DGND digitally; One end of the 32 capacitor C 32 is connected with the VDD of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with DGND digitally; The vdd terminal of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The VDDIO end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The SI end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; All GND end of the one or three number of axle word magnetoresistive transducer U8 all is connected with DGND digitally.

The model of the one or three number of axle word magnetoresistive transducer U8 that the utility model adopts is HMC5883L, it is a high integration module, be used for the locking flight course, carry three axle magnetoresistive transducers, amplifier, autodegauss driver, 12 ADC can control this module and reach 1o～2o in the strong magnetic field circumstance precision, can deviation calibrate, clever lightness is high, good reliability.Have desirable low-voltage power supply and ultralow Consumption, save aircraft work power consumption, be fit to the aircraft battery power supply.

As shown in Figure 7, described GPS positioning navigation module comprises a GPS integrated chip U9, the 19 resistance R 19, the 20 resistance R 20, the 21 resistance R 21, the 22 resistance R 22, the 33 capacitor C 33, the 34 capacitor C 34, the 35 capacitor C 35, the 36 capacitor C 36, the 37 capacitor C 37, the second inductance L 2, the 3rd inductance L 3, the 4th light emitting diode DS4, the second Schottky Rectifier D2, the 3rd Schottky Rectifier D3, the second reserve battery BT2 and the first ceramic antenna E1; One end of the 19 resistance R 19 is connected with the PPS end of a GPS integrated chip U9, and the other end is connected with the 4th light emitting diode DS4; The end of the 4th light emitting diode DS4 is connected with the 19 resistance R 19, and the other end is connected with DGND digitally; One end of the 20 resistance is connected with the TXA of a GPS integrated chip U9, and the other end is connected with the PA3 end of first microprocessor U4; One end of the 21 resistance R 21 is connected with the DXA of a GPS integrated chip U9, and the other end is connected with the PA2 end of first microprocessor U4; One end of the 22 resistance R 22 is connected with the positive pole of the second reserve battery BT2, and the other end is connected with the VBAT end of a GPS integrated chip U9; One end of the 33 capacitor C 33 and the PA3 of first microprocessor U4 end is connected, and the other end is connected with DGND digitally; One end of the 34 electric capacity and the PA2 of first microprocessor U4 end is connected, and the other end is connected with DGND digitally; One end of the 35 capacitor C 35 is connected with the VCC end of a GPS integrated chip U9, and the other end is connected with an end of the second inductance L 2; One end of the second inductance L 2 is connected with the 35 capacitor C 35, the other end with digitally be connected; One end of the 36 capacitor C 6 is connected with the VCC end of a GPS integrated chip U9, and the other end is connected with an end of the second inductance L 2; One end of the 3rd inductance L 3 is connected with the VCC end of a GPS integrated chip U9, and the other end is connected with digital power DVCC; One end of the 37 capacitor C 37 is connected with digital power DVCC, and the other end is connected with DGND digitally; The RF_IN end of the one GPS integrated chip U9 is connected with the first ceramic antenna E1; All GND end of the one GPS integrated chip U9 all is connected with DGND digitally; The positive pole of the second Schottky Rectifier D2 is connected with the VBAT end of a GPS integrated chip U9, and negative pole is connected with the positive pole of the second reserve battery BT2; The negative pole of the second reserve battery BT2 is connected with DGND digitally; The positive pole of the 3rd Schottky Rectifier D3 is connected with the VBAT end of a GPS integrated chip U9, and negative pole is connected with the VCC end of a GPS integrated chip U9; All NC ends of the one GPS integrated chip U9 are all unsettled.

The model of the one GPS integrated chip U9 is VK1613, adopt SiRF third generation high sensitivity, low power consumption chip StarIII, built-in ARM7TDMI CPU, search and computing satellite signals ability are stronger, support the wide pressure power supply of 3V ~ 5V, operating temperature range is large, use height above sea level less than 18000 meters, precision is 2.2 meters circumference errors, the ability that possesses quick location and follow the trail of 20 satellites, get final product accurate positioning flight device in conjunction with digital compass, provide the accurate location data, as elements of a fix information, current satellite information, three-dimensional velocity information.

As shown in Figure 8, radio receiving transmitting module comprises the first high speed wireless data receiving and transmitting integrated module JP1; 1 end of the first high speed wireless data receiving and transmitting integrated module JP1 is connected with DGND digitally; 2 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with digital power DVCC; 3 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CE of first microprocessor U4; 4 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CSN of first microprocessor U4; 5 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-SCK of first microprocessor U4; 6 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MOSI of first microprocessor U4; 7 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MISO of first microprocessor U4; 8 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-IRQ of first microprocessor U4.

Acp chip model in selected the first high speed wireless data receiving and transmitting integrated module JP1 of the utility model is nRF24L01.This chip uses SPI interface and processor communication, adopts Enhanced ShockBurst technology, and supports the 2Mbps high-speed transfer, and the reliable communication distance can reach 600 meters left and right farthest.And only need at the control microcomputer end, use single-chip microcomputer to communicate by letter with equal modules and can receive in real time, bidding protocol can use the RS232/RS485 form, and command mode is with reference to AT order commonly used.

As shown in Figure 9, serial ports/SWD debug i/f circuit comprises first serial debugging interface JP2, a SWD debugging interface JP3; 1 end of first serial debugging interface JP2 is connected with+5V power supply; 2 ends of first serial debugging interface JP2 are connected with the UART1-TX of first microprocessor U4 end; 3 ends of first serial debugging interface JP2 are connected with the UART1-RX of first microprocessor U4 end; 4 ends of first serial debugging interface JP2 are connected with DGND digitally; 1 end of the one SWD debugging interface U5 is connected with digital power DVCC; 2 ends of the one SWD debugging interface JP3 are connected with the SWDIO of first microprocessor U4 end; 3 ends of the one SWD debugging interface JP3 are connected with the SWDCLK of first microprocessor U4 end; 4 ends of the one SWD debugging interface JP3 are connected with DGND digitally.

But the utility model adopts SWD interface on-line debugging aircraft, and the programming program is to first microprocessor U3, to save the IO resource for each road sampling module signal input.And the serial ports 1 of the STM32 that reserves, data observation and the Function Extension of being convenient to debug process need to use.

As shown in figure 10, the signal input/output interface comprises remote signal input interface, four-way throttle signal output interface and function conversion keys circuit.

The remote signal input interface comprises the first remote signal input interface JP8; 1 end of the first remote signal input interface JP8 is connected with DGND digitally; 2 ends of the first remote signal input interface JP8 are connected with+5V power supply; 3 ends of the first remote signal input interface JP8 are connected with the Rev-PPM of first microprocessor U3.

Four-way throttle signal output interface comprises first signal output interface JP4, secondary signal output interface JP5, the 3rd signal output interface JP6 and the 4th signal output interface JP7; 1 end of first signal output interface JP4 is connected with the PWM-CH1 of first microprocessor U4; 3 ends of secondary signal output interface JP4 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP4 are unsettled; 1 end of secondary signal output interface JP5 is connected with the PWM-CH2 of first microprocessor U4; 3 ends of secondary signal output interface JP5 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP5 are unsettled; 1 end of the 3rd signal output interface JP6 is connected with the PWM-CH3 of first microprocessor U4; 3 ends of the 3rd signal output interface JP6 are connected with power supply ground DGND; 2 ends of the 3rd signal output interface JP6 are unsettled; 1 end of the 4th signal output interface JP7 is connected with the PWM-CH4 of first microprocessor U4; 3 ends of the 4th signal output interface JP7 are connected with power supply ground DGND; 2 ends of the 4th signal output interface JP7 are unsettled.

The function conversion keys circuit comprises the 9th resistance R 9, the tenth resistance R 10, second switch button S2 and the 3rd switch key S3; One end of the 9th resistance R 9 is connected with the KEY1 end of first little processing U4, and the other end is connected with the second button S2; The end of the second button S2 is connected with the 9th resistance R 9, and the other end is connected with DGND digitally; One end of the tenth resistance R 10 is connected with the KEY2 end of first little processing U4, and the other end is connected with the 3rd button 3; The end of the 3rd button S3 is connected with the tenth resistance R 10, and the other end is connected with DGND digitally.

When the aerocraft system pattern was the self-navigation pattern, first microprocessor U4 processed, merges each sensing data in real time, directly outputed to each road electron speed regulator by four-way throttle signal output interface and changed motor speed, controlled aircraft course; When the aerocraft system pattern switches to manual control, the remote signal of PPM modulation is input to microprocessor U4 by the first remote signal input interface JP8, drive signal with PWM and output to each road electron speed regulator by four-way throttle signal output interface after first microprocessor is processed, increase or reduce thereby change brushless motor speed.

Explanation at last, only unrestricted its comprises scope in order to the technical solution of the utility model to be described in above description, namely the technical solution of the utility model modified or be equal to replacement, and not breaking away from its purpose and scope, all should be covered by in the middle of claim scope of the present utility model.

Claims

1. self-navigation flight control system based on cross flow fan, comprise power supply module, microprocessor module, fuselage attitude control module, flying height detection module, digital compass module, wireless data transceiver module, GPS positioning navigation module, serial ports/SWD debug i/f circuit and signal input/output interface, it is characterized in that: fuselage attitude control module, flying height detection module, digital compass module, GPS positioning navigation module are connected universal serial bus and are connected with microprocessor module with wireless data transceiver module; The power supply module is that microprocessor module, fuselage attitude control module, flying height detection module, radio receiving transmitting module, serial ports/SWD debug i/f circuit and fuselage state indicating circuit provide working power;

Described power supply module comprises+5V power supply switch voltage-stabilizing circuit, analog power switch voltage-stabilizing circuit, digital power conversion mu balanced circuit, electric quantity detecting circuit, fuselage state indicating circuit and filtering antijamming circuit;

Described+5V power-switching circuit comprises the first switching type power supply conversion chip U1, the first Schottky Rectifier D1, the first stabilizing inducatnce L1, the first resistance R 1, the second resistance R 2, the 9th capacitor C 9, the tenth capacitor C 10, the 11 capacitor C 11 and the 12 capacitor C 12; The first switching type power supply conversion chip U1+VIN end is connected with driving power PVCC; The GND of the first switching type power supply conversion chip U1 is connected with power supply ground PGND; The first switching type power supply conversion chip U1's

Figure 2012207472476100001DEST_PATH_IMAGE002

/ OFF end is connected with power supply ground PGND; The end of the first Schottky Rectifier D1 is connected with the OUT end of the first switching type power supply conversion chip U1, and the other end is connected with power supply ground PGND; The OUT end of the end of the first stabilizing inducatnce L1 and the first switching type power supply conversion chip U1 is connected, and the other end is connected with+5V; The first resistance R 1 one ends are connected with+5V, and the other end is connected with the FB end of the first switching type power supply conversion chip U1; The second resistance R 2 one ends are connected with power supply ground PGND, and the other end is connected with the FB end of the first switching type power supply conversion chip U1; The 9th electric capacity R9 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; The tenth electric capacity R10 one end is connected with driving power PVCC, and the other end is connected with power supply ground PGND; The 11 electric capacity R11 one end is connected with+5V, and the other end is connected with power supply ground PGND; The 12 electric capacity R12 one end is connected with+5V, and the other end is connected with power supply ground PGND;

The model of described the first switching type power supply conversion chip U1 is LM2596-ADJ, and the model of the first Schottky Rectifier D1 is SS34;

Described analog power change-over circuit comprises the second linear voltage adjusting chip U3, the second capacitor C 2, the 6th capacitor C 6, the 7th capacitor C 7, the 8th capacitor C 8 and the 4th resistance R 4; The VIN end that the second linear voltage is regulated chip U3 is connected with+5V; The GND end that the second linear voltage is regulated chip U3 is connected with simulation ground AGND; The VOUT end that the second linear voltage is regulated chip U3 is connected with analog power AVCC; The positive pole of the second capacitor C 2 is connected with+5V, and negative pole is connected with simulation ground AGND; One end of the 6th capacitor C 6 is connected with+5V, and the other end is connected with simulation ground AGND; One end of the 7th capacitor C 7 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; One end of the 8th capacitor C 8 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; The 4th resistance R 4 one ends are connected with power supply ground PGND, and the other end is connected with simulation ground AGND;

Described digital power conversion circuit comprises the first linear voltage-regulation chip U2, the first capacitor C 1, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5 and the 3rd resistance R 3; The VIN of the first linear voltage-regulation chip U2 end is connected with+5V; The GND of the first linear voltage-regulation chip U2 end is connected with DGND digitally; The VOUT end of the first linear voltage-regulation chip U2 is connected with digital power DVCC; The positive pole of the first capacitor C 1 is connected with+5V, and negative pole is connected with DGND digitally; One end of the 3rd capacitor C 3 is connected with+5V, and the other end is connected with DGND digitally; One end of the 4th capacitor C 4 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 5th capacitor C 5 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 3rd resistance R 3 is connected with power supply ground PGND, and the other end is connected with DGND digitally;

The model that the described first linear voltage-regulation chip U2 and the second linear voltage are regulated chip U3 is LM1117-3.3;

Described electric quantity detecting circuit comprises the 23 resistance R 23, the 24 resistance R 24; The 24 resistance R 24 1 ends are connected with driving power PVCC, and the other end is connected with the VBAT-CH end of first microprocessor U4; The 23 resistance R 23 1 ends are connected with the VBAT-CH end of first microprocessor U4, and the other end is connected with power supply ground PGND;

Described fuselage state indicating circuit comprises the first hummer LS1, the first triode Q1, the first light emitting diode DS1, the second light emitting diode DS2, the 3rd light emitting diode DS3, the 11 resistance R 11, the 12 resistance R 12, the 13 resistance R 13 and the 14 resistance R 14; The positive pole of the first hummer is connected with analog power AVCC, and negative pole is connected with the collector of the first triode Q1; One end of the 14 resistance R 14 is connected with the base stage of the first triode Q1, and the other end is connected with the BELL end of first microprocessor U4; The emitter of the first triode Q1 is connected with simulation ground AGND; One end of the 11 resistance R 11 is connected with+5V power supply, and the other end is connected with the positive pole of the first light emitting diode DS1; The negative pole of the first light emitting diode DS1 is connected with power supply ground PGND; One end of the 12 resistance R 12 is connected with digital power DVCC, and the other end is connected with the positive pole of the second light emitting diode DS2; The negative pole of the second light emitting diode DS2 is connected with the LED1 end of first microprocessor U3; One end of the 13 resistance R 13 is connected with analog power AVCC, and the other end is connected with the positive pole of the 3rd light emitting diode DS3; The negative pole of the 3rd light emitting diode DS3 is connected with the LED2 end of first microprocessor U4;

The model of described the first triode Q1 is 8050;

Described filtering antijamming circuit comprises the 18 capacitor C 18, the 19 capacitor C 19, the 20 capacitor C 20, the 21 capacitor C 21, the 22 capacitor C 22, the 23 capacitor C 23, the 24 capacitor C 24 and the 25 capacitor C 25; One end of the 18 capacitor C 18 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 19 capacitor C 19 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 20 capacitor C 20 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 20 capacitor C 20 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 21 capacitor C 21 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 22 capacitor C 22 is connected with digital power DVCC, and the other end is connected with DGND digitally; One end of the 23 capacitor C 23 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; One end of the 24 capacitor C 24 is connected with analog power AVCC, and the other end is connected with simulation ground AGND; One end of the 25 capacitor C 25 is connected with analog power AVCC, and the other end is connected with simulation ground AGND;

Described microprocessor module comprises first microprocessor U4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 13 capacitor C 13, the 14 capacitor C 14, the 15 capacitor C 15, the 16 capacitor C 16, the 17 capacitor C 17, the first crystal oscillator Y1, the second crystal oscillator Y2, the first button S1 and the first reserve battery BT1; One end of the 5th resistance R 5 is connected with digital power DVCC, and the other end is connected with the NSRT of first microprocessor U4; One end of the 7th resistance R 7 is connected with DGND digitally, and the other end is connected with the BOOT1 of first microprocessor U4; The 8th resistance R 8 one ends are connected with DGND digitally, and the other end is connected with the BOOT0 of first microprocessor U4; The 6th resistance R 6 one ends are connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; The 16 capacitor C 16 1 ends are connected with the OSC-OUT of first microprocessor U4, and the other end is connected with DGND digitally; The 17 capacitor C 17 1 ends are connected with the OSC-IN of first microprocessor U4, and the other end is connected with DGND digitally; The 15 capacitor C 15 1 ends are connected with the NSRT of first microprocessor U4, and the other end is connected with DGND digitally; The 13 capacitor C 13 1 ends are connected with the OSC32-OUT of first microprocessor U4, and the other end is connected with GDND digitally; The 14 capacitor C 14 is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with DGND digitally; The first crystal oscillator Y1 one end is connected with the OSC32-IN of first microprocessor U4, and the other end is connected with the OSC32-OUT of first microprocessor U4; The second crystal oscillator Y2 one end is connected with the OSC-IN of first microprocessor U4, and the other end is connected with the OSC-OUT of first microprocessor U4; The first button S1 one end is connected with the NSRT of first microprocessor U4, and the other end is connected with DGND digitally; The first reserve battery BT1 one end is connected with the VBAT of first microprocessor U4, and the other end is connected with DGND digitally; VDD_1～VDD_4 of first microprocessor U4 is connected with digital power DVCC; The VDDA end of first microprocessor U4 is connected with analog power AVCC; The VSSA end of first microprocessor U4 is connected with simulation ground AGND; The VSS_1 of first microprocessor U4～VSS_4 end is connected with DGND digitally;

The model of described first microprocessor U4 is STM32F101RBT6;

Described fuselage attitude control module comprises fuselage three axis angular rate detection modules and fuselage three axial rake detection modules;

Fuselage three axis angular rate detection modules comprise the first angular velocity detection unit U5, the 26 capacitor C 26 and the 27 capacitor C 27; The VDDIO end of the first angular velocity detection unit U5 is connected with digital power DVCC; The SCL/SPC end of the first angular velocity detection unit U5 is connected with the Gyro-SPC end of first microprocessor U4; The SDA/SDI/SDO end of the first angular velocity detection unit U5 is connected with the Gyro-SDI end of first microprocessor U4; The SDO/SA0 end of the first angular velocity detection unit U5 is connected with the Gyro-SDO end of first microprocessor U4; The CS end of the first angular velocity detection unit U5 is connected with the Gyro-CS end of first microprocessor U4; The DR/INT2 end of the first angular velocity detection unit U5 is connected with the Gyro-DR end of first microprocessor U4; 8～No. 12 pins of the first angular velocity detection unit U5 are RESERVED end, are connected with DGND digitally; The GND of the first angular velocity detection unit U5 end is connected with DGND digitally; No. 15 pins of the first angular velocity detection unit U5 are that the RESERVED end is connected with digital power DVCC; The vdd terminal of the first angular velocity detection unit U5 is connected with digital power DVCC; The 26 capacitor C 26 1 ends are connected with digital power DVCC, and the other end is connected with DGND digitally; The 27 capacitor C 27 1 ends are connected with digital power DVCC, and the other end is connected with DGND digitally;

The model of described the first angular velocity detection unit U5 is L3G4200D;

Fuselage three axial rake detection modules comprise the first inclination angle acceleration detecting unit U6; The 5V of the first inclination angle acceleration detecting unit U6 end is connected with+5V power supply; The GND end of the first inclination angle acceleration detecting unit U6 is connected with simulation ground AGND; The Xout end of the first inclination angle acceleration detecting unit U6, Yout end and Zout end are connected with Acce-Z with Acce-X, the Acce-Y of first microprocessor U4 respectively; The SL end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS2 of first microprocessor U4; The 0G end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-0G of first microprocessor U4; The ST end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-GS1 of first microprocessor U4; The GS end of the first inclination angle acceleration detecting unit U6 is connected with the Acce-MODE of first microprocessor U4;

Described flying height detection module comprises the first digital gas pressure sensor U7, the 15 resistance R 15 and the 16 resistance R 16; The 15 resistance R 15 1 ends are connected with digital power DVCC, and the other end is connected with the Altimeter-SDA of the first digital gas pressure sensor U7; The 16 resistance R 16 1 ends are connected with digital power DVCC, and the other end is connected with the Altimeter-SCL of the first digital gas pressure sensor U7; The GND of the first digital gas pressure sensor U7 end is connected with DGND digitally; The EOC end of the first digital gas pressure sensor U7 is connected with the Altimeter-EOC of first microprocessor U4; The VDDA end of the first digital gas pressure sensor U7 is connected with analog power AVCC; The VDDD end of the first digital gas pressure sensor U7 is connected with digital power DVCC; The XCLR end of the first digital gas pressure sensor U7 is connected with the Altimeter-XCLR of first microprocessor U4; The NC end of the first digital gas pressure sensor U7 is unsettled;

The model of described the first digital gas pressure sensor U7 is BMP085;

Described digital compass module comprises the one or three number of axle word magnetoresistive transducer U8, the 17 resistance R 17, the 18 resistance R 18, the 29 capacitor C 29, the 30 capacitor C 30, the 31 capacitor C 31 and the 32 capacitor C 32; One end of the 17 resistance is connected with digital power DVCC, and the other end is connected with the Cmps-SCL end of first microprocessor U4; One end of the 18 resistance is connected with digital power DVCC, and the other end is connected with the Cmps-SDA end of first microprocessor U4; One end of the 29 capacitor C 29 is connected with the SETP end of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with the SETC end of the one or three number of axle word magnetoresistive transducer U8; The CI end of one end of the 30 capacitor C 30 and the one or three number of axle word magnetoresistive transducer U8 is connected, the other end with digitally be connected; The 31 capacitor C 31 1 ends are connected with the VDDIO of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with DGND digitally; One end of the 32 capacitor C 32 is connected with the VDD of the one or three number of axle word magnetoresistive transducer U8, and the other end is connected with DGND digitally; The vdd terminal of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The VDDIO end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; The SI end of the one or three number of axle word magnetoresistive transducer U8 is connected with digital power DVCC; All GND end of the one or three number of axle word magnetoresistive transducer U8 all is connected with DGND digitally;

The model of described the one or three number of axle word magnetoresistive transducer U8 is HMC5883L;

described GPS positioning navigation module comprises a GPS integrated chip U9, the 19 resistance R 19, the 20 resistance R 20, the 21 resistance R 21, the 22 resistance R 22, the 33 capacitor C 33, the 34 capacitor C 34, the 35 capacitor C 35, the 36 capacitor C 36, the 37 capacitor C 37, the second inductance L 2, the 3rd inductance L 3, the 4th light emitting diode DS4, the second Schottky Rectifier D2, the 3rd Schottky Rectifier D3, the second reserve battery BT2 and the first ceramic antenna E1, one end of the 19 resistance R 19 is connected with the PPS of a GPS integrated chip U9, and the other end is connected with the 4th light emitting diode DS4, the end of the 4th light emitting diode DS4 is connected with the 19 resistance R 19, and the other end is connected with DGND digitally, one end of the 20 resistance is connected with the TXA of a GPS integrated chip U9, and the other end is connected with the PA3 end of first microprocessor U4, one end of the 21 resistance R 21 is connected with the DXA of a GPS integrated chip U9, and the other end is connected with the PA2 end of first microprocessor U4, one end of the 22 resistance R 22 is connected with the positive pole of the second reserve battery BT2, and the other end is connected with the VBAT end of a GPS integrated chip U9, one end of the 33 capacitor C 33 and the PA3 of first microprocessor U4 end is connected, and the other end is connected with DGND digitally, one end of the 34 electric capacity and the PA2 of first microprocessor U4 end is connected, and the other end is connected with DGND digitally, one end of the 35 capacitor C 35 is connected with the VCC end of a GPS integrated chip U9, and the other end is connected with an end of the second inductance L 2, one end of the second inductance L 2 is connected with the 35 capacitor C 35, the other end with digitally be connected, one end of the 36 capacitor C 6 is connected with the VCC end of a GPS integrated chip U9, and the other end is connected with an end of the second inductance L 2, one end of the 3rd inductance L 3 is connected with the VCC end of a GPS integrated chip U9, and the other end is connected with digital power DVCC, one end of the 37 capacitor C 37 is connected with digital power DVCC, and the other end is connected with DGND digitally, the RF_IN end of the one GPS integrated chip U9 is connected with the first ceramic antenna E1, all GND end of the one GPS integrated chip U9 all is connected with DGND digitally, the positive pole of the second Schottky Rectifier D2 is connected with the VBAT end of a GPS integrated chip U9, and negative pole is connected with the positive pole of the second reserve battery BT2, the negative pole of the second reserve battery BT2 is connected with DGND digitally, the positive pole of the 3rd Schottky Rectifier D3 is connected with the VBAT end of a GPS integrated chip U9, and negative pole is connected with the VCC end of a GPS integrated chip U9, all NC ends of the one GPS integrated chip U9 are all unsettled,

The model of a described GPS integrated chip U9 is VK2525;

Described radio receiving transmitting module comprises the first high speed wireless data receiving and transmitting integrated module JP1; 1 end of the first high speed wireless data receiving and transmitting integrated module JP1 is connected with DGND digitally; 2 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with digital power DVCC; 3 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CE of first microprocessor U4; 4 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-CSN of first microprocessor U4; 5 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-SCK of first microprocessor U4; 6 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MOSI of first microprocessor U4; 7 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-MISO of first microprocessor U4; 8 ends of the first high speed wireless data receiving and transmitting integrated module JP1 are connected with the 24L01-IRQ of first microprocessor U4;

Acp chip model in described the first high speed wireless data receiving and transmitting integrated module JP1 is nRF24L01;

Described serial ports/SWD debug i/f circuit comprises first serial debugging interface JP2, a SWD debugging interface JP3; 1 end of first serial debugging interface JP2 is connected with+5V power supply; 2 ends of first serial debugging interface JP2 are connected with the UART1-TX of first microprocessor U4 end; 3 ends of first serial debugging interface JP2 are connected with the UART1-RX of first microprocessor U4 end; 4 ends of first serial debugging interface JP2 are connected with DGND digitally; 1 end of the one SWD debugging interface U5 is connected with digital power DVCC; 2 ends of the one SWD debugging interface JP3 are connected with the SWDIO of first microprocessor U4 end; 3 ends of the one SWD debugging interface JP3 are connected with the SWDCLK of first microprocessor U4 end; 4 ends of the one SWD debugging interface JP3 are connected with DGND digitally;

Described signal input/output interface comprises remote signal input interface, four-way throttle signal output interface and function conversion keys circuit;

Described remote signal input interface comprises the first remote signal input interface JP8; 1 end of the first remote signal input interface JP8 is connected with DGND digitally; 2 ends of the first remote signal input interface JP8 are connected with+5V power supply; 3 ends of the first remote signal input interface JP8 are connected with the Rev-PPM of first microprocessor U3;

Described four-way throttle signal output interface comprises first signal output interface JP4, secondary signal output interface JP5, the 3rd signal output interface JP6 and the 4th signal output interface JP7; 1 end of first signal output interface JP4 is connected with the PWM-CH1 of first microprocessor U4; 3 ends of secondary signal output interface JP4 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP4 are unsettled; 1 end of secondary signal output interface JP5 is connected with the PWM-CH2 of first microprocessor U4; 3 ends of secondary signal output interface JP5 are connected with power supply ground DGND; 2 ends of secondary signal output interface JP5 are unsettled; 1 end of the 3rd signal output interface JP6 is connected with the PWM-CH3 of first microprocessor U4; 3 ends of the 3rd signal output interface JP6 are connected with power supply ground DGND; 2 ends of the 3rd signal output interface JP6 are unsettled; 1 end of the 4th signal output interface JP7 is connected with the PWM-CH4 of first microprocessor U4; 3 ends of the 4th signal output interface JP7 are connected with power supply ground DGND; 2 ends of the 4th signal output interface JP7 are unsettled;