CN103023044A

CN103023044A - Combination switch with intelligent zero-crossing switching function

Info

Publication number: CN103023044A
Application number: CN2012104868368A
Authority: CN
Inventors: 顾金华
Original assignee: CHANGZHOU HONGDA ELECTRICAL Co Ltd
Current assignee: Nanjing Yingna Vision Robot Co., Ltd.
Priority date: 2012-11-27
Filing date: 2012-11-27
Publication date: 2013-04-03
Anticipated expiration: 2032-11-27
Also published as: CN103023044B

Abstract

The invention discloses a combination switch with an intelligent zero-crossing switching function. The combination switch comprises a control circuit and a silicon controlled rectifier (SCR) combination switch, wherein the silicon controlled combination switch comprises two unidirectional SCR1 and SCR2, a first electromagnetic switch K1, a second electromagnetic switch K2 and a resistor R, wherein the two unidirectional SCR1 and SCR2 are respectively provided with a control terminal G1 and a control terminal G2, and the two unidirectional SCR1 and SCR2 are connected in an anti-parallel manner to form a first wiring terminal A1 and a second wiring terminal A2, and a normally-opened contact K2-1 of the second electromagnetic switch K2 is connected with the resistor R in series; and two ends of a series circuit formed by the normally-opened contact K2-1 of the second electromagnetic switch K2 and the resistor R are connected to two ends of a normally-opened contact K1-1 of the first electromagnetic switch K1 in parallel. The combination switch disclosed by the invention has the advantages of SCR conduction during current zero-crossing, more reliable switching process and the like.

Description

The combination switch of intelligence operating passing zero

Technical field

The present invention relates to a kind of combination switch of intelligent operating passing zero, it is the device for the control capacitor switching, be the important component part of reactive compensator of electrical network, and the quality of fling-cut switch element function play very important effect to the reliability of reactive power compensator.

Background technology

In the implementation process of electric network reconstruction, often need to increase the shunt capacitor reactive power compensator, to improving the supply power voltage quality, excavate the potentiality of power supply unit, reduce line loss and energy-conservationly all play a positive role.

Early stage reactive power compensator mostly adopts the switching modes such as A.C. contactor, controllable silicon electronic switch, A.C. contactor can produce very large shoving and overvoltage when capacitor drops into and excise, the high pressure of transient state and switching impulse current can cause capacitor insulation puncture, probe of contactor scaling loss; Although and the controllable silicon electronic switch has solved the problems such as shoving in the capacitor switching process, overvoltage, breaking arc, but it dispels the heat difficult, need add that the auxiliary heat dissipation device is many, complex structure, cost be high, it is large to take up room, dual mode compensation effect and all not ideal enough on useful life.

In recent years, the development of power electronic technology and controllable silicon technology derives a kind of new device---combination switch in reactive power compensator.Existing compound switch structure is with controllable silicon and relay and connects, as shown in Figure 5.The implementation method that generally believes at present is: during input, at the voltage zero-cross moment zero cross fired controllable silicon in parallel with relay or contactor, stable after again with relay or contactor adhesive conducting; And when cutting out, first with controlled silicon conducting, then relay or contacts of contactor are disconnected, produce electric arc when avoiding relay or contactor to disconnect, turn-off at current zero-crossing point place controllable silicon at last, thereby realize that current over-zero cuts off.

This area those skilled in the art as can be known, make controlled silicon conducting (take one-way SCR as example), need two necessary conditions: the one, between its anode A and negative electrode K, add forward voltage, the 2nd, between its control utmost point G and negative electrode K, input a forward trigger voltage (being commonly called as an individual Trig control signal).In other words, no matter be the one-way SCR conducting, or the bidirectional triode thyristor conducting, must satisfy the controllable silicon two ends has the pressure drop and the trigger electrode that satisfy conducting that two conditions of triggering signal are arranged, and could realize the purpose of conducting.The cutting-off process of existing combination switch when being relay or contactor K disjunction, thinks that this moment, controllable silicon was conducting state, so relay or contactor do not produce electric arc when the K disjunction.And the fact is, the closure state before the disjunction of relay K contact, and the two ends, contact do not form voltage, namely, do not form forward voltage between silicon controlled anode A and the negative electrode K, although triggering signal is arranged, controllable silicon can not conducting.The contact of relay K will cut off operating current when disjunction like this, can produce a large amount of electric arc in this process, particularly in combination switch to the Capacity Selection of relay, generally be to satisfy running current to be as the criterion, do not consider fully and drop into and cut off the required capacity of main circuit operating current, so, a large amount of electric arcs that relay contact produces during cut-out make the relay contact of the combination switch in the existing structure damage easily, cause the poor reliability of combination switch work, have a strong impact on the q﹠r of power supply.

Existing most of patent has only been described the course of work in combination switch excision stage, is illustrated by following patent.Such as the patent No. " ZL200620098117.9 ", name is called the utility model patent of " dynamic reactive power compensation equipment ", adopted the quick compound relay of its delay time＜5 second in the compensating circuit of this compensation arrangement, when controlled silicon conducting, its relay normally open contact is also closed, contact resistance when closed is very little, can pass through most of electric current, is passing through the silicon controlled electric current no better than zero.Like this, in conducting process, without pressure drop with without heating, and eliminated harmonic wave on the controllable silicon, thereby compensation arrangement can be moved under dynamical state reliably.This patent has specifically described in conducting process, and controllable silicon only has triggering signal, but there is no pressure drop, do not satisfy the silicon controlled turn-on condition, be not have pressure drop between silicon controlled anode A and the negative electrode K, therefore, the compensation arrangement of this kind structure can not move under dynamical state reliably.

" 201220121016.4 " such as the patent No., name is called " a kind of contactor combination switch of operating passing zero ": testing circuit detects control signal and removes during excision, the storage capacitor delay circuit still can continue to provide the power supply of necessity, logic control is wanted isolated drive circuit and is enabled controllable silicon, then make relay disconnect contactor coil, the disjunction of contactor mechanical contact also switches to controlled silicon conducting after a period of time, and the controllable silicon electric current is zero shutoff.The patent No. " 201220016674.7 ", name are called " minute plerosis combination switch ": during excision, and the conducting of controllable silicon elder generation, then the contact of relay separates, and electric current flows through controllable silicon, and after 50 milliseconds, controllable silicon turn-offs, and current cut-off is finished the excision action.

Such as the patent No. " 200810050960.3 ", name is called " intelligent marshalling combination switch ": during excision single-phase electricity container, single-chip microcomputer is according to the order that receives, the triggering and conducting order of sending first electronic AC switch, just automatic conducting when voltage zero-cross of electronic AC switch.The patent No. " 200820216223.1 ", name is called " a kind of intelligent compound switch of dynamic passive compensation " and thinks: when cutting out operation, only need provide first the controllable silicon program sends triggering signal, send again the signal that relay disconnects, postpone to remove silicon controlled trigger signal behind tens of milliseconds, utilize the controllable silicon self-characteristic when current over-zero, to cut off voluntarily.The patent No. " 201110032781.9 ", name is called " a kind of Intelligent composite integrated switch ": when controller unit 3 receives a certain will cut off mutually the instruction of compensation condenser the time, start bidirectional triode thyristor and drive circuits for triggering, the bidirectional triode thyristor conducting is incorporated on the magnetic maintained switch, and then indicator cock drives circuits for triggering output pulse negative voltage, make switch contact be converted to normally open, at last, controller unit indication bidirectional triode thyristor drives circuits for triggering Automatic-searching zero crossing and cuts out bidirectional triode thyristor, cuts off and replenishes capacitor.The patent No. " 201020652595.6 ", name is called " dynamic combination switch ": when automatic reactive compensated controller will be withdrawn from a certain circuit capacitor, send to combination switch and to withdraw from signal, Master control chip receives removes signal, namely order the thyristor conducting, make the magnetic latching relay dead electricity after time-delay is less than 1 second, after magnetic latching relay main contacts and compensation condenser disconnected, compensation condenser also worked on by thyristor.After time-delay was less than 1 second, Master control chip was output as 0, the cut-off of optocoupler trigger, and thyristor will be in capacitor at current over-zero and disconnect, and the compensation condenser no-flashy-flow is out of service.

The patent No. " 201120498683.X ", name is called " a kind of combination switch ": when switching circuit is received the sub-gate signal that governor circuit sends, there is first large electric current to make the bidirectional triode thyristor conducting, then relay disconnects, bidirectional triode thyristor is from the full load current to the zero to cut-off, in fact, before relay disconnected, bidirectional triode thyristor is conducting not.The patent No. " ZL201220121016 " and for example, name is called in a kind of utility model patent of contactor combination switch of operating passing zero, recognize the defective that present contactor class combination switch can not disjunction when current over-zero, therefore, possess at existing combination switch on the basis of no-voltage input function, control signal is monitored, when detecting control signal and remove, still guarantee the power supply of control circuit, and again connect controllable silicon in parallel, divide fully Deng contacts of contactor and to have no progeny, make again the controllable silicon zero-current switching, realized that voltage zero-cross is connected and the function of current over-zero disjunction power capacitor, the fact is: under this operating state, when contacts of contactor disconnected, controllable silicon is conducting not.So it is inevitable that contacts of contactor forms electric arc in this state, also just will inevitably affect the reliability of combination switch.

Summary of the invention

The objective of the invention is: provide a kind of at the current over-zero controlled silicon conducting, make combination switch cut out the combination switch of the more reliable intelligent operating passing zero of process, can improve combination switch operating efficiency and useful life, power supply quality is high, can apply to frequent switching, require response speed and the very large occasion of switching precision, overcome the deficiency of prior art.

In order to achieve the above object, the first technical scheme of the present invention is: a kind of combination switch of intelligent operating passing zero, comprise control circuit and controllable silicon compound switch, and its:

A, described controllable silicon compound switch comprises two unidirectional controllable silicon S CR1, SCR2, the first electromagnetic switch K1, the second electromagnetic switch K2 and resistance R, described two unidirectional controllable silicon S CR1, SCR2 has respectively control end G1 and control end G2, and two unidirectional controllable silicon S CR1, the SCR2 reverse parallel connection also forms the first terminals A1 and the second terminals A2, two unidirectional controllable silicon S CR1, the two ends of the normally opened contact K1-1 of SCR2 reverse parallel connection and the first terminals A1 that forms and the second terminals A2 and the first electromagnetic switch K1 are in parallel, and the normally opened contact K2-1 of the second electromagnetic switch K2 connects with resistance R; Be connected in parallel on the two ends of the normally opened contact K1-1 of the first electromagnetic switch K1 by the two ends of the normally opened contact K2-1 of the second electromagnetic switch K2 and the series circuit that resistance R consists of;

B, described control circuit comprises the CPU treatment circuit, controllable silicon drive circuit, the first electromagnetic switch drive circuit, the second electromagnetic switch drive circuit and switching signal circuit, the input of controllable silicon drive circuit, the input of the input of the first electromagnetic switch drive circuit and the second electromagnetic switch drive circuit is electrically connected with the corresponding output of CPU treatment circuit respectively, 2 outputs of controllable silicon drive circuit are electrically connected with the control end G1 of unidirectional controllable silicon S CR1 and the control end G2 of unidirectional controllable silicon S CR2 respectively, two outputs of the first electromagnetic switch drive circuit are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively, two outputs of the second electromagnetic switch drive circuit are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively, and the output of switching signal circuit is electrically connected with the input of CPU treatment circuit.

In first above-mentioned technical scheme, described the first electromagnetic switch K1 and the second electromagnetic switch K2 are relay or contactor.

In first above-mentioned technical scheme, described the first electromagnetic switch drive circuit comprises resistance R 6, triode Q3, diode D2, the first power supply terminal L, N and the first relay J 1, one end of described resistance R 6 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the first relay J 1 connects positive source simultaneously, the end of the normally opened contact J1-1 of the first relay J 1 is electrically connected with the first power supply terminal L, and the other end of the normally opened contact J1-1 of the first relay J 1 and the first power supply terminal N are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively; The second electromagnetic switch drive circuit comprises resistance R 7, triode Q4, diode D5, second source terminal L, N and the second relay J 2, one end of described resistance R 7 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 7 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the second relay J 2 connects positive source simultaneously, the end of the normally opened contact J2-1 of the second relay J 2 is electrically connected with second source terminal L, and the other end of the normally opened contact J2-1 of the second relay J 2 and second source terminal N are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively.

In first above-mentioned technical scheme, described controllable silicon drive circuit comprises resistance R 1, R2, R3, R4, R7, diode D7, D8, the two silicon output of triode Q1 and zero cross fired optical coupler U0; One end of resistance R 1 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 1 is electrically connected with the base stage of triode Q1, the collector electrode of triode Q1 is electrically connected with the first input end of the two silicon output of zero cross fired optical coupler U0, the grounded emitter of triode Q1, the second input of the two silicon output of zero cross fired optical coupler U0 connects power supply by resistance R 2, the first output of the two silicon output of zero cross fired optical coupler U0 and an end of resistance R 3, the control end G1 of the negative pole of diode D7 and unidirectional controllable silicon S CR1 is electrically connected, the other end of resistance R 3 is connected with diode D7 and anodal all is connected with the cathodic electricity of unidirectional controllable silicon S CR1, the second output of the two silicon output of zero cross fired optical coupler U0 is by the end of 4 whiles of resistance R with resistance R 7, the control end G2 of the negative pole of diode D8 and unidirectional controllable silicon S CR2 is electrically connected, and the other end of resistance R 7 is connected with diode D8 anodal the connection with the cathodic electricity of unidirectional controllable silicon S CR2 simultaneously.

In first above-mentioned technical scheme, described the first electromagnetic switch K1 is magnetic latching relay; Described the first electromagnetic switch drive circuit comprises resistance R 5, R6, diode D1, D2, D3, triode Q2, Q3, the first relay J 1 and the second relay J 2; One end of described resistance R 5 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 5 is electrically connected with the base stage of triode Q2, the collector electrode of triode Q2 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D1 respectively, the grounded emitter of triode Q2, the other end of the coil of the negative pole of diode D1 and the first relay J 1 connects power supply simultaneously, the common port JK1-1 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the end of the coil KA1 of the first electromagnetic switch K1, and the in addition common port JK1-2 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the other end of the coil KA1 of the first electromagnetic switch K1; One end of resistance R 6 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the second relay J 2 connects positive source simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D3 and the first relay J 1 and the first relay J 1 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D3 and the normally opened contact J2-1 of the

second relay J

2 and 1 group of normally-open normally-close contact of the first relay J 1 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J2-1 of the second relay J 2; Described the second electromagnetic switch K2 is magnetic latching relay; Described the second electromagnetic switch drive circuit comprises resistance R 8, R9, diode D4, D5, D6, triode Q4, Q5, the 3rd relay J 3 and the 4th relay J 4; One end of described resistance R 9 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 9 is electrically connected with the base stage of triode Q5, the collector electrode of triode Q5 is electrically connected with an end of the coil of anodal and the 3rd relay J 3 of diode D4 respectively, the grounded emitter of triode Q5, the other end of the coil of the negative pole of diode D4 and the 3rd relay J 3 connects power supply simultaneously, the common port JK3-1 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the end of the coil KA2 of the second electromagnetic switch K2, and the in addition common port JK3-2 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the other end of the coil KA2 of the second electromagnetic switch K2; One end of resistance R 8 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 8 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the 4th relay J 4 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the 4th relay J 4 connects power supply simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D6 and the first relay J 4 and the first relay J 4 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D6 and the normally opened contact J4-1 of the

4th relay J

4 and 1 group of normally-open normally-close contact of the 3rd relay J 3 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J4-1 of the 4th relay J 4.

In order to achieve the above object, the second technical scheme of the present invention is: a kind of combination switch of intelligent operating passing zero, comprise control circuit and controllable silicon compound switch, and its:

A, described controllable silicon compound switch comprise two unidirectional controllable silicon S CR1, SCR2, the first electromagnetic switch K1, the second electromagnetic switch K2 and resistance R, described two unidirectional controllable silicon S CR1, SCR2 have respectively control end G1 and control end G2, and two unidirectional controllable silicon S CR1, SCR2 reverse parallel connections also form the first terminals A1 and the second terminals A2, and the normally opened contact K2-1 of the second electromagnetic switch K2 connects with resistance R; Two ends by the normally opened contact K2-1 of the second electromagnetic switch K2 and the series circuit that resistance R consists of are in parallel with the first terminals A1 and the second terminals A2 that are also formed by two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection; The two ends of the normally opened contact K1-1 of the first electromagnetic switch K1 are connected in parallel on the two ends of resistance R;

In second above-mentioned technical scheme, described the first electromagnetic switch K1 and the second electromagnetic switch K2 are relay or contactor.

In second above-mentioned technical scheme, described the first electromagnetic switch drive circuit comprises resistance R 6, triode Q3, diode D2, the first power supply terminal L, N and the first relay J 1, one end of described resistance R 6 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the first relay J 1 connects positive source simultaneously, the end of the normally opened contact J1-1 of the first relay J 1 is electrically connected with the first power supply terminal L, and the other end of the normally opened contact J1-1 of the first relay J 1 and the first power supply terminal N are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively; The second electromagnetic switch drive circuit comprises resistance R 7, triode Q4, diode D5, second source terminal L, N and the second relay J 2, one end of described resistance R 7 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 7 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the second relay J 2 connects positive source simultaneously, the end of the normally opened contact J2-1 of the second relay J 2 is electrically connected with second source terminal L, and the other end of the normally opened contact J2-1 of the second relay J 2 and second source terminal N are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively.

In second above-mentioned technical scheme, described controllable silicon drive circuit comprises resistance R 1, R2, R3, R4, R7, diode D7, D8, the two silicon output of triode Q1 and zero cross fired optical coupler U0; One end of resistance R 1 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 1 is electrically connected with the base stage of triode Q1, the collector electrode of triode Q1 is electrically connected with the first input end of the two silicon output of zero cross fired optical coupler U0, the grounded emitter of triode Q1, the second input of the two silicon output of zero cross fired optical coupler U0 connects power supply by resistance R 2, the first output of the two silicon output of zero cross fired optical coupler U0 and an end of resistance R 3, the control end G1 of the negative pole of diode D7 and unidirectional controllable silicon S CR1 is electrically connected, the other end of resistance R 3 is connected with diode D7 and anodal all is connected with the cathodic electricity of unidirectional controllable silicon S CR1, the second output of the two silicon output of zero cross fired optical coupler U0 is by the end of 4 whiles of resistance R with resistance R 7, the control end G2 of the negative pole of diode D8 and unidirectional controllable silicon S CR2 is electrically connected, and the other end of resistance R 7 is connected with diode D8 anodal the connection with the cathodic electricity of unidirectional controllable silicon S CR2 simultaneously.

In second above-mentioned technical scheme, described the first electromagnetic switch K1 is magnetic latching relay; Described the first electromagnetic switch drive circuit comprises resistance R 5, R6, diode D1, D2, D3, triode Q2, Q3, the first relay J 1 and the second relay J 2; One end of described resistance R 5 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 5 is electrically connected with the base stage of triode Q2, the collector electrode of triode Q2 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D1 respectively, the grounded emitter of triode Q2, the other end of the coil of the negative pole of diode D1 and the first relay J 1 connects power supply simultaneously, the common port JK1-1 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the end of the coil KA1 of the first electromagnetic switch K1, and the in addition common port JK1-2 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the other end of the coil KA1 of the first electromagnetic switch K1; One end of resistance R 6 is electrically connected with the output of CPU treatment circuit, the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the second relay J 2 connects positive source simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D3 and the first relay J 1 and the first relay J 1 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D3 and the normally opened contact J2-1 of the

second relay J

4th relay J

The good effect that the present invention has is: after adopting said structure, send input and cut out signal to the CPU treatment circuit by switching signal circuit of the present invention, deliver to respectively in controllable silicon drive circuit and the electromagnetic switch drive circuit by sending different control signals after the CPU processing circuit processes again, drive ghyristor circuit and first, second electromagnetic switch K1, the K2 of two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection formation.The ghyristor circuit elder generation conducting (voltage zero-cross conducting) that the present invention is made of two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection when dropping into, first, second electromagnetic switch of rear closure K1, K2; When cutting out, disjunction the first electromagnetic switch K1 of elder generation, electric current forms voltage drop by the normally opened contact K2-1 of the second electromagnetic switch K2 and the series circuit of resistance R formation, i.e. two unidirectional controllable silicon S CR1, between SCR2 reverse parallel connection and the first binding post A1 that forms and the second binding post A2 pressure drop is arranged, trigger two unidirectional controllable silicon S CR1, the ghyristor circuit (triggering during zero passage) that the SCR2 reverse parallel connection consists of, two unidirectional controllable silicon S CR1, the ghyristor circuit conducting that the SCR2 reverse parallel connection consists of, this moment, operating current was respectively by two unidirectional controllable silicon S CR1, ghyristor circuit and the first electromagnetic switch K1 that the SCR2 reverse parallel connection consists of, but two unidirectional controllable silicon S CR1 flow through, the electric current of the ghyristor circuit that the SCR2 reverse parallel connection consists of is much larger than the electric current of the first electromagnetic switch K1 that flows through, with the first electromagnetic switch K1 disjunction, two unidirectional controllable silicon S CR1, the ghyristor circuit delay zero-crossing that the SCR2 reverse parallel connection consists of turn-offs.Whole cutting out in the process, do not bear electric current during the first electromagnetic switch K1 disjunction, only bear very little electric current during the second electromagnetic switch K2 disjunction, that is to say by the control to the first electromagnetic switch K1 and the second electromagnetic switch K2, the realization electromagnetic switch is guaranteed the conducting of controllable silicon elder generation before the disjunction main circuit current, then the electromagnetic switch contact of disjunction main circuit makes the main circuit contact in the Weak current disjunction, controls at last controllable silicon and turn-offs at current zero-crossing point.Certainly, bidirectional triode thyristor SCR also can replace to the ghyristor circuit that is made of two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection, and the good effect that produces is identical with bidirectional triode thyristor.The invention enables main circuit before cutting out, can make controllable silicon really realize passing zero trigger, and under the state of controlled silicon conducting, the electromagnetic switch contact of disjunction main circuit, thereby thoroughly overcome the defective that prior art its contact when the electromagnetic switch disjunction produces a large amount of electric arcs, solved when electromagnetic switch is cut off main circuit current in the industry prior art, the electromagnetic switch contact produces a large amount of electric arcs and causes the insecure problem of combination switch work, present ubiquitous understanding mistaken ideas in the industry have been solved, greatly improved the dependable with function of combination switch work, prolonged the life-span of combination switch, for the switching of capacitor reactive compensation and the construction of intelligent grid have a positive effect.

Description of drawings

Fig. 1 is a kind of circuit theory block diagram of implementation of the present invention;

Fig. 2 is the circuit theory schematic diagram of the first implementation of the present invention;

Fig. 3 is the circuit theory schematic diagram of the second implementation of the present invention;

Fig. 4 is the circuit theory schematic diagram of the third implementation of the present invention;

Fig. 5 is the circuit theory schematic diagram of the 4th kind of implementation of the present invention;

Fig. 6 is the circuit theory diagrams of the second implementation of switching signal circuit among Fig. 1;

Fig. 7 is the circuit theory diagrams of the third implementation of switching signal circuit among Fig. 1;

Fig. 8 is the circuit theory diagrams of the second implementation of controllable silicon drive circuit among Fig. 1;

Fig. 9 is the circuit theory schematic diagram of existing controllable silicon compound switch.

Embodiment

The present invention is described in further detail below in conjunction with drawings and Examples.

Embodiment 1

Such as Fig. 1,2,3,6,7, shown in 8, a kind of combination switch of intelligent operating passing zero, comprise control circuit 1 and controllable silicon compound switch 2, described controllable silicon compound switch 2 comprises two unidirectional controllable silicon S CR1, SCR2, the first electromagnetic switch K1, the second electromagnetic switch K2 and resistance R, described two unidirectional controllable silicon S CR1, SCR2 has respectively control end G1 and control end G2, and two unidirectional controllable silicon S CR1, the SCR2 reverse parallel connection also forms the first terminals A1 and the second terminals A2, two unidirectional controllable silicon S CR1, the two ends of the normally opened contact K1-1 of SCR2 reverse parallel connection and the first terminals A1 that forms and the second terminals A2 and the first electromagnetic switch K1 are in parallel, and the normally opened contact K2-1 of the second electromagnetic switch K2 connects with resistance R; Be connected in parallel on the two ends of the normally opened contact K1-1 of the first electromagnetic switch K1 by the two ends of the normally opened contact K2-1 of the second electromagnetic switch K2 and the series circuit that resistance R consists of; Described control circuit 1 comprises CPU treatment circuit 1-1, controllable silicon drive circuit 1-2, the first electromagnetic switch drive circuit 1-3, the second electromagnetic switch drive circuit 1-4 and switching signal circuit 1-5, the input of controllable silicon drive circuit 1-2, the input of the input of the first electromagnetic switch drive circuit 1-3 and the second electromagnetic switch drive circuit 1-4 is electrically connected with the corresponding output of CPU treatment circuit 1-1 respectively, 2 outputs of controllable silicon drive circuit 1-2 are electrically connected with the control end G1 of unidirectional controllable silicon S CR1 and the control end G2 of unidirectional controllable silicon S CR2 respectively, two outputs of the first electromagnetic switch drive circuit 1-3 are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively, two outputs of the second electromagnetic switch drive circuit 1-4 are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively, and the output of switching signal circuit 1-5 is electrically connected with the input of CPU treatment circuit 1-1.

The first electromagnetic switch K1 of the present invention and the second electromagnetic switch K2 are relay or contactor.

As shown in Figure 2, described the first electromagnetic switch drive circuit 1-3 comprises resistance R 6, triode Q3, diode D2, the first power supply terminal L, N and the first relay J 1, one end of described resistance R 6 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the first relay J 1 connects positive source simultaneously, the end of the normally opened contact J1-1 of the first relay J 1 is electrically connected with the first power supply terminal L, and the other end of the normally opened contact J1-1 of the first relay J 1 and the first power supply terminal N are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively; The second electromagnetic switch drive circuit 1-4 comprises resistance R 7, triode Q4, diode D5, second source terminal L, N and the second relay J 2, one end of described resistance R 7 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 7 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the second relay J 2 connects positive source simultaneously, the end of the normally opened contact J2-1 of the second relay J 2 is electrically connected with second source terminal L, and the other end of the normally opened contact J2-1 of the second relay J 2 and second source terminal N are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively.When the first electromagnetic switch K1 and the second electromagnetic switch K2 are relay or contactor, the first power supply terminal L of the present invention, N and second source terminal L, the terminal that N refers to be electrically connected with the power supply of the coil that drives relay or contactor coil.

Shown in Fig. 2,3, described controllable silicon drive circuit 1-2 comprises resistance R 1, R2, R3, R4, R7, diode D7, D8, the two silicon output of triode Q1 and zero cross fired optical coupler U0; One end of resistance R 1 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 1 is electrically connected with the base stage of triode Q1, the collector electrode of triode Q1 is electrically connected with the first input end of the two silicon output of zero cross fired optical coupler U0, the grounded emitter of triode Q1, the second input of the two silicon output of zero cross fired optical coupler U0 connects power supply by resistance R 2, the first output of the two silicon output of zero cross fired optical coupler U0 and an end of resistance R 3, the control end G1 of the negative pole of diode D7 and unidirectional controllable silicon S CR1 is electrically connected, the other end of resistance R 3 is connected with diode D7 and anodal all is connected with the cathodic electricity of unidirectional controllable silicon S CR1, the second output of the two silicon output of zero cross fired optical coupler U0 is by the end of 4 whiles of resistance R with resistance R 7, the control end G2 of the negative pole of diode D8 and unidirectional controllable silicon S CR2 is electrically connected, and the other end of resistance R 7 is connected with diode D8 anodal the connection with the cathodic electricity of unidirectional controllable silicon S CR2 simultaneously.

Certainly, the mode that controllable silicon drive circuit 1-2 is not limited to foregoing description triggers the conducting of unidirectional controllable silicon S CR1 and unidirectional controllable silicon S CR2, also can adopt as shown in Figure 8 alternate manner to trigger the conducting of unidirectional controllable silicon S CR1 and unidirectional controllable silicon S CR2.

As shown in Figure 8, described controllable silicon drive circuit 1-2 comprises pulse transformer PT, triode Q101, diode D10, D21, D31, resistance R 51, the two ends of the primary coil of described pulse transformer PT connect respectively the two ends of diode D10, one termination power of the primary coil of described pulse transformer PT, and its other end is electrically connected with the collector electrode of triode Q101, the base stage of triode Q101 is electrically connected the grounded emitter of triode by resistance R 51 with the output of CPU treatment circuit 1-1; The first output of the first secondary coil of described pulse transformer PT is electrically connected with the control end G1 of unidirectional controllable silicon S CR1 by diode D21, and its second output is electrically connected with the anode of unidirectional controllable silicon S CR1; The first output of the second subprime coil of described pulse transformer PT is electrically connected with the control end G2 of unidirectional controllable silicon S CR2 by diode D31, and its second output is electrically connected with the anode of unidirectional controllable silicon S CR2.The course of work that this kind mode triggers unidirectional controllable silicon S CR1 and unidirectional controllable silicon S CR2 conducting is: during the alternating current zero passage, CPU treatment circuit 1-1 sends pulsed drive triode Q101 conducting, the first secondary coil of pulse transformer produces pulse output through D21, if exchange this moment when being in positive half cycle, unidirectional controllable silicon S CR1 conducting, unidirectional controllable silicon S CR2 state is then opposite; Alternating current is zero passage again, CPU treatment circuit 1-1 sends pulsed drive triode Q101 conducting, and pulse transformer second subprime coil produces pulse output through D31, exchanges this moment to be in negative half period, unidirectional controllable silicon S CR2 conducting, unidirectional controllable silicon S CR1 state is then opposite.

As shown in Figure 3, described the first electromagnetic switch K1 is magnetic latching relay; Described the first electromagnetic switch drive circuit 1-3 comprises resistance R 5, R6, diode D1, D2, D3, triode Q2, Q3, the first relay J 1 and the second relay J 2; One end of described resistance R 5 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 5 is electrically connected with the base stage of triode Q2, the collector electrode of triode Q2 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D1 respectively, the grounded emitter of triode Q2, the other end of the coil of the negative pole of diode D1 and the first relay J 1 connects power supply simultaneously, the common port JK1-1 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the end of the coil KA1 of the first electromagnetic switch K1, and the in addition common port JK1-2 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the other end of the coil KA1 of the first electromagnetic switch K1; One end of resistance R 6 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the second relay J 2 connects positive source simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D3 and the first relay J 1 and the first relay J 1 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D3 and the normally opened contact J2-1 of the

second relay J

2 and 1 group of normally-open normally-close contact of the first relay J 1 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J2-1 of the second relay J 2; Described the second electromagnetic switch K2 is magnetic latching relay; Described the second electromagnetic switch drive circuit 1-4 comprises resistance R 8, R9, diode D4, D5, D6, triode Q4, Q5, the 3rd relay J 3 and the 4th relay J 4; One end of described resistance R 9 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 9 is electrically connected with the base stage of triode Q5, the collector electrode of triode Q5 is electrically connected with an end of the coil of anodal and the 3rd relay J 3 of diode D4 respectively, the grounded emitter of triode Q5, the other end of the coil of the negative pole of diode D4 and the 3rd relay J 3 connects power supply simultaneously, the common port JK3-1 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the end of the coil KA2 of the second electromagnetic switch K2, and the in addition common port JK3-2 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the other end of the coil KA2 of the second electromagnetic switch K2; One end of resistance R 8 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 8 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the 4th relay J 4 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the 4th relay J 4 connects power supply simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D6 and the first relay J 4 and the first relay J 4 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D6 and the normally opened contact J4-1 of the

4th relay J

4 and 1 group of normally-open normally-close contact of the 3rd relay J 3 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J4-1 of the 4th relay J 4.Described power supply JV refers to the power supply of the coil that drives magnetic latching relay.

Shown in Fig. 2,3, described switching signal circuit 1-5 comprises button S1, S2 and resistance R S1, RS2, the termination power of described resistance R S1, the other end of resistance R S1 are electrically connected with the input of CPU treatment circuit 1-1 and the end of button S1 respectively, the other end ground connection of button S1; The termination power of described resistance R S2, the other end of resistance R S2 are electrically connected with the input of CPU treatment circuit 1-1 and the end of button S2 respectively, the other end ground connection of button S2.

Certainly, switching signal circuit 1-5 is not limited to and adopts key mode to send to drop into and cut out signal, also can adopt as shown in Figure 6 or alternate manner as shown in Figure 7 sends and drops into and cut out signal.

For example shown in Figure 6, described switching signal circuit 1-5 comprises CPU, resistance R 11, R12, R13, R14, photoelectrical coupler U3, U4, two I/O mouths of described CPU respectively with an end of resistance R 11, one end of resistance R 12 is electrically connected, one end of resistance R 11 and an end of resistance R 12 also are electrically connected with the first input end of photoelectrical coupler U3 and the first input end of photoelectrical coupler U4 respectively, the first output of photoelectrical coupler U3 and the first output of photoelectrical coupler U4 are electrically connected with an end of resistance R 13 and an end of resistance R 14 respectively, the other end of described resistance R 11, the other end of resistance R 12, another termination power of the other end of resistance R 13 and resistance R 14, the second input of photoelectrical coupler U3, the second input of the second output and photoelectrical coupler U4, the second output head grounding, an end of described resistance R 13 and an end of resistance R 14 also are electrically connected with the corresponding input of CPU treatment circuit 1-1 respectively.Wherein, it is TLP-521 that photoelectrical coupler U3, U4 preferentially select model, certainly, also can adopt the photoelectrical coupler of other model.

Or for example shown in Figure 7, described switching signal circuit 1-5 comprises CPU, triode Q, resistance R 15, R16, communication integrated chip U5, U6, the output of CPU is electrically connected with the corresponding input of communication integrated chip U5 respectively, the output of communication integrated chip U5 is electrically connected with the input of communication integrated chip U6, the output of communication integrated chip U6 is electrically connected with an end of resistance R 15 and the collector electrode of triode Q respectively, another termination power of resistance R 15, the grounded emitter of triode Q, the base stage of triode Q is electrically connected with an end of resistance R 16, and the output of communication integrated chip U6 and the other end of resistance R 16 are electrically connected with the corresponding input of CPU treatment circuit 1-1 respectively.Wherein, communication integrated chip U5, U6 preferentially select MAX485 communication integrated chip, certainly, also can adopt the communication integrated chip of other model.

When embodiment 1 uses, below all select magnetic latching relay as example take the first electromagnetic switch K1 and the second electromagnetic switch K2.Because reactive power compensation circuit or motor-drive circuit all are three-phase alternating current control circuits, therefore, select 3 groups of controllable silicon compound switch, and two unidirectional controllable silicon S CR1 of every group of controllable silicon compound switch, SCR2 reverse parallel connection and the first binding post A1 and the second binding post A2 that form are electrically connected with reactive power compensation circuit or the corresponding link of motor-drive circuit respectively, simultaneously, two of every group of controllable silicon compound switch unidirectional controllable silicon S CR1, ghyristor circuit and electromagnetic switch K that the SCR2 reverse parallel connection consists of, K2 is electrically connected with corresponding controllable silicon drive circuit and electromagnetic switch drive circuit respectively.Wherein, the first input end series connection power supply of the two silicon output of the zero cross fired in 3 groups of controllable silicon drive circuits optical coupler U0 is electrically connected with the output of CPU treatment circuit 1-1 by the second input of the two silicon output of 1 zero cross fired optical coupler U0; Perhaps the first input end of the two silicon output of the zero cross fired in 3 groups of controllable silicon drive circuits optical coupler U0 connects respectively power supply, and the second input of the two silicon output of each zero cross fired optical coupler U0 is electrically connected with the corresponding output of CPU treatment circuit 1-1 respectively.

The course of work of embodiment 1:

The first, shown in Fig. 2,3, the button S1 or the button S2 that press switching signal circuit 1-5 send input and cut out signal to CPU treatment circuit 1-1, send different control signals after being processed by CPU treatment circuit 1-1 again and deliver to respectively among controllable silicon drive circuit 1-2 and the first electromagnetic switch drive circuit 1-3 and the second electromagnetic switch 1-4, drive respectively ghyristor circuit, the first electromagnetic switch K1 and the second electromagnetic switch K2 of two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection formation.The ghyristor circuit elder generation conducting (voltage zero-cross conducting) that when dropping into, is consisted of by two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection, first, second magnetic latching relay of rear closure K1, K2(are certain, also closed the first magnetic latching relay K1 only); When cutting out, disjunction the first magnetic latching relay K1, if (closed the first magnetic latching relay K1 only when dropping into, closed the second magnetic latching relay K2 of elder generation when then cutting out, disjunction the first magnetic latching relay K1 again), electric current forms voltage drop by the normally opened contact K2-1 of the second magnetic latching relay K2 and the series circuit of resistance R formation, i.e. two unidirectional controllable silicon S CR1, between SCR2 reverse parallel connection and the first binding post A1 that forms and the second binding post A2 pressure drop is arranged, at this moment, trigger two unidirectional controllable silicon S CR1, the ghyristor circuit conducting (triggering during zero passage) that the SCR2 reverse parallel connection consists of, the operating current overwhelming majority two the unidirectional controllable silicon S CR1 that flow through, the ghyristor circuit that the SCR2 reverse parallel connection consists of, again disjunction the second magnetic latching relay K2, latter two unidirectional controllable silicon S CR1, the ghyristor circuit that the SCR2 reverse parallel connection consists of disconnects.

The second, as shown in Figure 6, CPU by described switching signal circuit 1-5 sends input and cuts out signal (high and low level) to CPU treatment circuit 1-1, send different control signals after being processed by CPU treatment circuit 1-1 again and deliver to respectively among controllable silicon drive circuit 1-2 and the first electromagnetic switch drive circuit 1-3 and the second electromagnetic switch 1-4, drive respectively ghyristor circuit, the first electromagnetic switch K1 and the second electromagnetic switch K2 of two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection formation.Concrete input is identical with above-mentioned the first course of work with the course of work that cuts out, and just seldom sets forth at this.

The third, as shown in Figure 7, CPU by described switching signal circuit 1-5 sends input and cuts out signal to CPU treatment circuit 1-1 by the mode of communication, send different control signals after being processed by CPU treatment circuit 1-1 again and deliver to respectively among controllable silicon drive circuit 1-2 and the first electromagnetic switch drive circuit 1-3 and the second electromagnetic switch 1-4, drive respectively ghyristor circuit, the first electromagnetic switch K1 and the second electromagnetic switch K2 of two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection formation.Concrete input is identical with above-mentioned the first course of work with the course of work that cuts out, and just seldom sets forth at this.

Embodiment 2

Shown in Fig. 1,4,5,6,7,8, a kind of combination switch of intelligent operating passing zero, comprise control circuit 1 and controllable silicon compound switch 2, and its: described controllable silicon compound switch 2 comprises two unidirectional controllable silicon S CR1, SCR2, the first electromagnetic switch K1, the second electromagnetic switch K2 and resistance R, described two unidirectional controllable silicon S CR1, SCR2 have respectively control end G1 and control end G2, and two unidirectional controllable silicon S CR1, SCR2 reverse parallel connections also form the first terminals A1 and the second terminals A2, and the normally opened contact K2-1 of the second electromagnetic switch K2 connects with resistance R; Two ends by the normally opened contact K2-1 of the second electromagnetic switch K2 and the series circuit that resistance R consists of are in parallel with the first terminals A1 and the second terminals A2 that are also formed by two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection; The two ends of the normally opened contact K1-1 of the first electromagnetic switch K1 are connected in parallel on the two ends of resistance R; Described control circuit 1 comprises CPU treatment circuit 1-1, controllable silicon drive circuit 1-2, the first electromagnetic switch drive circuit 1-3, the second electromagnetic switch drive circuit 1-4 and switching signal circuit 1-5, the input of controllable silicon drive circuit 1-2, the input of the input of the first electromagnetic switch drive circuit 1-3 and the second electromagnetic switch drive circuit 1-4 is electrically connected with the corresponding output of CPU treatment circuit 1-1 respectively, 2 outputs of controllable silicon drive circuit 1-2 are electrically connected with the control end G1 of unidirectional controllable silicon S CR1 and the control end G2 of unidirectional controllable silicon S CR2 respectively, two outputs of the first electromagnetic switch drive circuit 1-3 are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively, two outputs of the second electromagnetic switch drive circuit 1-4 are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively, and the output of switching signal circuit 1-5 is electrically connected with the input of CPU treatment circuit 1-1.

As shown in Figure 4, described the first electromagnetic switch drive circuit 1-3 comprises resistance R 6, triode Q3, diode D2, the first power supply terminal L, N and the first relay J 1, one end of described resistance R 6 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the first relay J 1 connects positive source simultaneously, the end of the normally opened contact J1-1 of the first relay J 1 is electrically connected with the first power supply terminal L, and the other end of the normally opened contact J1-1 of the first relay J 1 and the first power supply terminal N are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively; The second electromagnetic switch drive circuit 1-4 comprises resistance R 7, triode Q4, diode D5, second source terminal L, N and the second relay J 2, one end of described resistance R 7 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 7 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the second relay J 2 connects positive source simultaneously, the end of the normally opened contact J2-1 of the second relay J 2 is electrically connected with second source terminal L, and the other end of the normally opened contact J2-1 of the second relay J 2 and second source terminal N are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively.When the first electromagnetic switch K1 and the second electromagnetic switch K2 are relay or contactor, the first power supply terminal L of the present invention, N and second source terminal L, the terminal that N refers to be electrically connected with the power supply of the coil that drives relay or contactor coil.

Shown in Fig. 4,5, described controllable silicon drive circuit 1-2 comprises resistance R 1, R2, R3, R4, R7, diode D7, D8, the two silicon output of triode Q1 and zero cross fired optical coupler U0; One end of resistance R 1 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 1 is electrically connected with the base stage of triode Q1, the collector electrode of triode Q1 is electrically connected with the first input end of the two silicon output of zero cross fired optical coupler U0, the grounded emitter of triode Q1, the second input of the two silicon output of zero cross fired optical coupler U0 connects power supply by resistance R 2, the first output of the two silicon output of zero cross fired optical coupler U0 and an end of resistance R 3, the control end G1 of the negative pole of diode D7 and unidirectional controllable silicon S CR1 is electrically connected, the other end of resistance R 3 is connected with diode D7 and anodal all is connected with the cathodic electricity of unidirectional controllable silicon S CR1, the second output of the two silicon output of zero cross fired optical coupler U0 is by the end of 4 whiles of resistance R with resistance R 7, the control end G2 of the negative pole of diode D8 and unidirectional controllable silicon S CR2 is electrically connected, and the other end of resistance R 7 is connected with diode D8 anodal the connection with the cathodic electricity of unidirectional controllable silicon S CR2 simultaneously.

As shown in Figure 5, described the first electromagnetic switch K1 is magnetic latching relay; Described the first electromagnetic switch drive circuit 1-3 comprises resistance R 5, R6, diode D1, D2, D3, triode Q2, Q3, the first relay J 1 and the second relay J 2; One end of described resistance R 5 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 5 is electrically connected with the base stage of triode Q2, the collector electrode of triode Q2 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D1 respectively, the grounded emitter of triode Q2, the other end of the coil of the negative pole of diode D1 and the first relay J 1 connects power supply simultaneously, the common port JK1-1 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the end of the coil KA1 of the first electromagnetic switch K1, and the in addition common port JK1-2 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the other end of the coil KA1 of the first electromagnetic switch K1; One end of resistance R 6 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the second relay J 2 connects positive source simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D3 and the first relay J 1 and the first relay J 1 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D3 and the normally opened contact J2-1 of the second relay J 2 and 1 group of normally-open normally-close contact of the first relay J 1 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J2-1 of the second relay J 2; Described the second electromagnetic switch K2 is magnetic latching relay; Described the second electromagnetic switch drive circuit 1-4 comprises resistance R 8, R9, diode D4, D5, D6, triode Q4, Q5, the 3rd relay J 3 and the 4th relay J 4; One end of described resistance R 9 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 9 is electrically connected with the base stage of triode Q5, the collector electrode of triode Q5 is electrically connected with an end of the coil of anodal and the 3rd relay J 3 of diode D4 respectively, the grounded emitter of triode Q5, the other end of the coil of the negative pole of diode D4 and the 3rd relay J 3 connects power supply simultaneously, the common port JK3-1 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the end of the coil KA2 of the second electromagnetic switch K2, and the in addition common port JK3-2 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the other end of the coil KA2 of the second electromagnetic switch K2; One end of resistance R 8 is electrically connected with the output of CPU treatment circuit 1-1, the other end of resistance R 8 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the 4th relay J 4 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the 4th relay J 4 connects power supply simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D6 and the first relay J 4 and the first relay J 4 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D6 and the normally opened contact J4-1 of the 4th relay J 4 and 1 group of normally-open normally-close contact of the 3rd relay J 3 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J4-1 of the 4th relay J 4.Described power supply JV refers to the power supply of the coil that drives magnetic latching relay.

Shown in Fig. 4,5, described switching signal circuit 1-5 comprises button S1, S2 and resistance R S1, RS2, the termination power of described resistance R S1, the other end of resistance R S1 are electrically connected with the input of CPU treatment circuit 1-1 and the end of button S1 respectively, the other end ground connection of button S1; The termination power of described resistance R S2, the other end of resistance R S2 are electrically connected with the input of CPU treatment circuit 1-1 and the end of button S2 respectively, the other end ground connection of button S2.

(electric capacity among the reactive power compensation circuit figure, how not narration?) when embodiment 2 uses, below all select magnetic latching relay as example take the first electromagnetic switch K1 and the second electromagnetic switch K2.Because reactive power compensation circuit or motor-drive circuit all are three-phase alternating current control circuits, therefore, select 3 groups of controllable silicon compound switch, and two unidirectional controllable silicon S CR1 of every group of controllable silicon compound switch, SCR2 reverse parallel connection and the first binding post A1 and the second binding post A2 that form are electrically connected with reactive power compensation circuit or the corresponding link of motor-drive circuit respectively, simultaneously, two of every group of controllable silicon compound switch unidirectional controllable silicon S CR1, ghyristor circuit and electromagnetic switch K that the SCR2 reverse parallel connection consists of, K2 is electrically connected with corresponding controllable silicon drive circuit and electromagnetic switch drive circuit respectively.Wherein, the first input end series connection power supply of the two silicon output of the zero cross fired in 3 groups of controllable silicon drive circuits optical coupler U0 is electrically connected with the output of CPU treatment circuit 1-1 by the second input of the two silicon output of 1 zero cross fired optical coupler U0; Perhaps the first input end of the two silicon output of the zero cross fired in 3 groups of controllable silicon drive circuits optical coupler U0 connects respectively power supply, and the second input of the two silicon output of each zero cross fired optical coupler U0 is electrically connected with the corresponding output of CPU treatment circuit 1-1 respectively.

The course of work of embodiment 2:

The first, shown in Fig. 4,5, the button S1 or the button S2 that press switching signal circuit 1-5 send input and cut out signal to CPU treatment circuit 1-1, send different control signals after being processed by CPU treatment circuit 1-1 again and deliver to respectively among controllable silicon drive circuit 1-2 and the first electromagnetic switch drive circuit 1-3 and the second electromagnetic switch 1-4, drive respectively ghyristor circuit, the first electromagnetic switch K1 and the second electromagnetic switch K2 of two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection formation.The ghyristor circuit elder generation conducting (voltage zero-cross conducting) that when dropping into, is consisted of by two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection, first, second magnetic latching relay of rear closure K1, K2; When cutting out, disjunction the first magnetic latching relay K1, electric current forms voltage drop by the normally opened contact K2-1 of the second magnetic latching relay K2 and the series circuit of resistance R formation, i.e. two unidirectional controllable silicon S CR1, between SCR2 reverse parallel connection and the first binding post A1 that forms and the second binding post A2 pressure drop is arranged, at this moment, trigger two unidirectional controllable silicon S CR1, the ghyristor circuit conducting (triggering during zero passage) that the SCR2 reverse parallel connection consists of, the operating current overwhelming majority two the unidirectional controllable silicon S CR1 that flow through, the ghyristor circuit that the SCR2 reverse parallel connection consists of, again disjunction the second magnetic latching relay K2, latter two unidirectional controllable silicon S CR1, the ghyristor circuit that the SCR2 reverse parallel connection consists of disconnects.

It is the 89C2051 integrated circuit that single-chip microcomputer among the CPU treatment circuit 1-1 of the present invention is preferentially selected model, and it is the two silicon output of the zero cross fired optical coupler of MOC3061 or MOC3062 that the two silicon output of zero cross fired optical coupler U0 preferentially selects model.Certainly, also can adopt other model.

The present invention can be applicable to the capacitance compensation field, and the occasion that needs the control circuit break-make.

Hence one can see that, the present invention is when cutting out, satisfied during ghyristor circuit conducting that two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection consist of pressure drop and two necessary conditions of triggering signal have been arranged, the electromagnetic switch contact is not fragile yet, greatly improved combination switch work reliability and operating efficiency, prolonged working life, power supply quality is high, can apply to frequent switching, requires response speed and the very large occasion of switching precision.

The above only is preferred implementation of the present invention; but be not limited to this; be noted that for those skilled in the art; under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1. the combination switch of an intelligent operating passing zero comprises control circuit (1) and controllable silicon compound switch (2), it is characterized in that:

A, described controllable silicon compound switch (2) comprises two unidirectional controllable silicon S CR1, SCR2, the first electromagnetic switch K1, the second electromagnetic switch K2 and resistance R, described two unidirectional controllable silicon S CR1, SCR2 has respectively control end G1 and control end G2, and two unidirectional controllable silicon S CR1, the SCR2 reverse parallel connection also forms the first terminals A1 and the second terminals A2, two unidirectional controllable silicon S CR1, the two ends of the normally opened contact K1-1 of SCR2 reverse parallel connection and the first terminals A1 that forms and the second terminals A2 and the first electromagnetic switch K1 are in parallel, and the normally opened contact K2-1 of the second electromagnetic switch K2 connects with resistance R; Be connected in parallel on the two ends of the normally opened contact K1-1 of the first electromagnetic switch K1 by the two ends of the normally opened contact K2-1 of the second electromagnetic switch K2 and the series circuit that resistance R consists of;

B, described control circuit (1) comprises CPU treatment circuit (1-1), controllable silicon drive circuit (1-2), the first electromagnetic switch drive circuit (1-3), the second electromagnetic switch drive circuit (1-4) and switching signal circuit (1-5), the input of controllable silicon drive circuit (1-2), the input of the input of the first electromagnetic switch drive circuit (1-3) and the second electromagnetic switch drive circuit (1-4) is electrically connected with the corresponding output of CPU treatment circuit (1-1) respectively, 2 outputs of controllable silicon drive circuit (1-2) are electrically connected with the control end G1 of unidirectional controllable silicon S CR1 and the control end G2 of unidirectional controllable silicon S CR2 respectively, two outputs of the first electromagnetic switch drive circuit (1-3) are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively, two outputs of the second electromagnetic switch drive circuit (1-4) are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively, and the output of switching signal circuit (1-5) is electrically connected with the input of CPU treatment circuit (1-1).

2. the combination switch of intelligent operating passing zero according to claim 1, it is characterized in that: described the first electromagnetic switch K1 and the second electromagnetic switch K2 are relay or contactor.

3. the combination switch of intelligent operating passing zero according to claim 2, it is characterized in that: described the first electromagnetic switch drive circuit (1-3) comprises resistance R 6, triode Q3, diode D2, the first power supply terminal L, N and the first relay J 1, one end of described resistance R 6 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the first relay J 1 connects positive source simultaneously, the end of the normally opened contact J1-1 of the first relay J 1 is electrically connected with the first power supply terminal L, and the other end of the normally opened contact J1-1 of the first relay J 1 and the first power supply terminal N are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively; The second electromagnetic switch drive circuit (1-4) comprises resistance R 7, triode Q4, diode D5, second source terminal L, N and the second relay J 2, one end of described resistance R 7 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 7 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the second relay J 2 connects positive source simultaneously, the end of the normally opened contact J2-1 of the second relay J 2 is electrically connected with second source terminal L, and the other end of the normally opened contact J2-1 of the second relay J 2 and second source terminal N are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively.

4. the combination switch of intelligent operating passing zero according to claim 1, it is characterized in that: described controllable silicon drive circuit (1-2) comprises resistance R 1, R2, R3, R4, R7, diode D7, D8, the two silicon output of triode Q1 and zero cross fired optical coupler U0; One end of resistance R 1 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 1 is electrically connected with the base stage of triode Q1, the collector electrode of triode Q1 is electrically connected with the first input end of the two silicon output of zero cross fired optical coupler U0, the grounded emitter of triode Q1, the second input of the two silicon output of zero cross fired optical coupler U0 connects power supply by resistance R 2, the first output of the two silicon output of zero cross fired optical coupler U0 and an end of resistance R 3, the control end G1 of the negative pole of diode D7 and unidirectional controllable silicon S CR1 is electrically connected, the other end of resistance R 3 is connected with diode D7 and anodal all is connected with the cathodic electricity of unidirectional controllable silicon S CR1, the second output of the two silicon output of zero cross fired optical coupler U0 is by the end of 4 whiles of resistance R with resistance R 7, the control end G2 of the negative pole of diode D8 and unidirectional controllable silicon S CR2 is electrically connected, and the other end of resistance R 7 is connected with diode D8 anodal the connection with the cathodic electricity of unidirectional controllable silicon S CR2 simultaneously.

5. the combination switch of intelligent operating passing zero according to claim 1, it is characterized in that: described the first electromagnetic switch K1 is magnetic latching relay; Described the first electromagnetic switch drive circuit (1-3) comprises resistance R 5, R6, diode D1, D2, D3, triode Q2, Q3, the first relay J 1 and the second relay J 2; One end of described resistance R 5 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 5 is electrically connected with the base stage of triode Q2, the collector electrode of triode Q2 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D1 respectively, the grounded emitter of triode Q2, the other end of the coil of the negative pole of diode D1 and the first relay J 1 connects power supply simultaneously, the common port JK1-1 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the end of the coil KA1 of the first electromagnetic switch K1, and the in addition common port JK1-2 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the other end of the coil KA1 of the first electromagnetic switch K1; One end of resistance R 6 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the second relay J 2 connects positive source simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D3 and the first relay J 1 and the first relay J 1 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D3 and the normally opened contact J2-1 of the second relay J 2 and 1 group of normally-open normally-close contact of the first relay J 1 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J2-1 of the second relay J 2; Described the second electromagnetic switch K2 is magnetic latching relay; Described the second electromagnetic switch drive circuit (1-4) comprises resistance R 8, R9, diode D4, D5, D6, triode Q4, Q5, the 3rd relay J 3 and the 4th relay J 4; One end of described resistance R 9 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 9 is electrically connected with the base stage of triode Q5, the collector electrode of triode Q5 is electrically connected with an end of the coil of anodal and the 3rd relay J 3 of diode D4 respectively, the grounded emitter of triode Q5, the other end of the coil of the negative pole of diode D4 and the 3rd relay J 3 connects power supply simultaneously, the common port JK3-1 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the end of the coil KA2 of the second electromagnetic switch K2, and the in addition common port JK3-2 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the other end of the coil KA2 of the second electromagnetic switch K2; One end of resistance R 8 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 8 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the 4th relay J 4 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the 4th relay J 4 connects power supply simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D6 and the first relay J 4 and the first relay J 4 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D6 and the normally opened contact J4-1 of the 4th relay J 4 and 1 group of normally-open normally-close contact of the 3rd relay J 3 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J4-1 of the 4th relay J 4.

6. the combination switch of an intelligent operating passing zero comprises control circuit (1) and controllable silicon compound switch (2), it is characterized in that:

A, described controllable silicon compound switch (2) comprise two unidirectional controllable silicon S CR1, SCR2, the first electromagnetic switch K1, the second electromagnetic switch K2 and resistance R, described two unidirectional controllable silicon S CR1, SCR2 have respectively control end G1 and control end G2, and two unidirectional controllable silicon S CR1, SCR2 reverse parallel connections also form the first terminals A1 and the second terminals A2, and the normally opened contact K2-1 of the second electromagnetic switch K2 connects with resistance R; Two ends by the normally opened contact K2-1 of the second electromagnetic switch K2 and the series circuit that resistance R consists of are in parallel with the first terminals A1 and the second terminals A2 that are also formed by two unidirectional controllable silicon S CR1, SCR2 reverse parallel connection; The two ends of the normally opened contact K1-1 of the first electromagnetic switch K1 are connected in parallel on the two ends of resistance R;

7. the combination switch of intelligent operating passing zero according to claim 6, it is characterized in that: described the first electromagnetic switch K1 and the second electromagnetic switch K2 are relay or contactor.

8. the combination switch of intelligent operating passing zero according to claim 7, it is characterized in that: described the first electromagnetic switch drive circuit (1-3) comprises resistance R 6, triode Q3, diode D2, the first power supply terminal L, N and the first relay J 1, one end of described resistance R 6 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the first relay J 1 connects positive source simultaneously, the end of the normally opened contact J1-1 of the first relay J 1 is electrically connected with the first power supply terminal L, and the other end of the normally opened contact J1-1 of the first relay J 1 and the first power supply terminal N are electrically connected with the two ends of the coil KA1 of the first electromagnetic switch K1 respectively; The second electromagnetic switch drive circuit (1-4) comprises resistance R 7, triode Q4, diode D5, second source terminal L, N and the second relay J 2, one end of described resistance R 7 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 7 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the second relay J 2 connects positive source simultaneously, the end of the normally opened contact J2-1 of the second relay J 2 is electrically connected with second source terminal L, and the other end of the normally opened contact J2-1 of the second relay J 2 and second source terminal N are electrically connected with the two ends of the coil KA2 of the second electromagnetic switch K2 respectively.

9. the combination switch of intelligent operating passing zero according to claim 6, it is characterized in that: described controllable silicon drive circuit (1-2) comprises resistance R 1, R2, R3, R4, R7, diode D7, D8, the two silicon output of triode Q1 and zero cross fired optical coupler U0; One end of resistance R 1 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 1 is electrically connected with the base stage of triode Q1, the collector electrode of triode Q1 is electrically connected with the first input end of the two silicon output of zero cross fired optical coupler U0, the grounded emitter of triode Q1, the second input of the two silicon output of zero cross fired optical coupler U0 connects power supply by resistance R 2, the first output of the two silicon output of zero cross fired optical coupler U0 and an end of resistance R 3, the control end G1 of the negative pole of diode D7 and unidirectional controllable silicon S CR1 is electrically connected, the other end of resistance R 3 is connected with diode D7 and anodal all is connected with the cathodic electricity of unidirectional controllable silicon S CR1, the second output of the two silicon output of zero cross fired optical coupler U0 is by the end of 4 whiles of resistance R with resistance R 7, the control end G2 of the negative pole of diode D8 and unidirectional controllable silicon S CR2 is electrically connected, and the other end of resistance R 7 is connected with diode D8 anodal the connection with the cathodic electricity of unidirectional controllable silicon S CR2 simultaneously.

10. the combination switch of intelligent operating passing zero according to claim 6, it is characterized in that: described the first electromagnetic switch K1 is magnetic latching relay; Described the first electromagnetic switch drive circuit (1-3) comprises resistance R 5, R6, diode D1, D2, D3, triode Q2, Q3, the first relay J 1 and the second relay J 2; One end of described resistance R 5 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 5 is electrically connected with the base stage of triode Q2, the collector electrode of triode Q2 is electrically connected with an end of the coil of anodal and the first relay J 1 of diode D1 respectively, the grounded emitter of triode Q2, the other end of the coil of the negative pole of diode D1 and the first relay J 1 connects power supply simultaneously, the common port JK1-1 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the end of the coil KA1 of the first electromagnetic switch K1, and the in addition common port JK1-2 of 1 group of normally-open normally-close contact of the first relay J 1 is electrically connected with the other end of the coil KA1 of the first electromagnetic switch K1; One end of resistance R 6 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 6 is electrically connected with the base stage of triode Q3, the collector electrode of triode Q3 is electrically connected with an end of the coil of anodal and the second relay J 2 of diode D2 respectively, the grounded emitter of triode Q3, the other end of the coil of the negative pole of diode D2 and the second relay J 2 connects positive source simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D3 and the first relay J 1 and the first relay J 1 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D3 and the normally opened contact J2-1 of the second relay J 2 and 1 group of normally-open normally-close contact of the first relay J 1 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J2-1 of the second relay J 2; Described the second electromagnetic switch K2 is magnetic latching relay; Described the second electromagnetic switch drive circuit (1-4) comprises resistance R 8, R9, diode D4, D5, D6, triode Q4, Q5, the 3rd relay J 3 and the 4th relay J 4; One end of described resistance R 9 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 9 is electrically connected with the base stage of triode Q5, the collector electrode of triode Q5 is electrically connected with an end of the coil of anodal and the 3rd relay J 3 of diode D4 respectively, the grounded emitter of triode Q5, the other end of the coil of the negative pole of diode D4 and the 3rd relay J 3 connects power supply simultaneously, the common port JK3-1 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the end of the coil KA2 of the second electromagnetic switch K2, and the in addition common port JK3-2 of 1 group of normally-open normally-close contact of the 3rd relay J 3 is electrically connected with the other end of the coil KA2 of the second electromagnetic switch K2; One end of resistance R 8 is electrically connected with the output of CPU treatment circuit (1-1), the other end of resistance R 8 is electrically connected with the base stage of triode Q4, the collector electrode of triode Q4 is electrically connected with an end of the coil of anodal and the 4th relay J 4 of diode D5 respectively, the grounded emitter of triode Q4, the other end of the coil of the negative pole of diode D5 and the 4th relay J 4 connects power supply simultaneously, the normal-closed end of 1 group of normally-open normally-close contact of the negative pole of diode D6 and the first relay J 4 and the first relay J 4 in addition Chang Kaiduan of 1 group of normally-open normally-close contact meet power supply JV, the Chang Kaiduan of the end of the positive pole of diode D6 and the normally opened contact J4-1 of the 4th relay J 4 and 1 group of normally-open normally-close contact of the 3rd relay J 3 and the first relay J 1 in addition normal-closed end of 1 group of normally-open normally-close contact are electrically connected another termination power cathode of the normally opened contact J4-1 of the 4th relay J 4.