CN103022096A - Terminal structure of high-voltage semiconductor device and method for manufacturing terminal structure - Google Patents
Terminal structure of high-voltage semiconductor device and method for manufacturing terminal structure Download PDFInfo
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- CN103022096A CN103022096A CN2012105801153A CN201210580115A CN103022096A CN 103022096 A CN103022096 A CN 103022096A CN 2012105801153 A CN2012105801153 A CN 2012105801153A CN 201210580115 A CN201210580115 A CN 201210580115A CN 103022096 A CN103022096 A CN 103022096A
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Abstract
The invention provides a terminal structure of a high-voltage semiconductor device and a method for manufacturing the terminal structure. The terminal structure comprises a semiconductor substrate of a first conductive type, a doped region of a second conductive type, an isolation dielectric layer, an extraction electrode and a field plate, wherein the doped region is positioned inside the semiconductor substrate, the isolation dielectric layer is positioned on a partial region of the surface of the semiconductor substrate, the extraction electrode is positioned on the surface of the doped region, the field plate is positioned on a partial region of the surface of the isolation dielectric layer, and the electrode is connected with the field plate. The terminal structure is characterized in that the isolation dielectric layer is provided with groove structures positioned below the field plate. The invention further provides the method for manufacturing the terminal structure of the high-voltage semiconductor device. The terminal structure and the method have the advantages that the groove structures are arranged on the dielectric layer and are positioned below the field plate, so that the distance from the field plate to the semiconductor substrate is shortened, a coupling effect between the field plate and the substrate is enhanced, electric-line-of-force absorption capacity of the field plate is effectively improved, the intensity of an electric field in the range of a region between two peak electric fields below outer boundaries of an original substrate and an original field plate is integrally improved, breakdown voltage is increased, and a process for manufacturing the terminal structure is simple.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, relate in particular to a kind of field plate improves laterally or the longitudinal high-pressure semiconductor device is withstand voltage terminal structure and preparation method thereof that utilizes.
Background technology
Along with the continuous research and development of people to power semiconductor device module, turn-off thyristor (Gate Turn-Off Thyristor has appearred on the market, GTO), double diffusion metal-oxide semiconductor fieldeffect transistor (Double-diffused MOSFET, DMOS), insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, the multiple power device such as IGBT), its performance is become better and better, and uses also more and more extensive.The sales volume of power integrated circuit presents and significantly increases progressively year by year trend, has been penetrated into the numerous areas of industry and consumption market.The performance index of a power device mainly can be passed judgment on from a plurality of angles such as puncture voltage, maximum current, maximum power, conducting resistance, area, speed.In actual applications, for the requirement of different performance index, can select suitable power device.
In order to improve the puncture voltage of device, generally can adopt terminal technology commonly used such as using field plate or field limiting ring, or increase the radius of curvature of PN junction corner by enlarging junction depth, to reduce peak value electric field intensity.Fig. 1 is the terminal structure of prior art mesohigh semiconductor device.Generally, for the field plate that is connected in semiconductor surface, as shown in Figure 1, comprise: the Semiconductor substrate 11 of the first conduction type, be positioned at the doped region 12 of the second conduction type of Semiconductor substrate 11, be positioned at the spacer medium layer 13 of semiconductor substrate surface subregion, and be positioned at the electrode 15 on described doped region 12 surfaces and the field plate 14 on the described spacer medium layer 21 surface portion zone, described electrode 15 links to each other with described field plate 14.It is as follows that this terminal structure improves withstand voltage theoretical explanation: for ease of describing, choosing the first conduction type is that P type, the second conduction type are N-type, mix the diode structure of drawing as example take P type substrate, N+, introduce field plate, field plate and surface, P district are coupled, part power line ends at surface, P district from field plate, affects the electromotive force on surface, P district, namely is equivalent to the effect of additional charge.The electric field that additional charge causes makes depletion region advance in body on the one hand, is equivalent on the one hand near the surface field original transverse p/n junction depletion region electric field of opposite direction that superposeed, thereby has reduced the electric field strength of PN junction surf zone own.But the P district semiconductor surface of correspondence below the field plate external boundary is because the electric field Overlay herein that additional charge causes can cause producing a spike electric field.By adjusting the width of field plate, so that the spike electric field that field plate causes is consistent with PN junction electric field strength, can obtain optimal withstand voltage effect.
In order further to improve the voltage endurance capability of device, need make the semiconductor depletion region of field plate below bear as far as possible large voltage, electric field strength in this regional extent is all reached or near critical electric field strength.A kind of structure that satisfies above-mentioned requirements is dielectric layer to be done ramp-like, forms the slope Metal field plate.General, by form the perishable layer of one deck on the dielectric layer surface, behind the photoetching opening window, utilize the selection ratio of etchant solution, namely corrode the speed of top dielectric layer greater than the speed of corrosion lower floor, form slope dielectric layer structure, referenced patent number is CN1181562C, the Chinese patent of CN101752208A.Perhaps also can utilize the gray-level light lithography, form curved surface slope dielectric layer structure, with reference to US Patent No. 2004/0129993A1.But the technology difficulty and the complexity that form the slope dielectric layer are all higher.In addition, also can adopt sandwich construction, allow the part field plate that up and down overlapping region is arranged, make to have coupling between the field plate, further adjust Electric Field Distribution, with reference to Chinese patent CN 200610138829.3.Yet this structure need to be through repeatedly deposit, photoetching, the etching of dielectric layer and metal level, and preparation has brought complexity to a certain degree to technique.
Summary of the invention
For overcoming the problems referred to above, the object of the present invention is to provide a kind of technique simply to improve the terminal structure and preparation method thereof of the high-voltage semi-conductor device of voltage endurance capability.
The invention provides a kind of terminal structure of high-voltage semi-conductor device, comprise: the Semiconductor substrate of the first conduction type, be positioned at the doped region of the second conduction type of described Semiconductor substrate, be positioned at the spacer medium layer on the described semiconductor substrate surface subregion, and be positioned at the extraction electrode on described doped region surface and the field plate on the described spacer medium layer surface portion zone, described electrode links to each other with described field plate, it is characterized in that, the spacer medium layer of described field plate below comprises groove structure.
Preferably, described groove is covered by described field plate.
Preferably, the thickness range of described spacer medium layer is 0.1～3 μ m.
Preferably, the degree of depth of described groove is 1/4～3/4 of described spacer medium layer thickness.
Preferably, the ratio of the degree of depth of the width of described groove and described groove is 1/2～2.
The present invention also provides a kind of preparation method of terminal structure of high-voltage semi-conductor device, comprising:
Step S01: the Semiconductor substrate that the first conduction type is provided;
Step S02: form the spacer medium layer at described substrate surface;
Step S03: in the subregion of described spacer medium layer, form groove structure through photoetching, etching;
Step S04: through photoetching, etching, in described substrate surface definition electrode draw-out area;
Step S05: the doped region that in described substrate, forms the second conduction type;
Step S06: form electrode and field plate in surface and the described spacer medium layer surface portion zone of described doped region respectively.
Preferably, described groove is covered by described field plate.
Preferably, the thickness range of described spacer medium layer is 0.1～3 μ m.
Preferably, the degree of depth of described groove is 1/4～3/4 of described spacer medium layer thickness.
Preferably, the ratio of the degree of depth of the width of described groove and described groove is 1/2～2.
Terminal structure of high-voltage semi-conductor device of the present invention and preparation method thereof has mainly utilized the field plate below to improve voltage endurance capability with the dielectric layer of some groove structures.The distance of Metal field plate and Semiconductor substrate has strengthened the coupling between field plate and the substrate because the existence of groove has furthered, improved should the zone electric field strength.Like this, by the dielectric layer below field plate several groove structures are set, the effect that allows field plate absorb power line is brought into play better, can be so that the electric field strength Integral lifting in the regional extent between two peak value electric fields of original PN junction and field plate external boundary below, thereby improved puncture voltage, and the technique of formation groove structure dielectric layer is very simple again.
Description of drawings
Fig. 1 is the schematic diagram of the terminal structure of prior art mesohigh semiconductor device
Fig. 2 is the structural representation of a preferred embodiment of the terminal structure of a kind of high-voltage semi-conductor device of the present invention
Fig. 3 is the process chart of a kind of preparation method of terminal structure of high-voltage semi-conductor device in the preparation above-mentioned preferred embodiment of the present invention
Fig. 4～8th, the schematic cross-section of the preparation method's of the terminal structure of a kind of high-voltage semi-conductor device in the above-mentioned preferred embodiment of the present invention concrete preparation process
Fig. 9 is the electric field strength of above-mentioned preferred embodiment mesohigh semiconductor device terminal structure of the present invention and the comparison diagram of prior art.
Embodiment
Terminal structure and preparation method to high-voltage semi-conductor device provided by the invention is described in further detail below in conjunction with the drawings and specific embodiments.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-accurately ratio, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
The invention provides a kind of terminal structure of high-voltage semi-conductor device.See also Fig. 2, Fig. 2 is the structural representation of preferred embodiment of the terminal structure of a kind of high-voltage semi-conductor device of the present invention.For convenience of explanation, in this embodiment, comprise concrete P type and N-type district, and take P type silicon substrate 1 as example, but this is not used in and limits the scope of the invention.As shown in Figure 2, the terminal structure of the high-voltage semi-conductor device in the present embodiment comprises: P type semiconductor substrate 1, be positioned at the N-type doped region 5 of P type semiconductor substrate, spacer medium layer 2 on the P type semiconductor substrate 1 surface portion zone, and the extraction electrode 8 and the field plate 6 that is positioned on the spacer medium layer 2 surface portion zone that are positioned at N-type doped region 5 surfaces, described extraction electrode 8 links to each other with described field plate 6, wherein, spacer medium layer 2 comprises groove structure, and groove is covered by field plate 6.Need to prove, among the present invention, the field plate material can but to be not limited to be metal Ti/Al, Ti/TiN/Al, the thickness of field plate 6 can but to be not limited to be 3 μ m.
In the present invention, Semiconductor substrate can but to be not limited to be the semi-conducting materials such as silicon, germanium or germanium silicon, spacer medium layer 2 can but to be not limited to be one or more mixtures of silicon dioxide, silicon nitride, hafnium oxide, zirconium dioxide or other insulating medium layers, Semiconductor substrate is p type single crystal silicon substrate 1 in the present embodiment, and spacer medium layer 2 is silicon dioxide.Among the present invention, the thickness range of spacer medium layer 2 is 0.1～3 μ m, and the degree of depth of groove is 1/4～3/4 of spacer medium layer 2 thickness, and the ratio of the hierarchy structure of groove is 1/2～2.
Existing 3-8 by reference to the accompanying drawings further describes the preparation method of the terminal structure of above-mentioned high-voltage semi-conductor device in the present embodiment of the present invention.
Fig. 3 is the process chart of a kind of preparation method of terminal structure of high-voltage semi-conductor device in the preparation above-mentioned preferred embodiment of the present invention.
Fig. 4～8th, the schematic cross-section of the preparation method's of the terminal structure of a kind of high-voltage semi-conductor device in the above-mentioned preferred embodiment of the present invention concrete preparation process.Among the present invention, Semiconductor substrate can but to be not limited to be the semi-conducting materials such as silicon, germanium or germanium silicon, for convenience of explanation, in this embodiment, comprise concrete P type and N-type district, and take P type silicon substrate 1 as example, but this is not used in and limits the scope of the invention.
See also Fig. 3, the preparation method's of the terminal structure of a kind of high-voltage semi-conductor device of present embodiment concrete steps are as follows:
Step S01: a P type silicon substrate 1 is provided;
Step S02: see also Fig. 4, adopt but be not limited to chemical vapour deposition technique to form spacer medium layer 2 on P type silicon substrate 1 surface; Spacer medium layer 2 can but to be not limited to be one or more mixtures of silicon dioxide, silicon nitride, hafnium oxide, zirconium dioxide or other insulating medium layers, spacer medium layer 2 is silicon dioxide in the present embodiment.The thickness range of spacer medium layer 2 is 0.1～3 μ m, in the present embodiment, the thickness of spacer medium layer 2 can but be not limited to 1 μ m.
Step S03: see also Fig. 5, in the subregion of spacer medium layer 2, form groove structure through photoetching, etching.Concrete, spin coating one deck photoresist 3 on spacer medium layer 2 at first, then in photoresist 3, form groove pattern through photoetching, then the groove pattern on the photoresist 3 adopts as template but is not limited to the method etching spacer medium layer 2 of reactive ion etching, in spacer medium layer 2, form groove structure, and remove photoresist.Among the present invention, the degree of depth of groove is 1/4～3/4 of spacer medium layer 2 thickness, and the ratio of the hierarchy structure of groove is 1/2～2.In the present embodiment, the width of each groove is 0.5 μ m, and the degree of depth of groove is 0.5 μ m, and the ratio of hierarchy structure is 1:1.
Step S04: see also Fig. 6, on spacer medium layer 2, through photoetching, etching, form electrode draw-out area 7 on Semiconductor substrate 1 surface; Concrete, spin coating photoresist 4 on spacer medium layer 2 at first, then in photoresist 4, form groove pattern through photoetching, then the groove pattern on the photoresist 4 as template adopt but be not limited to dilute hydrofluoric acid solution by but be not limited to the method etching spacer medium layer 2 of wet etching, thereby in definition electrode draw-out area, P type silicon substrate 1 surface 7, and remove photoresist.In the present embodiment, the thickness of the spacer medium layer 2 removed of institute's etching can but to be not limited to be 0.5 μ m.
Step S05: see also Fig. 7, adopt but be not limited to be the mode of Implantation at P type silicon substrate 1 interior doped N-type impurity, such as phosphorus or arsenic, in the present embodiment, can but be not limited to activate this impurity by annealing, thereby the control junction depth forms N-type doped region 5.Need to prove that the surface of N-type doped region 5 namely is electrode draw-out area 7.
Step S06: see also Fig. 8, adopting but being not limited to is the method depositing metal layers on and the spacer medium layer 2 surface portion zone upper in N-type doped region 5 surfaces (electrode draw-out area 7) respectively of evaporation or sputter, then through photoetching and etching technics definition metal level, through removing photoresist, form extraction electrode 8 on N-type doped region 5 surfaces, and at spacer medium layer 2 surface portion zone formation field plate 6, extraction electrode 8 links to each other with field plate 6.Need to prove that the groove in the spacer medium layer 2 is covered by field plate 6, the material of field plate 6 can but to be not limited to be Ti/Al or Ti/TiN/Al, the thickness of metal level can but be not limited to 3 μ m.
Fig. 9 is the comparison diagram of the semiconductor surface electric field strength of terminal structure of the present invention and terminal structure of the prior art.Wherein, the distribution curve of the surface field intensity of curve 51 expressions terminal structure of the prior art, the distribution curve of the surface field intensity of curve 52 expressions terminal structure of the present invention.As seen from Figure 9, the surface field of terminal structure of the present invention has a plurality of peak values, whole electric field ratio prior art large, thereby can bear higher puncture voltage.
Compare with the terminal structure (as shown in Figure 1) of existing high-voltage semi-conductor device, the terminal structure of high-voltage semi-conductor device of the present invention has mainly utilized the field plate below to improve voltage endurance capability with the spacer medium layer of groove structure.The distance of field plate and Semiconductor substrate has strengthened the coupling between field plate and the substrate because the existence of groove has furthered, improved should the zone electric field strength.Like this, by the spacer medium layer below field plate several groove structures are set, the effect that allows field plate absorb power line is brought into play better, can be so that the electric field strength Integral lifting in the regional extent between two peak value electric fields of original PN junction and field plate external boundary below, thereby the raising puncture voltage, and preparation technology is simple.
Foregoing description only is the description to preferred embodiment of the present invention, is not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure all belong to the protection range of claims.
Claims (10)
1. the terminal structure of a high-voltage semi-conductor device, comprise: the Semiconductor substrate of the first conduction type, be positioned at the doped region of the second conduction type of described Semiconductor substrate, be positioned at the spacer medium layer on the described semiconductor substrate surface subregion, and be positioned at the extraction electrode on described doped region surface and the field plate on the described spacer medium layer surface portion zone, described electrode links to each other with described field plate, it is characterized in that, the spacer medium layer of described field plate below comprises groove structure.
2. the preparation method of the terminal structure of high-voltage semi-conductor device according to claim 1 is characterized in that, described groove is covered by described field plate.
3. the terminal structure of high-voltage semi-conductor device according to claim 1 is characterized in that, the thickness range of described spacer medium layer is 0.1～3 μ m.
4. the terminal structure of high-voltage semi-conductor device according to claim 1 is characterized in that, the degree of depth of described groove is 1/4～3/4 of described spacer medium layer thickness.
5. the terminal structure of high-voltage semi-conductor device according to claim 4 is characterized in that, the ratio of the width of described groove and the degree of depth of described groove is 1/2～2.
6. the preparation method of the terminal structure of a high-voltage semi-conductor device is characterized in that, comprising:
Step S01: the Semiconductor substrate that the first conduction type is provided;
Step S02: form the spacer medium layer at described substrate surface;
Step S03: in the subregion of described spacer medium layer, form groove structure through photoetching, etching;
Step S04: through photoetching, etching, in described substrate surface definition electrode draw-out area;
Step S05: the doped region that in described substrate, forms the second conduction type;
Step S06: form electrode and field plate in surface and the described spacer medium layer surface portion zone of described doped region respectively.
7. the preparation method of the terminal structure of high-voltage semi-conductor device according to claim 6 is characterized in that, described groove is covered by described field plate.
8. the preparation method of the terminal structure of high-voltage semi-conductor device according to claim 6 is characterized in that, the thickness range of described spacer medium layer is 0.1～3 μ m.
9. the preparation method of the terminal structure of high-voltage semi-conductor device according to claim 6 is characterized in that, the degree of depth of described groove is 1/4～3/4 of described spacer medium layer thickness.
10. the preparation method of the terminal structure of high-voltage semi-conductor device according to claim 9 is characterized in that, the ratio of the width of described groove and the degree of depth of described groove is 1/2～2.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367403A (en) * | 2013-08-01 | 2013-10-23 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacturing method thereof |
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| US3767981A (en) * | 1971-06-04 | 1973-10-23 | Signetics Corp | High voltage planar diode structure and method |
| JPS5792862A (en) * | 1980-12-01 | 1982-06-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| CN102119443A (en) * | 2008-08-05 | 2011-07-06 | 住友电气工业株式会社 | Schottky barrier diode and method for manufacturing schottky barrier diode |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3767981A (en) * | 1971-06-04 | 1973-10-23 | Signetics Corp | High voltage planar diode structure and method |
| JPS5792862A (en) * | 1980-12-01 | 1982-06-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| CN102119443A (en) * | 2008-08-05 | 2011-07-06 | 住友电气工业株式会社 | Schottky barrier diode and method for manufacturing schottky barrier diode |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367403A (en) * | 2013-08-01 | 2013-10-23 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacturing method thereof |
| WO2015014324A1 (en) * | 2013-08-01 | 2015-02-05 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN103367403B (en) * | 2013-08-01 | 2019-10-08 | 苏州能讯高能半导体有限公司 | Semiconductor devices and its manufacturing method |
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