CN103022026A - Multichip module and manufacturing method thereof - Google Patents

Multichip module and manufacturing method thereof Download PDF

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Publication number
CN103022026A
CN103022026A CN2011102898330A CN201110289833A CN103022026A CN 103022026 A CN103022026 A CN 103022026A CN 2011102898330 A CN2011102898330 A CN 2011102898330A CN 201110289833 A CN201110289833 A CN 201110289833A CN 103022026 A CN103022026 A CN 103022026A
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China
Prior art keywords
chip
high voltage
voltage device
current
power switch
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CN2011102898330A
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CN103022026B (en
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唐健夫
陈曜洲
潘均宏
蓝鹏儒
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Richtek Technology Corp
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Richtek Technology Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13062Junction field-effect transistor [JFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

The invention provides a multichip module and a manufacturing method thereof. The multichip module comprises a high-voltage element chip, a low-voltage control chip, a single chip base and a plurality of pins, wherein the high-voltage element chip is provided with at least one power switch; the low-voltage control chip is coupled with the high-voltage element chip by a metal guide wire; the single chip base is used for fixing the high-voltage element chip and the low-voltage control chip; and the plurality of pins are coupled with the single chip base through an extending part of the chip base or the metal guide wire.

Description

Multi-chip module and manufacture method thereof
Technical field
The present invention relates to a kind of multi-chip module and manufacture method thereof, refer to especially a kind of multi-chip module and manufacture method thereof that high voltage device chip and low voltage control chip is fixed in the same chip seat.
Background technology
Fig. 1 shows a kind of typical power supply circuit, wherein, low voltage control chip 14 in the multi-chip module 10, back coupling signal FB according to flyback (flyback), and current sense signal CS, power switch in the operate high pressure element chip 12 is to be converted to input voltage vin output voltage V out.
See also Fig. 2 A, show the arrangement of 10 1 kinds of prior aries of multi-chip module.As shown in the figure, multi-chip module 10 comprises high voltage device chip 12 and low voltage control chip 14.Wherein, high voltage device chip 12 is fixed on the special-purpose chip carrier 11; And low voltage control chip 14 is fixed on another special-purpose chip carrier 13.Generally speaking, high voltage device is different from the processing procedure of low voltage component, and the cost of making respectively is manufactured on the same substrate lowly more simultaneously, and therefore creating respectively high voltage device chip 12 and low voltage control chip 14 is very general modes; In addition, if the element that high voltage device is rectilinear, then its substrate surface has current potential, and therefore, high voltage device chip 12 should not be fixed on the same chip seat with low voltage control chip 14 simultaneously, in order to avoid influence each other, even causing short circuit, its embodiment is shown in Fig. 2 A, high voltage device chip 12 is fixed on different chip carrier 11 and 13 from low voltage control chip 14, and it is packaged in the same module.The advantage of this prior art is: integrating high-voltage element chip 12 and low voltage control chip 14 and are avoided the mutual interference effect of chip signal within single encapsulation.
Fig. 2 B shows among Fig. 2 A, the profile of AA tangent line.As shown in the figure, on the chip carrier that separates 11 and the chip carrier 13, respectively fixedly high voltage device chip 12 and low voltage control chip 14, and its chip chamber utilize plain conductor 15 mutually to couple, to transmit signal.The shortcoming of this prior art is: chip is fixed in single exclusive chip carrier, so the area of each chip carrier is little with respect to the arrangement of sharing chip carrier, and thus, the efficient of its heat radiation is relatively relatively poor.In addition; temperature sensor (not shown) in the low voltage control chip 14 can't sensing high voltage device chip 12 (or the sensing accuracy is relatively poor) temperature; to start overheat protector (over temperature protection, OTP) when the excess Temperature.Above-mentioned prior art for example is found in U.S. patent application case No. 2007/0200537.
Fig. 3 A-3C shows the prior art of another kind of multi-chip module 20 arrangements.Compared to aforementioned prior art, this prior art is that high voltage device and low voltage component are integrated in single (monolithic) chip 22.As shown in Figure 3A, chip carrier 21 is fixed thereon one chip 22, thus, chip carrier 21 in aforesaid prior art, the chip carrier 11 and 13 that separates, the area of dissipation of this prior art is larger, has better radiating effect.Fig. 3 B shows respectively the top view of one chip 22 with sketch, as shown in the figure, high voltage device 221 is integrated in the one chip 22 with low voltage component 222.Fig. 3 C shows among Fig. 2 A, the profile of AA tangent line.But the shortcoming of this prior art is that high voltage device need to be made with low voltage component simultaneously on same substrate, its manufacturing cost is higher; In addition, high voltage device and low voltage component produce the interactional noise problem of signal, easily such as the problems such as (crosstalk) of crosstalking on same substrate.
In view of this, the present invention is namely for above-mentioned the deficiencies in the prior art, propose a kind of high voltage device chip and low voltage control chip to be fixed in multi-chip module and the manufacture method thereof of same chip seat, can improve the chip cooling problem, and not need to increase manufacturing cost.
Summary of the invention
One of the object of the invention is to overcome the deficiencies in the prior art and defective, proposes a kind of multi-chip module.
Another purpose of the present invention is, proposes a kind of multi-chip module manufacture method.
For reaching above-mentioned purpose, just wherein a viewpoint is sayed, the invention provides a kind of multi-chip module, comprises: a high voltage device chip, and it has at least one power switch; One low voltage control chip, it couples by plain conductor and this high voltage device chip; The one chip seat is in order to be fixed thereon this high voltage device chip and this low voltage control chip; And a plurality of pins, the extension by this chip carrier or plain conductor and this one chip seat couple.
Therein in a kind of enforcement kenel, wherein this high voltage device chip should comprise: horizontal (lateral) metal oxide semiconductcor field effect transistor (metal oxide semiconductor field effect transistor, MOSFET) power switch; An and horizontal vague and general type starting switch.
Described multi-chip module, wherein this high voltage device chip can more comprise a thermal diode in order to sensing temperature.
Implement in the kenel at another kind, wherein this horizontal vague and general type starting switch should have a horizontal vague and general type MOSFET or a horizontal vague and general type junction field effect transistor (junction field effect transistor, JFET).
Implement in the kenel at another kind, wherein this power switch has one first electric current inflow end, one first control end and one first outflow of bus current end, by the operation of this first control end, control a switching current and flow into this first electric current inflow end, and this first outflow of bus current end flows out certainly; This high voltage device chip more comprises a sampling transistor, and in order to this switching current of taking a sample, it comprises: one second electric current flows into end, is contained in this first electric current and flows into end; One second control end is contained in this first control end; And one second outflow of bus current end, flow out isolatedly with this first outflow of bus current end, and produce a sampling current that has a ratio with this switching current.
With regard to another viewpoint, the present invention also provides a kind of multi-chip module manufacture method, comprises: a high voltage device chip is provided, and it has at least one power switch; By plain conductor this high voltage device chip is coupled to a low voltage control chip; This high voltage device chip and this low voltage control chip are fixed in the one chip seat; And by an extension or the plain conductor of this chip carrier this one chip seat is coupled to a plurality of pins.
Illustrate in detail below by specific embodiment, when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and reaches.
Description of drawings
Figure the 1st shows a kind of typical power supply circuit;
Fig. 2 A-2B shows the arrangement of 10 1 kinds of prior aries of multi-chip module;
Fig. 3 A-3C shows the prior art of another kind of multi-chip module 20 arrangements;
Fig. 4 A-4B shows first embodiment of the invention;
Fig. 5 A-5C shows second embodiment of the invention.
Symbol description among the figure
10,20,30,40 multi-chip modules
11,13,15,21,31 chip carriers
12,16,32,42 high voltage device chips
14,34,44 low voltage control chips
15,35 plain conductors
22 one chips
221 high voltage devices
222 low voltage components
37 pins
39 extensions
CS current sense signal
The Drain drain electrode
Drift Region drift region
FB feedbacks signal
The Gate grid
R resistance
The S1 power switch
The S2 sampling transistor
Source 1, Source 2 source electrodes
The Vin input voltage
The Vout output voltage
Embodiment
See also Fig. 4 A and 4B, show first embodiment of the invention, comprise high voltage device chip 32, low voltage control chip 34, one chip seat 31 and a plurality of pins 37 with at least one power switch in the multi-chip module 30.Shown in Fig. 4 A, it couples low voltage control chip 34 by plain conductor 35 and high voltage device chip 32.And high voltage device chip 32 all is fixed on the one chip seat 31 cutaway view of CC hatching line among Fig. 4 A shown in Fig. 4 B with low voltage control chip 34.In addition, a plurality of pins 37 couple with low voltage control chip 34 by the extension 39 of chip carrier 31 or the high voltage device chip 32 on plain conductor 35 and the one chip seat 31.
For high voltage device chip 32 and low voltage control chip 34 can be fixed on the one chip seat 31, and for to avoid the substrate surface of rectilinear high voltage device as described in the prior art to have different current potentials from the substrate surface of low voltage control chip; The high voltage device chip 32 of present embodiment can but be not limited to comprise: lateral metal oxide semiconductor field-effect transistor (metal oxide semiconductor field effect transistor, MOSFET) power switch; And/or horizontal vague and general type starting switch.Because laterally high voltage device is different from rectilinear high voltage device, the substrate surface of its substrate surface and low voltage control chip has same potential (ground connection), therefore can be fixed on the same chip seat 31.
Wherein, in the high voltage device chip 32, can but be not limited to comprise such as thermal diode (thermal diode), can be in order to sensing temperature, and then high voltage device controlled, further to avoid chip overheating.
In addition, above-mentioned horizontal vague and general type starting switch is for example and without limitation to horizontal vague and general type MOSFET or horizontal vague and general type junction field effect transistor (junction field effect transistor, JFET), and it is in order to operate in the circuit start program.
Fig. 5 A-5C shows second embodiment of the invention.Shown in Fig. 5 A, comprise high voltage device chip 42 and low voltage control chip 44 in the multi-chip module 40.In the present embodiment, high voltage device chip 42 for example comprises power switch S1 and sampling transistor S2, and sampling transistor S2 is in order to the electric current of sense power switch S 1.The electric current of sampling transistor S2 flows into the electric current inflow end that end is coupled to power switch S1.The control end of the control end of sampling transistor S2 and power switch S1 all is coupled to the control pin Gate of low voltage control chip 44.The outflow of bus current end of sampling transistor S2 and an end of resistance R couple, and the other end of resistance R then is coupled to ground.(in the situation of NMOS, it is that grid, outflow of bus current end are source electrode for drain electrode, control end that electric current flows into end; Then be corresponding terminal when PMOS or two-carrier junction transistor, this knows usually that by having in the constructed field the knowledgeable is known.) by this kind sampling mode, can reduce the power loss of sense power switching current, and raising efficiency, the accuracy of taking a sample improved.In addition, please refer to Fig. 5 B, show by sampling transistor S2 sense power switch S 1 electric current, to reach the mechanism of overcurrent protection (over current protection, OCP), can further omit the current sense CS pin of low voltage control chip 44.Shown in Fig. 5 B, sampling transistor S2 source electrode is coupled to a comparator circuit, compare with a set point; and produce overcurrent protection signal OCP, can reach the over current protection protection mechanism, and then omit the current sense CS pin of low voltage control chip 44; with the raising conformability, and reduce manufacturing cost.
Fig. 5 C shows the top view of sampling transistor S2 and power switch S1.Shown in Fig. 5 C, power switch S1 comprises drain D rain, drift region, grid G ate and source S ource1.In the way of reality, can be considered source S ource1 is partitioned into a bit of with the source S ource2 as sampling transistor S2, and drain D rain, the drift region, then share with power switch S1 with grid G ate, that is to say, the drain D rain of power switch S1 (electric current flow into end) and grid G ate (control end) also respectively as or comprise the drain D rain (electric current flows into end) and grid G ate (control end) of sampling transistor S2, and the source S ource2 of sampling transistor S2 (outflow of bus current end) is isolated with the source S ource1 (outflow of bus current end) of power switch S1, but sampling transistor S2 and power switch S1 are integrated into single element, to save the element area and to simplify the element production process.So; can be according to the dimension scale of source S ource2 and source S ource1; with the source S ource2 voltage or the current signal that sense, can derive the switching current of power switch S1, with as current sense signal CS or directly in order to carry out the over current protection protection mechanism.
Below for preferred embodiment the present invention is described, just the above for making those skilled in the art be easy to understand content of the present invention, is not to limit interest field of the present invention only.Under same spirit of the present invention, those skilled in the art can think and various equivalence changes.For example, power switch S1 can be PMOS or nmos pass transistor; Shown in each embodiment circuit, can insert the element that does not affect the signal major significance, such as other switch etc.; For example the input of comparator or error amplifier is positive and negative again can exchange, and only needs the signal processing mode of corresponding correction circuit to get final product; For example multi-chip module of the present invention can be applied to various power supply circuits again, and such as power factor correcting (PFC) circuit, flyback power factor correction circuit or half-bridge circuit etc. is not limited to the flyback circuit shown in each figure.All this kind all can teaching according to the present invention be analogized and gets, and therefore, scope of the present invention should contain above-mentioned and other all equivalences change.

Claims (10)

1. a multi-chip module is characterized in that, comprises:
One high voltage device chip, it has at least one power switch;
One low voltage control chip, it couples by plain conductor and this high voltage device chip;
The one chip seat is in order to be fixed thereon this high voltage device chip and this low voltage control chip; And
A plurality of pins, the extension by this chip carrier or plain conductor and this one chip seat couple.
2. multi-chip module as claimed in claim 1, wherein, this high voltage device chip comprises:
One lateral metal oxide semiconductor field-effect transistor power switch; And
One horizontal vague and general type starting switch.
3. multi-chip module as claimed in claim 2, wherein, this high voltage device chip also comprises a thermal diode in order to sensing temperature.
4. multi-chip module as claimed in claim 2, wherein, this horizontal vague and general type starting switch has a horizontal vague and general type MOSFET or a horizontal vague and general type junction field effect transistor.
5. multi-chip module as claimed in claim 1, wherein, this power switch has one first electric current and flows into end, one first control end and one first outflow of bus current end, operation by this first control end, control a switching current and flow into this first electric current inflow end, and this first outflow of bus current end flows out certainly; This high voltage device chip also comprises a sampling transistor, and in order to this switching current of taking a sample, it comprises:
This first electric current flows into end;
This first control end; And
One second outflow of bus current end flows out isolatedly with this first outflow of bus current end, and produces a sampling current that has a ratio with this switching current, and wherein this sampling transistor and power switch are integrated into single element.
6. a multi-chip module manufacture method is characterized in that, comprises:
One high voltage device chip is provided, and it has at least one power switch;
By plain conductor this high voltage device chip is coupled to a low voltage control chip;
This high voltage device chip and this low voltage control chip are fixed in the one chip seat; And
An extension or plain conductor by this chip carrier are coupled to a plurality of pins with this one chip seat.
7. multi-chip module manufacture method as claimed in claim 6, wherein, this high voltage device chip comprises:
One lateral metal oxide semiconductor field-effect transistor power switch; And
One horizontal vague and general type starting switch.
8. multi-chip module manufacture method as claimed in claim 7, wherein, this high voltage device chip also comprises a thermal diode in order to sensing temperature.
9. multi-chip module manufacture method as claimed in claim 7, wherein, this horizontal vague and general type starting switch has a horizontal vague and general type MOSFET or a horizontal vague and general type junction field effect transistor.
10. multi-chip module manufacture method as claimed in claim 6, wherein, this power switch has one first electric current and flows into end, one first control end and one first outflow of bus current end, operation by this first control end, control a switching current and flow into this first electric current inflow end, and this first outflow of bus current end flows out certainly; This high voltage device chip also comprises a sampling transistor, and in order to this switching current of taking a sample, it comprises:
This first electric current flows into end;
This first control end; And
One second outflow of bus current end flows out isolatedly with this first outflow of bus current end, and produces a sampling current that has a ratio with this switching current, and wherein this sampling transistor and power switch are integrated into single element.
CN201110289833.0A 2011-09-20 2011-09-20 Multi-chip module and manufacture method thereof Active CN103022026B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104332465A (en) * 2014-09-03 2015-02-04 江苏长电科技股份有限公司 3D packaging structure and technological method thereof

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CN101359661A (en) * 2007-07-31 2009-02-04 万国半导体股份有限公司 Multi-die dc-dc boost power converter with efficient packaging
CN101378053A (en) * 2007-08-31 2009-03-04 万国半导体股份有限公司 High-side and low-side nmosfets composite package
CN101594048A (en) * 2009-03-19 2009-12-02 深圳市联德合微电子有限公司 A kind of PWM type buck converter with overcurrent protection function
US20100149837A1 (en) * 2007-05-22 2010-06-17 Panasonic Corporation Switching power supply
CN102184920A (en) * 2009-11-24 2011-09-14 英特赛尔美国股份有限公司 Voltage converter and systems including same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100149837A1 (en) * 2007-05-22 2010-06-17 Panasonic Corporation Switching power supply
CN101359661A (en) * 2007-07-31 2009-02-04 万国半导体股份有限公司 Multi-die dc-dc boost power converter with efficient packaging
CN101378053A (en) * 2007-08-31 2009-03-04 万国半导体股份有限公司 High-side and low-side nmosfets composite package
CN101594048A (en) * 2009-03-19 2009-12-02 深圳市联德合微电子有限公司 A kind of PWM type buck converter with overcurrent protection function
CN102184920A (en) * 2009-11-24 2011-09-14 英特赛尔美国股份有限公司 Voltage converter and systems including same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104332465A (en) * 2014-09-03 2015-02-04 江苏长电科技股份有限公司 3D packaging structure and technological method thereof
CN104332465B (en) * 2014-09-03 2017-05-17 江阴芯智联电子科技有限公司 3D packaging structure and technological method thereof

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