CN103021930B - A kind of metal interconnecting layer lithographic method - Google Patents
A kind of metal interconnecting layer lithographic method Download PDFInfo
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- CN103021930B CN103021930B CN201110284500.9A CN201110284500A CN103021930B CN 103021930 B CN103021930 B CN 103021930B CN 201110284500 A CN201110284500 A CN 201110284500A CN 103021930 B CN103021930 B CN 103021930B
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Abstract
The present invention proposes a kind of the first metal interconnecting layer lithographic method being applied to employing metal hard mask, the method is after main etching forms through hole and groove, first adopt all or part of metal hard mask of hydrogen peroxide solution wet etching, then LRM is carried out, finally clean through hole and flute surfaces respectively with EKC and DHF solution, remove the polymer of etch by-products completely, solve after main etching and LRM, adopting DHF to remove etch by-products easily causes the junction of the TEOS layer below metal hard mask and IMD to occur the problem caved in, avoid because depression destroys the smooth of through-hole surfaces, difficulty is caused to the through-hole surfaces deposit diffusion barriers of subsequent step and copper seed layer.
Description
Technical field
The present invention relates to a kind of semiconductor making method, particularly a kind of metal interconnecting layer lithographic method.
Background technology
At present, semiconductor integrated circuit (IC) manufactures main growing semiconductor device in wafer (wafer) device side of silicon substrate and interconnects.Semiconductor device is produced in device layer, for metal oxide semiconductor field effect tube (MOSFET) device, the primary structure of MOSFET element comprises: active area, source electrode, drain and gate, wherein, described active area is arranged in silicon substrate, and described grid is positioned at active region, forms source electrode and drain electrode after ion implantation is carried out respectively in the active area of described grid both sides, below described grid, there is conducting channel, between described grid and conducting channel, have gate dielectric layer.According to the operation principle of MOSFET element, conducting and the closedown that different voltage realizes MOSFET element must be applied respectively by the source electrode to MOSFET, grid and drain electrode, therefore after the primary structure of MOSFET element completes, tungsten (W) contact (Contact also will be made in device layer, and tungsten plug (plug) CT), the each several part of MOSFET element is electrically connected to each other, completes the device layer technique of MOSFET element.
Device layer at MOSFET element place also will make metal interconnecting layer, by metal interconnecting layer for the Signal transmissions between NOSFET device provides physics to ensure after making on device layer.The making of metal interconnecting layer is called metal interconnected layer process (BEOL).In prior art, BEOL typically refers at the middle etching through hole (via) of inter-metal dielectric (IMD) and groove (trench) and fills metal wherein and forms metal connecting line and metal gasket (metalpad), wherein, IMD is used for metalpad and the electric insulation of metal connecting line in metal interconnecting layer, by metal connecting line, the grid of different MOSFET element, source electrode or drain electrode is connected to same metalpad.
The metal interconnecting layer manufacture craft of prior art first above the tungsten CT or tungsten plug of device layer, deposits liner and IMD successively, liner adopts silicon nitride material, as the etching stop layer of etching through hole, the combination of the multilayer dielectricity of silex glass (PE-FSG) layer that typical IMD is silicon rich silicon dioxide (SRO) layer (being used for avoiding the fluorine ion in metal interconnecting layer down to infiltrate semiconductor device layer), silex glass (HDP-FSG) layer being mixed with fluorine ion, gas ions enhancement mode are mixed with fluorine ion and silicon dioxide composition.
Development IMD along with semiconductor technology is more prone to adopt low-k (low-k) medium, such as: carbon atoms silicon dioxide or black diamond (BlackDiamond, BD).Meanwhile, also generally start to adopt metal hard mask technology in the process of etching through hole and groove.
To be positioned in prior art on tungsten CT and tungsten plug, and directly form with tungsten the metal interconnecting layer be electrically connected and be called the first metal interconnecting layer.Fig. 1 is the first metal interconnecting layer lithographic method flow chart of steps adopting metal hard mask in prior art, adopt the designs simplification generalized section of the first metal interconnecting layer etching of metal hard mask in prior art shown in composition graphs 2 ~ Fig. 6, the concrete steps of the first metal interconnecting layer lithographic method adopting metal hard mask are described in prior art.
Step 1, Fig. 2 are the cross-sectional view of the step 1 of the first metal interconnecting layer lithographic method adopting metal hard mask in prior art, as shown in Figure 2, at tungsten CT200 (or tungsten plug) top deposit liner (liner) layer 201 and the IMD202 successively of wafer device side;
In this step, liner layer 201 is as etching through hole etching stop layer in IMD202, normally silicon nitride or carborundum; IMD202 in the present embodiment is BD.
Step 2, Fig. 3 are the cross-sectional view of the step 2 of the first metal interconnecting layer lithographic method adopting metal hard mask in prior art, as shown in Figure 3, tetraethoxysilane (tetraethylorthosilicate is deposited successively above IMD202, TEOS) after layer and TiN metal level, TiN metal level applies the first photoresist (PR) afterwards photoetching form the first photoengraving pattern, with the first photoengraving pattern for mask etching TiN metal level forms metal hard mask 304, exposed portion TEOS layer 203;
Wherein, the process that photoetching forms the first photoengraving pattern comprises: expose a PR, the step such as development.In this step, the method that etching TiN metal level forms metal hard mask 304 is prior art, repeats no more; The pattern that it should be noted that on metal hard mask 304 is the transmission of the first photoengraving pattern, for defining position and the A/F of groove.TEOS layer 203 is as transition zone between IMD202 and TiN metal level.
In this step, also have the step of stripping first photoengraving pattern after forming metal hard mask 304, specifically, main employing two kinds of methods are peeled off the first photoengraving pattern and are namely removed PR, the first, adopt oxygen (O
2) carry out dry etching, there is chemical reaction in oxygen and PR, PR can be removed; The second, also can adopt wet method ashing method, such as, adopt the mixed solution of sulfuric acid and hydrogen peroxide PR can be removed.
Step 3, Fig. 4 are the cross-sectional view of the step 3 of the first metal interconnecting layer lithographic method adopting metal hard mask in prior art, and as shown in Figure 4, after wafer device side coating the 2nd PR, photoetching forms the second photoengraving pattern 405;
In this step, 2nd PR of coating covers on metal hard mask 304 with on the TEOS layer 203 exposed, on, the process that photoetching forms the second photoengraving pattern 405 comprises: expose the 2nd PR, the step such as development, and the second photoengraving pattern 405 defines position and the A/F of through hole.
Step 4, Fig. 5 are the cross-sectional view of the step 4 of the first metal interconnecting layer lithographic method adopting metal hard mask in prior art, as shown in Figure 5, after main etching IMD202 forms through hole and groove respectively, remove liner layer 201 (LinerRemoval, LRM);
The present embodiment is for Damascus method of first etching through hole (viafirst), the main etching process of the method comprises two steps: the first step etches TEOS layer 203 and IMD202 with the second photoengraving pattern 405 successively for mask, through hole is formed in IMD202, second step etches TEOS layer 203 and IMD202 with metal hard mask 304 successively for mask, groove is formed in IMD202 above through hole, the concrete grammar being formed through hole and groove by main etching in IMD202 is respectively prior art, this repeats no more, it should be noted that, LRM of the prior art is after main etching forms through hole, still with the second photoengraving pattern 405 for mask continue etching Liner layer until open liner layer 201 completely, expose tungsten CT200 (or tungsten plug) surface in semiconductor device layer.After LRM, also have the strip step of the second photoengraving pattern 405, in concrete grammar refer step 2, remove the method for a PR.
Step 5, Fig. 6 are the cross-sectional view of the step 5 of the first metal interconnecting layer lithographic method adopting metal hard mask in prior art, and as shown in Figure 6, hydrofluoric acid containing solution (DHF) 606 wet method removes etch by-products;
Accessory substance in the etching process of above-mentioned steps 4 is polymer (polymer), need to remove in this step, simultaneously in order to not corrode the tungsten surface of exposing below the liner layer 201 opened, avoid the ohmic contact damage between the metal connecting line that formed in tungsten and follow-up through hole, thus causing the resistance between metal interconnecting layer and semiconductor device layer to increase, the wet etching of this step can not adopt hydrogen peroxide (H metal being had to severe corrosive
2o
2) solution, the problem that the method that the DHF solution 606 generally adopted in prior art removes etch by-products is brought is: DHF solution 606 can corrode the interface, junction of TEOS layer 203 and IMD202 on the one hand, on the other hand because the existence of TiN metal level applies tension stress to TEOS layer 203, above two aspect effects all can cause the junction of TEOS layer 203 and IMD202 to occur depression (necking), this depression destroys the smooth of through-hole surfaces, causes difficulty to the through-hole surfaces deposit diffusion barriers of subsequent step and copper seed layer.
Summary of the invention
In view of this, the technical problem that the present invention solves is: adopt in the first metal interconnecting layer lithographic method of metal hard mask, the DHF wet clean step removed after liner layer can cause serious depression, and the existence of this depression causes difficulty to follow-up through-hole surfaces deposit diffusion barriers and copper seed layer.
For solving the problem, technical scheme of the present invention is specifically achieved in that
A kind of metal interconnecting layer lithographic method, be applied to the etching of the first metal interconnecting layer adopting metal hard mask, the wafer with semiconductor device layer is provided, described semiconductor device layer comprises tungsten contact or tungsten plug, it is characterized in that, the method comprises: above the contact of described tungsten or tungsten plug successively after deposited liner layer, inter-metal medium, teos layer and metal level, etch described metal level and form metal hard mask after photoetching;
Described wafer device side photoetching forms the second photoengraving pattern;
With described second photoengraving pattern and described metal hard mask for covering teos layer described in main etching and inter-metal medium, form through hole and groove, with described laying for main etching stop-layer;
Wet etching removes part or all of metal hard mask;
With described teos layer for covering the described laying of etching;
The hydroxydopamines organic solvent of alkalescence and hydrofluoric acid containing solution is through hole and groove described in wet-cleaned respectively.
Described metal level is titanium nitride or boron nitride.
Described wet etching adopts hydrogen peroxide solution.
The time range of described wet etching is 1 to 10 minutes.
Described hydrogen peroxide solution is concentration range is 1% to 50%.
The scavenging period scope of described hydroxydopamines organic solvent is 1 to 20 minutes.
The scavenging period scope of described hydrofluoric acid containing solution is 1 to 20 minutes.
The described deionized water of hydrofluoric acid containing solution and the volume range of hydrofluoric acid are 100: 1 to 1000: 1.
As seen from the above technical solutions, the invention solves after main etching and LRM, adopting DHF to remove etch by-products easily causes the junction of the TEOS layer below metal hard mask and IMD to occur the problem caved in, avoid, because depression destroys the smooth of through-hole surfaces, causing difficulty to the through-hole surfaces deposit diffusion barriers of subsequent step and copper seed layer.
Accompanying drawing explanation
Fig. 1 is the first metal interconnecting layer lithographic method flow chart of steps adopting metal hard mask in prior art;
Fig. 2 ~ 6 are for adopting the cross-sectional view of the first metal interconnecting layer etching of metal hard mask in prior art;
Fig. 7 is the first metal interconnecting layer lithographic method flow chart of steps that the present invention adopts metal hard mask;
Fig. 8 ~ 14 adopt the cross-sectional view of the first metal interconnecting layer etching of metal hard mask for the present invention.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail.
Specific embodiment one
Fig. 7 is the first metal interconnecting layer lithographic method flow chart of steps adopting metal hard mask in prior art, adopt the designs simplification generalized section of the first metal interconnecting layer etching of metal hard mask in prior art shown in composition graphs 8 ~ Figure 14, the concrete steps of the first metal interconnecting layer lithographic method adopting metal hard mask are described in prior art.
Step 701, Fig. 8 are the cross-sectional view of the step 701 of the first metal interconnecting layer lithographic method adopting metal hard mask in the present invention, as shown in Figure 8, at tungsten CT (or tungsten plug) top deposit liner (liner) layer 201 and the IMD202 successively of wafer device side;
In this step, liner layer 201 is as etching through hole etching stop layer in IMD202, normally silicon nitride or carborundum; IMD202 in the present embodiment is BD.
Step 702, Fig. 9 are the cross-sectional view of the step 702 of the first metal interconnecting layer lithographic method adopting metal hard mask in the present invention, as shown in Figure 9, tetraethoxysilane (tetraethylorthosilicate is deposited successively above IMD202, TEOS) after layer 203 and metal level, apply on the metal layer the first photoresist (PR) afterwards photoetching form the first photoengraving pattern, with the first photoengraving pattern for mask etching metal level forms metal hard mask 304, exposed portion TEOS layer 203;
In this step, TEOS layer 203 is as transition zone between IMD202 and TiN metal level.Metal level is the metal material such as titanium nitride (TiN) or boron nitride (BN), require in the process of dry etching through hole and groove, the metal hard mask 304 that metal level is formed relatively TEOS layer 203 and IMD202 has higher etching selection ratio, the present embodiment using TiN as metal level, hereinafter referred to as TiN metal level.The process that photoetching forms the first photoengraving pattern comprises: expose a PR, the step such as development.In this step, the method that etching TiN metal level forms metal hard mask 304 is prior art, repeats no more.The pattern that it should be noted that on metal hard mask 304 is the transmission of the first photoengraving pattern, for defining position and the A/F of groove.
In this step, also have the step of stripping first photoengraving pattern after forming metal hard mask 304, specifically, main employing two kinds of methods are peeled off the first photoengraving pattern and are namely removed PR, the first, adopt oxygen (O
2) carry out dry etching, there is chemical reaction in oxygen and PR, PR can be removed; The second, also can adopt wet method ashing method, such as, adopt the mixed solution of sulfuric acid and hydrogen peroxide PR can be removed.
Step 703, Figure 10 are the cross-sectional view of the step 703 of the first metal interconnecting layer lithographic method adopting metal hard mask in the present invention, and as shown in Figure 10, after wafer device side coating the 2nd PR, photoetching forms the second photoengraving pattern 405;
In this step, 2nd PR of coating covers on metal hard mask 304 with on the TEOS layer 203 exposed, the process that photoetching forms the second photoengraving pattern 405 comprises: expose the 2nd PR, the step such as development, and the second photoengraving pattern 405 defines position and the A/F of through hole.
Step 704, Figure 11 are the cross-sectional view of the step 704 of the first metal interconnecting layer lithographic method adopting metal hard mask in the present invention, as shown in figure 11, main etching TEOS layer 203 and IMD202 form through hole and groove respectively, are main etching stop-layer with liner layer 201;
The present embodiment is for Damascus method of first etching through hole (viafirst), the main etching process of the method comprises two steps: the first step etches TEOS layer 203 and IMD202 with the second photoengraving pattern 405 successively for mask, in IMD202, etching forms through hole, second step etches TEOS layer 203 and IMD202 with metal hard mask 304 successively for mask, and above through hole, etching forms groove; The strip step of the second photoengraving pattern 405 is also had after etching forms through hole; The concrete grammar being formed through hole and groove by main etching in IMD202 is respectively the present invention, and this repeats no more.In the present invention, the etching terminal endpoint detection method of main etching is determined, it should be noted that compared with prior art, after main etching forms through hole and groove, no longer opens liner layer 201.After main etching, also have the second photoengraving pattern 405 strip step that the second photoresist is formed, concrete grammar is see the associated description of step 702.
Step 705, Figure 12 are the cross-sectional view of the step 705 of the first metal interconnecting layer lithographic method adopting metal hard mask in the present invention, and as shown in figure 12, wet etching 1201 removes the hard mask 304 of part metals;
The present embodiment adopts hydrogen peroxide solution to carry out wet etching 1201, and hydrogen peroxide solution is very strong to corrosions of metal such as TiN, and metal hard mask 304 is wholly or partly erosion removal.The concentration range of hydrogen peroxide solution is 1% to 50%, such as 1%, 20% or 50%; The wet etching time range adopting hydrogen peroxide solution is 1 minute to 10 minutes, such as, and 1 minute, 5 minutes or 10 minutes.In this step, except hydrogen peroxide solution, wet etching 1201 can also be carried out with the etchant solution that other can remove metal hard mask 304, reach the object removing metal hard mask 304.Require that etchant solution is very large to the etching selection ratio of metal hard mask 304 and TEOS layer 203, IMD202 and liner layer 201 three, namely while wet etching 1201 removes metal hard mask 304, do not damage three as far as possible.
Step 706, Figure 13 are the cross-sectional view of the step 706 of the first metal interconnecting layer lithographic method adopting metal hard mask in the present invention, and as shown in figure 13, etching removes liner layer 201 (LRM);
In this step, the method of LRM is dry etching, liner layer 201 is etched for covering with residual metal hard mask 304 and TEOS layer 203, adopt endpoint detection method to control the dwell time of etching, open the tungsten surface that liner layer 201 exposes tungsten CT (or tungsten plug) in semiconductor device layer.
Step 707, Figure 14 are the cross-sectional view of the step 707 of the first metal interconnecting layer lithographic method adopting metal hard mask in the present invention, as shown in figure 14, through hole respectively after wet-cleaned 1401LRM of hydroxydopamines organic solvent (EKC) and DHF solution and groove;
In this step, the wet-cleaned order of EKC and DHF solution does not affect the present invention, first can use EKC, also can first use DHF solution.EKC is not fluorine-containing alkaline solution, and for reducing the fluorine element of DHF solution to the corrosiveness at interface, junction between TEOS layer 203 and IMD202, the wet-cleaned time range of EKC is 1 minute to 20 minutes, such as, and 1 minute, 10 minutes or 20 minutes.The volume range of the deionized water of DFH solution and hydrofluoric acid (HF) is 100: 1 to 1000: 1, such as, and 100: 1,500: 1 or 1000: 1; The wet-cleaned time range of DHF solution is 1 minute to 20 minutes, such as, and 1 minute, 10 minutes or 20 minutes.
In fact, the wet-cleaned adopting DHF solution guarantees to remove completely the step that polymer need not lack of etch by-products, EKC and DHF solution can only be adopted respectively to carry out the polymer of wet method removing etch by-products, under the prerequisite of polymer is removed in guarantee completely, reduce concentration and the wet-cleaned time of DHF solution as far as possible, reduce the corrosion to TEOS layer 203 and interface, IMD202 junction.
The present invention proposes a kind of the first metal interconnecting layer lithographic method adopting metal hard mask, the method is after main etching forms through hole and groove, first adopt all or part of metal hard mask 304 of hydrogen peroxide solution wet etching, then LRM is carried out, finally clean through hole and flute surfaces respectively with EKC and DHF solution, remove the polymer of etch by-products completely.The method is not on the one hand while removing liner layer 201 and protecting the tungsten surface of semiconductor device layer, partially or completely remove the metal hard mask 304 above TEOS layer 203, on the other hand because DHF is in the corrosion of TEOS layer 203 edge, reduce the tension stress that metal hard mask 304 pairs of TEOS layers 203 apply, on the other hand, carry out cleaning the content alleviating hydrofluoric acid in DHF solution owing to using EKC, two aspects alleviate the necking phenomenon at the interface, junction of TEOS layer 203 and IMD202 jointly, solve after main etching and LRM, adopting DHF to remove etch by-products easily causes the junction of the TEOS layer 203 below metal hard mask 304 and IMD202 to occur the problem caved in, avoid because depression destroys the smooth of through-hole surfaces, difficulty is caused to the through-hole surfaces deposit diffusion barriers of subsequent step and copper seed layer.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (8)
1. a metal interconnecting layer lithographic method, be applied to the etching of the first metal interconnecting layer adopting metal hard mask, the wafer with semiconductor device layer is provided, described semiconductor device layer comprises tungsten contact or tungsten plug, it is characterized in that, the method comprises: above the contact of described tungsten or tungsten plug successively after deposited liner layer, inter-metal medium, teos layer and metal level, etch described metal level and form metal hard mask after photoetching;
Described wafer device side photoetching forms the second photoengraving pattern;
With described second photoengraving pattern and described metal hard mask for covering teos layer described in main etching and inter-metal medium, form through hole and groove, with described laying for main etching stop-layer;
Wet etching removes part or all of metal hard mask;
With described teos layer for covering the described laying of etching;
The hydroxydopamines organic solvent of alkalescence and hydrofluoric acid containing solution is through hole and groove described in wet-cleaned respectively, to remove the polymer of etch by-products.
2. method according to claim 1, is characterized in that, described metal level is titanium nitride or boron nitride.
3. method according to claim 1, is characterized in that, described wet etching adopts hydrogen peroxide solution.
4. method according to claim 1, is characterized in that, the time range of described wet etching is 1 to 10 minutes.
5. method according to claim 3, is characterized in that, described hydrogen peroxide solution is concentration range is 1% to 50%.
6. method according to claim 1, is characterized in that, the scavenging period scope of described hydroxydopamines organic solvent is 1 to 20 minutes.
7. method according to claim 1, is characterized in that, the scavenging period scope of described hydrofluoric acid containing solution is 1 to 20 minutes.
8. method according to claim 1, is characterized in that, the described deionized water of hydrofluoric acid containing solution and the volume range of hydrofluoric acid are 100:1 to 1000:1.
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| CN104078413B (en) * | 2013-03-27 | 2019-04-02 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of contact hole |
| CN104752333B (en) * | 2013-12-31 | 2018-07-03 | 中芯国际集成电路制造(上海)有限公司 | The production method of first metal interconnecting layer |
| CN104835776B (en) * | 2014-02-08 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | The production method of TSV blind holes |
| CN111029259B (en) * | 2019-11-11 | 2021-07-23 | 中国科学院苏州纳米技术与纳米仿生研究所 | Manufacturing method of circuit substrate |
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| US7378343B2 (en) * | 2005-11-17 | 2008-05-27 | United Microelectronics Corp. | Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content |
| WO2009047588A1 (en) * | 2007-10-09 | 2009-04-16 | Freescale Semiconductor, Inc. | Method for manufacturing a semiconductor device and semiconductor device obtainable with such a method |
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