CN103021450B - Close-coupled Charger transfer refresh circuit and method for refreshing thereof - Google Patents
Close-coupled Charger transfer refresh circuit and method for refreshing thereof Download PDFInfo
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Abstract
The invention belongs to memory technology field, particularly relate to a kind of close-coupled Charger transfer refresh circuit and method of operating thereof.Close-coupled Charger transfer refresh circuit of the present invention, comprise the array that size is M*N, be divided into t M × (N/t) subarray in column direction, each subarray numbering 1 ~ n, the empty power end VHn of the sense amplifier of each subarray is connected, and the empty power end VHn between subarray is connected by charge transfer switch Tn, M, N, n, t are natural number, the empty power end of all sense amplifiers of each subarray is connected, be denoted as VHn, and the empty power end VHn between subarray is connected by charge transfer switch Tn.The present invention both saved refresh power consumption, significantly reduced refresh time again, and control circuit is simple, without the need to extra area overhead.
Description
Technical field
The invention belongs to memory technology field, particularly relate to a kind of close-coupled Charger transfer refresh circuit and method of operating thereof.
Background technology
In recent years, dynamic RAM is widely used in the aspects such as all kinds of such as consumer electronics product, image/video process chip, game machine.Traditionally, DRAM compares the main drawback of SRAM in embedded device application and is: the volatibility of memory cell data causes to be needed to refresh, and this results in extra steering logic expense and data maintenance power dissipation overhead.Keep in power consumption in data, refresh the dynamic power consumption brought and account for 30%, the voltage swing that the reading written-back operation that this part dynamic power consumption mainly comes from unit is brought on bit line.
In order to the data reducing DRAM keep power consumption, traditional scheme is all spatially sub-bit-line or subarray several groups of bit lines or array partition, and an accessed array operation is divided into according to the division of set of bit lines or array the child-operation of successively twice by sequential.See accompanying drawing 1 and accompanying drawing 2, for conventional charge transfer refresh circuit schematic diagram and time sequential routine figure (list of references, Acrossingchargerecyclerefreshschemewithaseparateddrivers ense-amplifierforGbDRAMs, SymposiumonVLSICircuitsDigestofTechnicalPapers, 1995, pp.101-102), a logical line fresh array is divided into subarray A and subarray B, the empty power end of all sense amplifiers of each subarray is connected, be denoted as VHn, and the empty power end between subarray is connected by charge transfer switch T-phase.Like this, the stray capacitance Cp (comprising bit line parasitic capacitance Cb and empty power end stray capacitance Cv, Cp=Cb+Cv) of subarray A/B and charge transfer switch T constitutes basic charge share model.Accompanying drawing 3 refreshes once row refresh operation step exploded view for conventional charge shifts, and wherein stage (1) ~ stage (3) is that subarray A refreshes the stage, and stage (4) ~ stage (7) is that subarray B refreshes the stage.Charger transfer occurs in stage (3) ~ stage (5): when the sense amplifier of subarray A is opened and after unit write back, bit line and empty power end VHA do not reset immediately, but the empty power end VHB of this part electric charge and subarray B is shared (charge transfer switch T opens as shown in fig. 1), power supply as subarray B sense amplifier goes to drive its bit line small-signal part to amplify, thus for the charge consumption of power supply when saving amplification.Subarray capable refreshing (i.e. written-back operation) time is a clock period, and once capable refreshing takies 2 clock period.
Conventional charge transfer refreshes (chargetransferrefresh, CTR) and makes memory refress lower power consumption, but has the following disadvantages:
Charge transfer effciency has much room for improvement;
Once row refresh time can be optimized further;
The time overhead problem of charge transfer effciency problem and accessed array operation.According to charge share model, charge transfer effciency (in the unit interval both sides' stray capacitance exchange charge amount) and charge transfer switch pipe size and to shift both sides' stray capacitance size relevant.Consider in a logical line refresh operation, charge transfer switch pipe opening time section and other operational phase proportion, its unbalanced pulse width obviously has certain restriction, and consider laying out pattern's factor, Charger transfer pipe size is determined, thus the principal element improving charge transfer effciency is the size of stray capacitance, namely how to divide array;
In addition, because an accessed array operation is divided into the sub-accessed array operation repeatedly having precedence, carry out the Charger transfer operation between bit line or array, therefore once visit array handling time is elongated.Consider that a logical line refreshes, as Fig. 1 and 2, in (2) later stage in stage and stage (3), electric charge on the stray capacitance Cp of subarray A is in hold mode, be not transferred, and now subarray B not yet starts refresh operation, therefore become the once redundancy time of row refresh operation during this period of time, correspondingly the data accessibility of storer reduces.
Another kind of traditional Charger transfer method for refreshing (patent publication No. CN1898748A), propose repeatedly to circulate between multiple array again the method for electric charge, but still have the following disadvantages, (1) need between multiple array, set up complicated switching mechanism, the inductive switch controller of corresponding needs complexity, area utilization ratio is not high; (2) loose with the Charger transfer refresh step between the multiple array of a line, row refresh time is long, and the data accessibility of storer is not high.
The present invention, by pair array classifying rationally, improves the efficiency that Charger transfer refreshes; Propose compact refresh scheme simultaneously, shorten once row refresh time, improve the data accessibility of storer.
Summary of the invention
In order to achieve the above object, the present invention proposes a kind of close-coupled Charger transfer refresh circuit, comprises the array that size is M*N, is divided into t M in column direction
×(N/t) subarray, each subarray numbering 1 ~ n, the empty power end VHn of the sense amplifier of each subarray is connected, and the empty power end VHn between subarray is connected by charge transfer switch Tn, M, N, n, t are natural number, the empty power end of all sense amplifiers of each subarray is connected, and be denoted as VHn, and the empty power end VHn between subarray is connected by charge transfer switch Tn.
Preferably, the stray capacitance Cp of every adjacent subarray and charge transfer switch T constitutes basic charge share model.
Preferably, stray capacitance Cp comprises bit line parasitic capacitance Cb and empty power end stray capacitance Cv, wherein Cp=Cb+Cv.
Preferably, each subarray starts refreshing successively every set time Tdelay, their bit line amplify the part after being divided into Charger transfer amplify and sense amplifier enable signal open after full amplitude of oscillation amplification.
Preferably, during each subarray refresh operation, the opening time of sense amplifier when part amplification time and full amplitude of oscillation amplification time sum equal normal running.
Preferably, when entering refresh mode, electric charge on its stray capacitance Cp is transferred to lower an array by each subarray successively, simultaneously in order to accelerate row refresh operation, often organizing in the charge transfer process that adjacent subarray carries out, the electric charge of subarray stray capacitance Cp is not paused be transferred to another subarray.
In order to achieve the above object, the present invention also proposes a kind of close-coupled Charger transfer method for refreshing, is the array of M*N, is divided into t M in column direction by size
×(N/t) subarray, each subarray numbering 1 ~ n, the empty power end VHn of the sense amplifier of each subarray is connected, and the empty power end VHn between subarray is connected by charge transfer switch Tn, M, N, n, t are natural number, when entering refresh mode, electric charge on its stray capacitance Cp is transferred to lower an array by each subarray successively, simultaneously in order to accelerate row refresh operation, often organizing in the charge transfer process that adjacent subarray carries out, the electric charge of subarray stray capacitance Cp is not paused be transferred to another subarray.
Preferably, during each subarray refresh operation, the opening time of sense amplifier when part amplification time and full amplitude of oscillation amplification time sum equal normal running.
Preferably, each subarray starts refreshing successively every set time Tdelay, their bit line amplify the part after being divided into Charger transfer amplify and sense amplifier enable signal open after full amplitude of oscillation amplification.
Preferably, during each subarray refresh operation, the opening time of sense amplifier when part amplification time and full amplitude of oscillation amplification time sum equal normal running.
The invention provides a kind of structure of refreshing for compact Charger transfer and method, between adjacent subarray, transfer refreshes electric charge, and the compact overlap of the refresh step of subarray, both refresh power consumption was saved, significantly reduce refresh time again, and control circuit is simple, without the need to extra area overhead.
Accompanying drawing explanation
Accompanying drawing 1 is conventional charge transfer refresh circuit schematic diagram;
Accompanying drawing 2 is conventional charge transfer refresh operation sequential chart;
Accompanying drawing 3 refreshes once row refresh operation step exploded view for conventional charge shifts;
Accompanying drawing 4 is according to embodiment of the present invention close-coupled Charger transfer refresh circuit schematic diagram;
Accompanying drawing 5 is for refresh once row refresh operation step exploded view according to embodiment of the present invention close-coupled Charger transfer;
Accompanying drawing 6 is according to embodiment of the present invention close-coupled Charger transfer refresh operation schematic diagram;
Accompanying drawing 7 is the comparison of three kinds of refresh schemes;
Accompanying drawing 8 is the simulation result refreshed according to embodiment of the present invention close-coupled Charger transfer;
Accompanying drawing 9 is the control signal sequential chart according to embodiment of the present invention close-coupled Charger transfer refresh operation;
Accompanying drawing 10 is according to the control signal generation circuit of the embodiment of the present invention based on array partition.
Embodiment
Accompanying drawing 4 is according to embodiment of the present invention close-coupled Charger transfer refresh circuit schematic diagram.The array being 128 × 256 size is divided into 4 128 × 64 subarrays (each subarray numbering 1 ~ n) in column direction, the empty power end of all sense amplifiers of each subarray is connected, be denoted as VHn, and the empty power end VHn between subarray is connected by charge transfer switch Tn.Exemplarily, only show subarray A, B, C, D in figure.It should be noted that, here embodiment only exemplify size be 128 × 256 array be divided into 4 128 × 64 subarrays (each subarray numbering 1 ~ n) in column direction, it will be appreciated by those skilled in the art that it is be not limited to this, can be expanded to general array, such as, be that the array of M*N is divided into t M in column direction by size
×(N/t) subarray (each subarray numbering 1 ~ n), the empty power end VHn of the sense amplifier of each subarray is connected, and the empty power end VHn between subarray is connected by charge transfer switch Tn.Preferably, t can choose 4.
Accompanying drawing 5 is for refresh once row refresh operation step exploded view according to embodiment of the present invention close-coupled Charger transfer.In stage (1), enter refresh mode and refresh n-th line, subarray A unit is opened, and sets up bit line small-signal.In stage (2), SAE
aopen, the full amplitude of oscillation of subarray read output signal is amplified, and meanwhile, subarray unit B is opened, and sets up bit line small-signal.In stage (3), subarray A bit line swings, and unit is write back, another side, and T1 opens, and subarray part B is amplified, and meanwhile, subarray C unit is opened, and sets up bit line small-signal.In stage (4), SAE
bopen, the full amplitude of oscillation of subarray read output signal is amplified.In stage (5), subarray B bit line swings, and unit is write back, another side, and T2 opens, and subarray C part is amplified, and meanwhile, subarray D unit is opened, and sets up bit line small-signal.In stage (6), SAE
copen, the full amplitude of oscillation of subarray read output signal is amplified.In stage (7), subarray C bit line swings, and unit is write back, another side, and T3 opens, and subarray D part is amplified.In stage (8), SAE
dopen, the full amplitude of oscillation of subarray read output signal is amplified.In stage (9), subarray D bit line swings, and unit is write back.Then refresh the (n+1)th row, get back to the stage (1).It can thus be appreciated that, when storer enters refresh mode, electric charge on its stray capacitance Cpn is transferred to lower an array by each subarray successively, simultaneously in order to accelerate row refresh operation, often organizing in the charge transfer process that adjacent subarray carries out, stage (4) ~ (7) in traditional scheme are advanced to the moment between stage (2) ~ (3) carry out, the electric charge of subarray stray capacitance Cpn is not paused be transferred to another subarray.
As shown in Figure 6, accompanying drawing 6 is according to embodiment of the present invention close-coupled Charger transfer refresh operation schematic diagram.Wherein each subarray starts refreshing successively every set time Tdelay (1ns), their bit line amplify the part after being divided into Charger transfer amplify (as stage (3), (5), (7)) and sense amplifier enable signal SAEn open after full amplitude of oscillation amplification (as stage (4), (6), (8)); Simultaneously during each subarray refresh operation, when part amplification time and full amplitude of oscillation amplification time sum equal normal running, the opening time of sense amplifier, this ensure that subarray refresh operation time is consistent with the normal working time.In once row refresh operation, each subarray once row refresh operation time is a clock period, and 4 sub-array row refresh operations form accurate parallel work-flow, account for 2 clock period.
Accompanying drawing 7 is the comparison of three kinds of refresh schemes.Wherein, array size is 128 × 256, and subarray (128 × 64) once row refresh time is a clock period 3ns.Employing conventional refresh scheme once row refresh time is about its 3.5 times, and employing conventional charge transfer refresh scheme once row refresh time is its 2 times, and employing close-coupled Charger transfer refresh scheme once row refresh time is its 2 times.Can find out, the refresh time proposed a plan is consistent with scheme 2, compares scheme 1 and reduces 43%, and sense amplifier power consumption is compared the above two and reduced 31.6% and 58.4% respectively.
Accompanying drawing 8 is the simulation result refreshed according to embodiment of the present invention close-coupled Charger transfer.Clock period Tclk is 3ns.Subarray A ~ D starts refresh operation successively every 1ns, charge transfer switch T1 ~ T3 opens successively every 1ns after refresh mode starts 2.4ns, corresponding to the stage (3) in Fig. 5, (5), (7), within 600ps effective time, bit line signal is amplified RBLn/BRBLn part.Subarray sense amplifier enable signal SAEB/SAEC/SAED opens successively every 1ns after refresh mode starts 3ns, corresponding to the stage (4) in Fig. 5, (6), (8), within 400ps effective time, bit line signal is amplified the full amplitude of oscillation of RBLn/BRBLn.The empty power end VHA ~ VHD of subarray in stage (3), (5), (7) complete electric charge and share, complete drive the full amplitude of oscillation of sense amplifier to amplify in stage (4), (6), (8).R/w cell completes in stage (3), (5), (7), (9).Each subarray refresh time is a clock period, and once row refresh time is two clock period 6ns.
Accompanying drawing 9 is the control signal sequential chart according to embodiment of the present invention close-coupled Charger transfer refresh operation.When entering Charger transfer refresh mode, effectively, with refreshing relevant intermediate control signal REN_REF is effective for internal refresh enable signal iRREQ.Make logic by signal iRREQ, REN_REF and normal mode of operation signal SIGNAL, produce the Special controlling signal under close-coupled Charger transfer refresh mode.
Accompanying drawing 10 is according to the control signal generation circuit of the embodiment of the present invention based on array partition.By the control signal bunch SIGNAL produced in sheet, four tunnels are divided into through subarray chip selection signal BSEL, the three road time delayed signals produced with REN_REF make logic, the final control signal bunch SIGNAL<n> generating each subarray.Wherein, after entering close-coupled Charger transfer refresh mode, chip selection signal BSEL becomes low level, makes Sheffer stroke gate invalid, exports the three road time delayed signals that control signal bunch SIGNAL<n> depends on REN_REF generation.The signal of the three tunnel pulsewidth DL2 now produced by REN_REF, mutual time delay DL1 and the SIGANL signal by the generation of iRREQ mono-tunnel, become final output control signal bunch SIGNAL<n>.
Although illustrate and describe the preferred embodiments of the present invention, it will be apparent for a person skilled in the art that and can make a lot of change and amendment without departing from the invention in it is wider.The present invention is applicable to the dynamic RAM adopting any unit; Be applicable to adopt any one refresh scheme (distributed refresh, lump type refreshing etc.).
Claims (8)
1. a close-coupled Charger transfer refresh circuit, comprise the array that size is M*N, be divided into t M × (N/t) subarray in column direction, each subarray numbering 1 ~ n, the empty power end VHn of the sense amplifier of each subarray is connected, and the empty power end VHn between subarray is connected by charge transfer switch Tn, M, N, n, t are natural number, it is characterized in that:
The empty power end of all sense amplifiers of each subarray is connected, and be denoted as VHn, and the empty power end VHn between subarray is connected by charge transfer switch Tn;
Each subarray starts refreshing successively every set time Tdelay, their bit line amplify the part after being divided into Charger transfer amplify and sense amplifier enable signal open after full amplitude of oscillation amplification.
2. close-coupled Charger transfer refresh circuit according to claim 1, is characterized in that: the stray capacitance Cp of every adjacent subarray and charge transfer switch Tn constitutes basic charge share model.
3. close-coupled Charger transfer refresh circuit according to claim 2, is characterized in that: stray capacitance Cp comprises bit line parasitic capacitance Cb and empty power end stray capacitance Cv, wherein Cp=Cb+Cv.
4. close-coupled Charger transfer refresh circuit according to claim 1, is characterized in that: during each subarray refresh operation, the opening time of sense amplifier when part amplification time and full amplitude of oscillation amplification time sum equal normal running.
5. close-coupled Charger transfer refresh circuit according to claim 3, it is characterized in that: when entering refresh mode, electric charge on its stray capacitance Cp is transferred to lower an array by each subarray successively, simultaneously in order to accelerate row refresh operation, often organizing in the charge transfer process that adjacent subarray carries out, the electric charge of subarray stray capacitance Cp is not paused be transferred to another subarray.
6. a close-coupled Charger transfer method for refreshing, be the array of M*N by size, be divided into t M × (N/t) subarray in column direction, each subarray numbering 1 ~ n, the empty power end VHn of the sense amplifier of each subarray is connected, and the empty power end VHn between subarray is connected by charge transfer switch Tn, M, N, n, t are natural number, it is characterized in that:
When entering refresh mode, electric charge on its stray capacitance Cp is transferred to lower an array by each subarray successively, simultaneously in order to accelerate row refresh operation, often organizing in the charge transfer process that adjacent subarray carries out, the electric charge of subarray stray capacitance Cp is not paused be transferred to another subarray;
During each subarray refresh operation, the opening time of sense amplifier when part amplification time and full amplitude of oscillation amplification time sum equal normal running.
7. a kind of close-coupled Charger transfer method for refreshing according to claim 6, it is characterized in that: each subarray starts refreshing successively every set time Tdelay, their bit line amplify the part after being divided into Charger transfer amplify and sense amplifier enable signal open after full amplitude of oscillation amplification.
8. a kind of close-coupled Charger transfer method for refreshing according to claim 7, is characterized in that: during each subarray refresh operation, the opening time of sense amplifier when part amplification time and full amplitude of oscillation amplification time sum equal normal running.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0203718A2 (en) * | 1985-05-28 | 1986-12-03 | Nortel Networks Corporation | Dynamic MOS memory reference voltage generator |
| US4653030A (en) * | 1984-08-31 | 1987-03-24 | Texas Instruments Incorporated | Self refresh circuitry for dynamic memory |
| CN1898748A (en) * | 2003-10-23 | 2007-01-17 | 英飞凌科技股份公司 | Method and circuit configuration for multiple charge recycling during refresh operations in a dram device |
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- 2011-09-22 CN CN201110285030.8A patent/CN103021450B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4653030A (en) * | 1984-08-31 | 1987-03-24 | Texas Instruments Incorporated | Self refresh circuitry for dynamic memory |
| US4653030B1 (en) * | 1984-08-31 | 1997-08-26 | Texas Instruments Inc | Self refresh circuitry for dynamic memory |
| EP0203718A2 (en) * | 1985-05-28 | 1986-12-03 | Nortel Networks Corporation | Dynamic MOS memory reference voltage generator |
| CN1898748A (en) * | 2003-10-23 | 2007-01-17 | 英飞凌科技股份公司 | Method and circuit configuration for multiple charge recycling during refresh operations in a dram device |
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