CN100517501C - Complementary dynamic storage unit - Google Patents
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- CN100517501C CN100517501C CNB2006100079733A CN200610007973A CN100517501C CN 100517501 C CN100517501 C CN 100517501C CN B2006100079733 A CNB2006100079733 A CN B2006100079733A CN 200610007973 A CN200610007973 A CN 200610007973A CN 100517501 C CN100517501 C CN 100517501C
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Abstract
The invention discloses a complementary dynamic memory cell whose random access cycle is less than 1/8 of that of a traditional structure, comprising: a memory cell and a complementary memory cell; a word line connecting with the control grids of the memory cell and the complementary memory cell cells; a bit line connecting with the drain of the memory cell; and a complementary bit line connecting with the drain of the complementary memory cell, where the differential voltage caused by the charges stored in the memory cell and the complementary memory cell is transmitted to a sensitivity amplifier through the bit line and the complementary bit line.
Description
Technical field
The present invention relates to a kind of semiconductor storage unit, particularly a kind of complementary dynamic storage unit.
Background technology
In general, dynamic storage unit is kept in information by electric capacity (1T-1C).Any leakage mechanisms, electric charge must be replenished before canned data is lost.For example, a bit is stored in a unit, uses " 0 ", " 1 " expression respectively.Voltage difference between logical one and " 0 " can not be too little, and the one, suppress all possible noise, the 2nd, sense amplifier can correctly be discerned.For other storeies, as static memory cell, do not have dynamic charge to leak, but cost is a memory cell area become big (6-T, 4-T).Under same process conditions, to compare with static memory, dynamic storage has been saved the area of octuple.The shortcoming of traditional dynamic storage unit is that access speed is very slow.In to the very high application of storage capacity requirement, highdensity DRAM unit has exchanged the reduction of cost of bit for any sacrifice in performance.In general, the typical access cycle of dynamic storage is 45-60ns, and under the same process conditions typical access cycle of static memory be 2-5ns.In many high-speed applications, dynamic storage is very limited.
Past, to the research of dynamic storage high-speed applications owing to various reason achievements are little.For example, these DRAM devices and their rival compare the requirement that still can not satisfy high-speed applications.FC-RAM (fast clock storer) and RL-RAM (hanging down sluggish storer) have realized high-speed functions, by the cycle is dropped to 20ns from 45ns, and bandwidth are brought up to Gbit/s, but that cost is a lag time is elongated.In addition, above measure can not all reach needed bandwidth to storage operation at random, and application at a high speed often needs the random read-write to the address.
To the pattern of another optimization, sram cache (cache) at a high speed is linked between DRAM array and the processor, can improve average access time and bandwidth like this.But can the real access time depend on buffer memory and hit, and the hit rate of buffer memory has determined real bandwidth and handling capacity.
Therefore, will be very tempting if a kind of storer of the DRAM unit that is dominant based on area can satisfy the demand of high-speed applications.
Summary of the invention
The purpose of this invention is to provide a kind of complementary dynamic storage unit, the random access time of this unit is lower than 1/8th of traditional structure.
The invention provides a kind of complementary dynamic storage unit for this reason, it comprises: a storage unit (A) and a complementary storage unit (B), wherein, described storage unit (A) and complementary storage unit (B) comprise respectively: a control metal-oxide-semiconductor and store M OS pipe;
The drain electrode of described control metal-oxide-semiconductor connect described bit line (BL, BL_B), the grid of described control metal-oxide-semiconductor connects described word line (WL);
The grid of described store M OS pipe connects negative voltage, and the drain electrode of described store M OS pipe or source electrode connect the source electrode of described control metal-oxide-semiconductor, forms memory capacitance thus;
Wherein, by the current potential on bit line (BL) and the paratope line (BL_B) respectively with storage unit (A) and complementary storage unit (B) on current potential generation electric charge share, make between storage unit (A) and the complementary storage unit (B) and produce differential voltage.One inventor finds that the retention time of complementation unit is 50 times of single unit.In other words, so just may under identical situation of retention time, be reduced the access time.Typical dynamic storage random access time is divided into five parts: electric charge is shared, the sensitive amplification, and data transmit, and cell value recovers, electric charge preliminary filling/balance.According to the conventional method, needing to produce a reference voltage provides sensitive differential level of amplifying, and differential level is amplified to full logic level.In general the structure that produces so reliable and stable datum is very complicated.And in the time of read-write DRAM unit, this reference voltage produces part inevitably can bring the system skew and the noise at zero point., realizes the difference information of voltage that reference voltage level must be between power supply and ground and near half of supply voltage because sharing by electric charge.This can cause the current decay between bit line and the memory node, so electric charge is shared and must be finished in the phase one.Xtor (transmission gate) has limited the electric current of amplification stage.In order to guarantee normally finishing of next accessing operation, because the restriction of transmission gate, this process may be very long.
Complementary dynamic storage cell (CDcell) structure has been improved above-mentioned time-constrain to a great extent.At first, differential voltage is produced by the storage unit of complementation, and reference voltage can be an any level.Reference voltage is chosen as supply voltage or ground level can makes electric current increase 4 times, differential voltage is increased to original 2 times.The speed shared of electric charge has promoted 8 times like this, and since the structure that shortens bit line length and many groupings (bank) further performance boost 4 times.Always have 32 times performance boost in the electric charge stage of sharing like this.
Secondly, the structure of many groupings has been accelerated the speed of data transmission and electric charge preliminary filling/balance, and has strengthened the intensity of sense amplifier, and this is irrelevant with storage unit.Though this will cause the area of unnecessary logic and extra amplifier, the benefit that these costs and the memory cell structure of complementation are better than traditional SRAM structure is compared and is much smaller.
At last, sensitive amplification and unit information rewrite and depend on the performance of sense amplifier to a great extent, but are subject to the electric current by transfer tube and diffusion resistance more.By adopting complementary structure, the information of storage unit is not decided by final level value, but is decided by the level difference of two complementation units.In the single memory cell structure, the NMOS pipe passes " 1 " and PMOS pipe biography " 0 " has the threshold value loss, so sequential is restricted.But complementary storage unit is not like this, and the level of difference is to be determined by the fastest transmission level, passes through NMOS such as " 1 " by PMOS or " 0 ".According to the square law of metal-oxide-semiconductor electric current, make speed be able to 4 times lifting like this.Because aforesaid reference voltage and long data retention time more, complementary storage unit is the octuple of single unit speed.
In many packet memory array structure, the complementation unit dynamic storage has been saved the work power consumption.Power consumption in the digital display circuit is relevant with electric capacity, organizes structure more bit line is shortened, thereby electric capacity is reduced, and power consumption reduces.The quiescent dissipation of dynamic storage has also reduced because refreshing the reduction of power consumption like this.
In a word, approximately fast 10 times of the store access cycles of complementation unit storer than conventional dynamic storage, power consumption is lower, has therefore reached the performance that is similar to static memory.
The present invention is described in detail below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 (a) is a complementary dynamic storage unit schematic diagram of the present invention;
Fig. 1 (b) is the instantiation of complementary dynamic storage unit of the present invention;
Fig. 2 shown use complementary dynamic storage unit of the present invention open the bit line structure memory array cell;
Fig. 3 has shown the folded bit line structure memory array cell of using complementary dynamic storage unit of the present invention;
Fig. 4 (a) is the refresh time of common dynamic cell structure and the Gaussian distribution figure of inefficacy figure place;
Fig. 4 (b) has shown the comparison to the Gaussian distribution figure of the refresh time of structure and inefficacy figure place of complementary dynamic cell among common dynamic cell structure and the present invention;
Fig. 5 (a), Fig. 5 (b) and Fig. 5 (c) of the present inventionly have the storer reading and writing of memory cell and refresh waveform.
Embodiment
In general, shown in Fig. 1 (a) and Fig. 1 (b), complementary dynamic storage unit of the present invention is made up of the dynamic storage cell of a pair of generation differential voltage, and one of them storage unit B is the complementary storage unit of another storage unit A.The differential voltage that wherein said two storage unit A and B are produced sends sense amplifier to by corresponding bit line BL and BL_B respectively.
Further specify the structure and the course of work of complementary dynamic storage unit of the present invention below in conjunction with accompanying drawing.
Fig. 1 (a) has shown the principle of complementary dynamic storage unit of the present invention.Can see that from Fig. 1 (a) complementary dynamic storage unit of the present invention comprises at least:
A storage unit A (left figure) and a complementary storage unit B (right figure);
The word line WL that connects the control grid of described storage unit and described complementary storage unit;
The bit line BL that connects the drain electrode of described storage unit; The paratope line BL_B that connects the drain electrode of described complementary storage unit; Wherein, by the current potential on bit line (BL) and the paratope line (BL_B) respectively with storage unit (A) and complementary storage unit (B) on current potential generation electric charge share, make between storage unit (A) and the complementary storage unit (B) and produce differential voltage.
When the storage unit A canned data was high level, complementary storage unit B canned data was a low level, and vice versa.
Described storage unit A and described complementary storage unit B are respectively single metal-oxide-semiconductor, and its information is stored in the stray capacitance of source electrode of described metal-oxide-semiconductor.
Described this differential voltage sends sense amplifier to by bit line BL and paratope line BL_B.
Described electric charge is shared and is meant, when the oxide-semiconductor control transistors T1 of storage unit A among Fig. 1 (a) and complementary storage unit B and T2 (following also be referred to as " turn-on transistor ") conducting, current potential on bit line BL and the paratope line BL_B and the current potential generation electric charge on memory node SN and the SN are shared.For example during the electronegative potential on reading memory node SN,, then share, make the current potential on the bit line BL_B reduce (realization read operation) by electric charge if the pre-charging potential on the bit line BL_B is high; Equally in write operation, if memory node SN goes up current potential when low, apply (promptly connecting) write data that current potential is high by giving bit line BL, then share by electric charge, make current potential on the memory node SN raise (realization write operation).In a word, when the generation electric charge was shared, the current potential that participates in the shared object of electric charge reached unanimity.
Fig. 1 (b) has shown the instantiation of complementary dynamic storage unit of the present invention, wherein PMOS transistor M3 and M4 form the memory capacitance of storage unit, its grid connects the pole plate that negative voltage VN forms electric capacity, and this PMOS transistor M3 and M4 are equivalent to the memory capacitance among Fig. 1 (a).
Below with reference to Fig. 1 (a) course of work of the present invention is described.
Read operation: establish original state SN for high, then SN is low, and bit line BL, BL_B be height, when word line WL level during by high step-down, and T1, T2 conducting.SN, BL current potential are identical, and bit line BL voltage does not change; BL_B and SN electric charge are shared, and the BL_B current potential descends, by high step-down.BL, BL_B form voltage difference, are connected on this variation of sense amplifier meeting perception on the bit line, read " 1 ", " 0 ".
Write operation: establish original state SN for high, SN is low, writes data and makes that SN is low, and SN is high.When write state begins, bit line BL dragged down for " 0 ", BL_B for high, when word line level during by high step-down, T1, T2 conducting.SN, BL electric charge are shared, and the SN current potential descends, by high step-down; BL_B and SN electric charge are shared, and SN is written into high level.
The cellular construction of complementation of the present invention is that dynamic cell is right, and the data of each storage unit are complementary.For example, unit A stores " 0 ", and unit B must be stored " 1 ", and vice versa.
| Cell A | 0 | 1 | 1 | 0 |
| |
1 | 0 | 1 | 0 |
| Valid | Valid | Invalid | Invalid |
Can notice that it is invalid that two kinds of possible data storage situations are arranged, as, 1-1 or 0-0.In both cases, data can be stored arbitrarily, and guarantee that when resetting storage unit is in correct status.One of advantage of complementation unit be exactly unit information be mutually redundant.In fact semiconductor material such as silicon have many defect sturctures, as point defect etc.These defectives make the work difference of each device.The retention time of dynamic storage unit is subjected to the influence of leakage current, and the distribution of leakage current is different because the position on chip is different.This distribution is a Gaussian distribution.This just means the local unit influence overall situation.For example, the average retention time of whole storer is 1s, and some unit are 30ms to the retention time.The complementation unit of physically separated redundancy makes leakage current obtain equilibrium because of the different influence in position.This system that makes can allow littler design margin, therefore power consumption, speed, cost everyway is got a promotion.
Obviously, can utilize complementary dynamic storage unit of the present invention to make up a kind of high-speed memory.
Fig. 2 shown use above-mentioned complementary dynamic storage unit of the present invention open the bit line structure memory array cell.Fig. 3 has shown the folded bit line structure memory array cell of using above-mentioned complementary dynamic storage unit of the present invention.Wherein, symmetrical circular is represented storage unit A of the present invention and complementary storage unit B respectively among Fig. 2 and Fig. 3.
As Fig. 2, shown in Figure 3, in memory array, the gating of decoding scheme control WL; The turn-on transistor conducting of the WL control store unit of gating realizes that BL/BLB and charge storing unit are shared, forms voltage difference between BL and the BL_B thus; SA amplifies the read-write capability of the voltage difference realization storage unit between BL and BL_B.
Fig. 4 (a) has shown the refresh time of common dynamic cell structure and the Gaussian distribution figure of inefficacy figure place.
Fig. 4 (b) has shown the comparison to the Gaussian distribution figure of the refresh time of structure and inefficacy figure place of complementary dynamic cell among common dynamic cell structure and the present invention; In the drawings, curve (1) is the refresh time of common dynamic cell structure and the Gaussian distribution figure of inefficacy figure place, curve (2) be among the present invention complementary dynamic cell to the refresh time of structure and the Gaussian distribution figure of inefficacy figure place.As can be seen from the figure, compare with common dynamic cell structure, utilize complementary dynamic cell of the present invention to structure, make the refresh cycle elongated, power consumption reduces.
Fig. 5 (a), Fig. 5 (b) and Fig. 5 (c) have shown the storer reading and writing with memory cell of the present invention respectively and have refreshed waveform.Wherein,
WL memory cell conducts transistor gate control signal;
BL/BLB connects the bit line signal of storage unit;
The memory node signal of SN/SNb storage unit;
Eq is at the precharge control signal of BL/BL_B;
Sa sense amplifier control signal;
The output control signal of cas BL/BLB;
The wen write control signal.
Below in conjunction with Fig. 5 (a), Fig. 5 (b) and Fig. 5 (c) storer reading and writing of the present invention, refresh process are described respectively.
The read procedure of storer of the present invention: when signal eq from low to high, WL from high to low, the memory cell conducts transistor turns, electric charge takes place for BL/BL_B and SN/SNb (being the SN among Fig. 1) shares, and makes BL/BL_B produce voltage difference; By applying (promptly connecting) signal sa, make sense amplifier amplify the voltage difference of BL/BLB; By applying (promptly connecting) signal cas, transmit the output terminal of the value of BL/BLB to storer, thus sense data; Look-at-me cas then, signal sa, the supply of signal WL, and make signal eq from high to low, BL/BLB is pre-charged to VDD.
The process of writing of storer of the present invention: when signal eq from low to high, WL is from high to low the time, the memory cell conducts transistor turns, electric charge takes place for BL/BL_B and SN/SNb shares, and produces the voltage difference of BL/BL_B; Apply (promptly connecting) signal sa, make sense amplifier amplify the voltage difference of BL/BL_B; Apply (promptly connecting) signal wen, write data to the input end of storer; Apply (promptly connecting) signal cas, write data and be sent to BL/BL_B, be sent to SN/SNb simultaneously, realize that data write; After data write, the supply of look-at-me cas, wen, sa, WL made signal eq from high to low, and BL/BLB is pre-charged to VDD.
The refresh process of memory cell of the present invention: when signal eq from low to high, WL is from high to low the time, the memory cell conducts transistor turns, electric charge takes place for BL/BL_B and SN/SNb shares, and produces the voltage difference of BL/BL_B; Apply (promptly connecting) signal sa, the voltage difference that makes sense amplifier amplify BL/BLB is with the memory node SN/SNb of data write storage unit again; After Refresh Data was finished, the supply of look-at-me sa, WL made signal eq from high to low, and BL/BLB is pre-charged to VDD.
By above-mentioned analysis, those of ordinary skill in the art can realize the read operation with storer of complementary dynamic storage unit of the present invention by method, wherein said complementary dynamic storage unit is made up of a storage unit A and a complementary storage unit B, said method comprising the steps of:
Apply the control signal that makes its conducting by word line to the turn-on transistor grid of storage unit A and complementary storage unit B, make the turn-on transistor conducting respectively of storage unit A and complementary storage unit B;
Then, share, between bit line BL and paratope line BL_B, produce voltage difference by the memory node SN of bit line BL and paratope line BL_B and storage unit A and the memory node SN generation electric charge of complementary storage unit B;
Amplify described voltage difference by sense amplifier;
Magnitude of voltage through the bit line BL/ paratope line BL_B that amplifies is transferred to the output terminal of storer, thus sense data.
Wherein, the conducting of the turn-on transistor of described storage unit A and complementary storage unit B is to take place from low to high the time at the precharge control signal eq of bit line/paratope line.
Wherein, by applying (promptly connecting) sense amplifier control signal sa, make sense amplifier amplify described voltage difference.
Wherein, by applying the output control signal cas of (promptly connecting) signal bit line BL and paratope line BL_B, the potential value of the bit line BL/ paratope line BLB through amplifying is transferred to the output terminal of storer.
Wherein, after sense data, by interrupting the supply of described bit line/paratope line output control signal cas, described sense amplifier control signal sa, described grid control signal, and make bit line BL and paratope line BL_B precharge control signal eq by hypermutation to low, bit line BL and paratope line BL_B are pre-charged to VDD.
By above-mentioned analysis, those of ordinary skill in the art can realize by the following method that the present invention has the write operation of the storer of complementary dynamic storage unit, described complementary dynamic storage unit is made up of a storage unit A and a complementary storage unit B, said method comprising the steps of:
Data be will write and bit line BL and paratope line BL_B will be sent to;
Apply the control signal that makes its conducting by word line to the turn-on transistor grid of storage unit A and complementary storage unit B, make the turn-on transistor conducting respectively of storage unit A and complementary storage unit B;
Then, share by the memory node SN of bit line BL and paratope line BL_B and storage unit A and the memory node SN generation electric charge of complementary storage unit B, send the data that write that are sent on bit line BL and the paratope line BL_B to the memory node SN of storage unit A and the memory node SN of complementary storage unit B, realize that thus data write.
Wherein, writing before data are sent to bit line BL and paratope line BL_B,, the input end that data are sent to storer will be write by applying (promptly connecting) write control signal wen.
Wherein, after data write, bit line BL and paratope line BL_B are pre-charged to VDD.
By above-mentioned analysis, those of ordinary skill in the art can realize the refresh operation with storer of complementary dynamic storage unit of the present invention by the following method, described complementary dynamic storage unit is made up of a storage unit A and a complementary storage unit B, said method comprising the steps of:
Apply the control signal that makes its conducting by word line to the turn-on transistor grid of storage unit A and complementary storage unit B, make the turn-on transistor conducting respectively of storage unit A and complementary storage unit B;
Then, share, between bit line BL and paratope line BL_B, produce voltage difference by the memory node SN of bit line BL and paratope line BL_B and storage unit A and the memory node SN generation electric charge of complementary storage unit B;
Amplify described voltage difference by sense amplifier, utilize then through the voltage difference of amplification and by electric charge shared memory node SN and SN, thereby realize refreshing data write storage unit again.
After refreshing, BL_B is pre-charged to VDD with bit line BL/ paratope line.
Claims (4)
1. complementary dynamic storage unit, it is characterized in that: it comprises: a storage unit (A) and a complementary storage unit (B), wherein, described storage unit (A) and complementary storage unit (B) comprise respectively: a control metal-oxide-semiconductor and store M OS pipe;
The drain electrode of described control metal-oxide-semiconductor connect described bit line (BL, BL_B), the grid of described control metal-oxide-semiconductor connects described word line (WL);
The grid of described store M OS pipe connects negative voltage, and the drain electrode of described store M OS pipe or source electrode connect the source electrode of described control metal-oxide-semiconductor, forms memory capacitance thus;
Wherein, by the current potential on bit line (BL) and the paratope line (BL_B) respectively with storage unit (A) and complementary storage unit (B) on current potential generation electric charge share, make between storage unit (A) and the complementary storage unit (B) and produce differential voltage.
2. complementary dynamic storage unit according to claim 1 is characterized in that: when storage unit (A) canned data was high level, complementary storage unit (B) canned data was a low level, and vice versa.
3. complementary dynamic storage unit according to claim 1 is characterized in that: described differential voltage sends sense amplifier to by bit line and paratope line.
4. complementary dynamic storage unit according to claim 1 is characterized in that: described oxide-semiconductor control transistors and described store M OS pipe are the PMOS pipes.
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| ITTO20120682A1 (en) * | 2012-07-31 | 2014-02-01 | St Microelectronics Pvt Ltd | NON-VOLATILE MEMORY DEVICE WITH GROUPED CELLS |
| CN103680631A (en) * | 2013-12-25 | 2014-03-26 | 苏州宽温电子科技有限公司 | Improved differential framework XPM memory unit |
| CN103745748A (en) * | 2013-12-25 | 2014-04-23 | 苏州宽温电子科技有限公司 | Improved differential-architecture SONOS flash storage unit |
| CN104008776A (en) * | 2014-06-19 | 2014-08-27 | 苏州宽温电子科技有限公司 | Improved active region read-only memory cell |
| CN105448343B (en) * | 2014-08-29 | 2019-09-27 | 展讯通信（上海）有限公司 | A kind of read-only memory unit and read-only memory |
| US9589636B1 (en) * | 2015-09-22 | 2017-03-07 | Arm Ltd. | Method, system and device for complementary non-volatile memory device operation |
| US10403347B2 (en) * | 2018-01-29 | 2019-09-03 | Micron Technology, Inc. | Apparatuses and methods for accessing ferroelectric memory including providing reference voltage level |
| CN116467988A (en) * | 2022-01-11 | 2023-07-21 | 长鑫存储技术有限公司 | Reading out circuit layout |
| CN117809701B (en) * | 2023-12-06 | 2024-10-18 | 北京大学 | Memory array and in-memory computing circuit |
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