CN103021450A - Compact charge transfer refresh circuit and refresh method thereof - Google Patents
Compact charge transfer refresh circuit and refresh method thereof Download PDFInfo
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- CN103021450A CN103021450A CN2011102850308A CN201110285030A CN103021450A CN 103021450 A CN103021450 A CN 103021450A CN 2011102850308 A CN2011102850308 A CN 2011102850308A CN 201110285030 A CN201110285030 A CN 201110285030A CN 103021450 A CN103021450 A CN 103021450A
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Abstract
The invention belongs to the technical field of memories and especially relates to a compact charge transfer refresh circuit and a refresh method thereof. The compact charge transfer refresh circuit comprises an array of M*N. The array is divided into t subarrays of M*(N/t) in a row direction. The serial numbers of the subarrays are in a range of 1 to n. Virtual power ends VHn of sense amplifiers of the subarrays are connected. Virtual power ends VHn between the subarrays are connected by charge transfer switches Tn. M, N, n and t represent natural numbers. The virtual power ends of the sense amplifiers of the subarrays are connected and VHn represents the virtual power ends. The virtual power ends VHn between the subarrays are connected by the charge transfer switches Tn. The compact charge transfer refresh circuit reduces refresh power consumption, obviously reduces refresh time, has a simple control circuit and has no additional area cost.
Description
Technical field
The invention belongs to the memory technology field, relate in particular to a kind of close-coupled electric charge and shift refresh circuit and method of operating thereof.
Background technology
In recent years, dynamic RAM is widely used in all kinds of aspects such as consumer electronics product, image/video process chip, game machine.Traditionally, DRAM compares the main inferior position of SRAM in embedded device is used and is: the volatibility of memory cell data causes and need to refresh, and this has brought extra steering logic expense and data to keep the power consumption expense.In data keep power consumption, refresh the dynamic power consumption that brings and account for 30%, this part dynamic power consumption mainly comes from reading of unit and writes back and operate in the voltage swing that brings on the bit line.
For the data that reduce DRAM keep power consumption, traditional scheme is several groups of bit lines or array partition sub-bit-line or subarray spatially all, on sequential an accessed array operation is divided into successively twice child-operation according to the division of set of bit lines or array.Referring to accompanying drawing 1 and accompanying drawing 2, for conventional charge shifts refresh circuit synoptic diagram and time sequential routine figure (list of references, A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs, Symposium on VLSI Circuits Digest of Technical Papers, 1995, pp.101-102), a logical line is refreshed array partition become subarray A and subarray B, the empty power end of all sense amplifiers of each subarray links to each other, be denoted as VHn, and the empty power end between subarray links to each other by charge transfer switch T.Like this, the stray capacitance Cp of subarray A/B (comprising bit line stray capacitance Cb and empty power end stray capacitance Cv, Cp=Cb+Cv) and charge transfer switch T have consisted of basic charge share model.Accompanying drawing 3 refreshes once capable refresh operation step exploded view for conventional charge shifts, wherein stage (1)～stage (3) is refreshed the stage for subarray A, and stage (4)～stage (7) is refreshed the stage for subarray B.Electric charge shifts stage (the 3)～stage (5) that occurs in: when the sense amplifier of subarray A is opened and after the unit write back, bit line and not immediately zero clearing of empty power end VHA, but the empty power end VHB of this part electric charge and subarray B is shared (as shown in fig. 1 charge transfer switch T unlatching), remove to drive its bit line small-signal as the power supply of subarray B sense amplifier and partly amplify, thereby saved when amplifying charge consumption for power supply.Capable the refreshing of subarray (namely writing back an operation) time is a clock period, once goes to refresh to take 2 clock period.
Conventional charge shifts and to refresh (charge transfer refresh, CTR) so that the memory refress power-dissipation-reduced, but has the following disadvantages:
Charge transfer effciency has much room for improvement;
The refresh time of once going can further be optimized;
The time overhead problem of charge transfer effciency problem and accessed array operation.According to the charge share model, charge transfer effciency (both sides' stray capacitance exchange charge amount in the unit interval) is relevant with transfer both sides stray capacitance size with charge transfer switch pipe size.Consider in logical line refresh operation, charge transfer switch pipe opening time section and other operational phase proportion, its unbalanced pulse width obviously has certain restriction, and consider the laying out pattern factor, electric charge transfer pipeline size is determined, thereby the principal element that improves charge transfer effciency is the size of stray capacitance, namely how to divide array;
In addition, because the operation of accessed array is divided into the sub-accessed array operation that precedence is repeatedly arranged, carry out the electric charge jump operation between bit line or array, it is elongated therefore once to visit the array processing time.Consider that a logical line refreshes, such as Fig. 1 and 2, in (2) later stage in stage and stage (3), electric charge on the stray capacitance Cp of subarray A is in hold mode, be not transferred, and this moment, subarray B not yet began refresh operation, had therefore become during this period of time once to go the redundancy time of refresh operation, and correspondingly the data accessibility of storer has reduced.
Another kind of traditional electric charge shifts method for refreshing (patent publication No. CN 1898748A), the method of electric charge proposes repeatedly to circulate between a plurality of arrays again, but still have the following disadvantages, (1) need between a plurality of arrays, set up complicated switching mechanism, the inductive switch controller of corresponding needs complexity, the area utilization ratio is not high; (2) it is loose to shift refresh step with the electric charge between a plurality of arrays of delegation, and the row refresh time is long, and the data accessibility of storer is not high.
The present invention improves electric charge and shifts the efficient that refreshes by the pair array classifying rationally; Propose simultaneously compact refresh scheme, shorten once capable refresh time, improve the data accessibility of storer.
Summary of the invention
In order to achieve the above object, the present invention proposes a kind of close-coupled electric charge and shifts refresh circuit, comprise that size is the array of M*N, be divided in column direction the subarray of t M * (N/t), each subarray numbering 1～n, the empty power end VHn of the sense amplifier of each subarray links to each other, and the empty power end VHn between subarray links to each other by charge transfer switch Tn, M, N, n, t are natural number, the empty power end of all sense amplifiers of each subarray links to each other, be denoted as VHn, and the empty power end VHn between subarray links to each other by charge transfer switch Tn.
Preferably, the stray capacitance Cp of every adjacent subarray and charge transfer switch T have consisted of basic charge share model.
Preferably, stray capacitance Cp comprises bit line stray capacitance Cb and empty power end stray capacitance Cv, wherein Cp=Cb+Cv.
Preferably, each subarray starts successively every set time Tdelay and refreshes, and their bit line amplifies and is divided into that the part of electric charge after shifting amplified and the full amplitude of oscillation amplification of sense amplifier enable signal after opening.
Preferably, during each subarray refresh operation, the opening time of sense amplifier when the part amplification time equals normal running with full amplitude of oscillation amplification time sum.
Preferably, when entering refresh mode, each subarray is transferred to lower an array successively with the upper electric charge of its stray capacitance CP, simultaneously in order to add the fastrunning refresh operation, in the charge transfer process that every group of adjacent subarray carries out, make the electric charge of subarray stray capacitance CP not be transferred to another subarray with pausing.
In order to achieve the above object, the present invention also proposes a kind of close-coupled electric charge and shifts method for refreshing, be the array of M*N with size, be divided in column direction the subarray of t M * (N/t), each subarray numbering 1～n, the empty power end VHn of the sense amplifier of each subarray links to each other, and the empty power end VHn between subarray links to each other by charge transfer switch Tn, M, N, n, t is natural number, when entering refresh mode, each subarray is transferred to lower an array successively with the upper electric charge of its stray capacitance CP, simultaneously in order to add the fastrunning refresh operation, in the charge transfer process that every group of adjacent subarray carries out, make the electric charge of subarray stray capacitance CP not be transferred to another subarray with pausing.
Preferably, during each subarray refresh operation, the opening time of sense amplifier when the part amplification time equals normal running with full amplitude of oscillation amplification time sum.
Preferably, each subarray starts successively every set time Tdelay and refreshes, and their bit line amplifies and is divided into that the part of electric charge after shifting amplified and the full amplitude of oscillation amplification of sense amplifier enable signal after opening.
Preferably, during each subarray refresh operation, the opening time of sense amplifier when the part amplification time equals normal running with full amplitude of oscillation amplification time sum.
The invention provides and a kind ofly shift structure and the method that refreshes for compact electric charge, between adjacent subarray, shift and refresh electric charge, and the refresh step compactness of subarray is overlapping, both saved and refreshed power consumption, significantly reduced again refresh time, and control circuit is simple, need not extra area overhead.
Description of drawings
Accompanying drawing 1 shifts the refresh circuit synoptic diagram for conventional charge;
Accompanying drawing 2 shifts the refresh operation sequential chart for conventional charge;
Accompanying drawing 3 refreshes once capable refresh operation step exploded view for conventional charge shifts;
Accompanying drawing 5 refreshes once capable refresh operation step exploded view for shifting according to embodiment of the invention close-coupled electric charge;
Accompanying drawing 6 is to shift the refresh operation synoptic diagram according to embodiment of the invention close-coupled electric charge;
Accompanying drawing 7 is the comparison of three kinds of refresh schemes;
Accompanying drawing 8 is for shifting the simulation result that refreshes according to embodiment of the invention close-coupled electric charge;
Accompanying drawing 9 is the control signal sequential chart that shifts refresh operation according to embodiment of the invention close-coupled electric charge;
Accompanying drawing 10 is according to the control signal generation circuit of the embodiment of the invention based on array partition.
Embodiment
Accompanying drawing 4 is to shift the refresh circuit synoptic diagram according to embodiment of the invention close-coupled electric charge.Be size that 128 * 256 array is divided into 4 128 * 64 subarrays (each subarray numbering 1～n) in column direction, the empty power end of all sense amplifiers of each subarray links to each other, be denoted as VHn, and the empty power end VHn between subarray links to each other by charge transfer switch Tn.As example, subarray A, B, C, D have only been shown among the figure.It should be noted that, it is that 128 * 256 array is divided into 4 128 * 64 subarrays (each subarray numbering 1～n) in column direction that the embodiment here only exemplifies size, it will be appreciated by those skilled in the art that it is to be not limited to this, it can be expanded to general array, for example be that the array of M*N is divided into subarray (each subarray numbering 1～n) of t M * (N/t) in column direction with size, the empty power end VHn of the sense amplifier of each subarray links to each other, and the empty power end VHn between subarray links to each other by charge transfer switch Tn.Preferably, t can choose 4.
Accompanying drawing 5 refreshes once capable refresh operation step exploded view for shifting according to embodiment of the invention close-coupled electric charge.In stage (1), entering refresh mode, to refresh n capable, and subarray A unit is opened, and sets up the bit line small-signal.At stage (2), SAE
AOpen, the full amplitude of oscillation of subarray read output signal is amplified, and simultaneously, subarray B unit is opened, and sets up the bit line small-signal.In stage (3), subarray A bit line swings, and the unit is write back, another side, and T1 opens, and subarray B partly amplifies, and simultaneously, subarray C unit is opened, and sets up the bit line small-signal.At stage (4), SAE
BOpen, the full amplitude of oscillation of subarray read output signal is amplified.In stage (5), subarray B bit line swings, and the unit is write back, another side, and T2 opens, and subarray C partly amplifies, and simultaneously, subarray D unit is opened, and sets up the bit line small-signal.At stage (6), SAE
COpen, the full amplitude of oscillation of subarray read output signal is amplified.In stage (7), subarray C bit line swings, and the unit is write back, another side, and T3 opens, and subarray D partly amplifies.At stage (8), SAE
DOpen, the full amplitude of oscillation of subarray read output signal is amplified.In stage (9), subarray D bit line swings, and the unit is write back.Then it is capable to refresh n+1, gets back to the stage (1).Hence one can see that, when storer enters refresh mode, each subarray is transferred to lower an array successively with the upper electric charge of its stray capacitance CPn, simultaneously in order to add the fastrunning refresh operation, in the charge transfer process that every group of adjacent subarray carries out, stage in the traditional scheme (4)～(7) are advanced between stage (2)～(3) constantly carry out, so that the electric charge of subarray stray capacitance CPn is not transferred to another subarray with pausing.
As shown in Figure 6, accompanying drawing 6 is to shift the refresh operation synoptic diagram according to embodiment of the invention close-coupled electric charge.Wherein each subarray starts successively every set time Tdelay (1ns) and refreshes, and their bit line amplifies the full amplitude of oscillation amplification (such as stage (4), (6), (8)) after being divided into the part of electric charge after shifting and amplifying (such as stage (3), (5), (7)) and sense amplifier enable signal SAEn and open; Simultaneously during each subarray refresh operation, the opening time of sense amplifier had guaranteed that like this subarray refresh operation time is consistent with the normal working time when part amplification time equaled normal running with full amplitude of oscillation amplification time sum.Once going in the refresh operation, it is a clock period that each subarray is once gone the refresh operation time, and 4 capable refresh operations of subarray consist of accurate parallel work-flow, account for 2 clock period.
Accompanying drawing 7 is the comparison of three kinds of refresh schemes.Wherein, array size is 128 * 256, and subarray (128 * 64) once capable refresh time is a clock period 3ns.Employing conventional brush new departure once capable refresh time is about its 3.5 times, and employing conventional charge transfer refresh scheme once capable refresh time is its 2 times, and employing close-coupled electric charge transfer refresh scheme once capable refresh time is its 2 times.Can find out that the refresh time that proposes a plan is consistent with scheme 2, compare scheme 1 and reduce 43%, and the sense amplifier power consumption is compared the above two and reduced respectively 31.6% and 58.4%.
Accompanying drawing 10 is according to the control signal generation circuit of the embodiment of the invention based on array partition.By the control signal that produces in the sheet bunch SIGNAL, BSEL is divided into four the tunnel through the subarray chip selection signal, makes logic with three road time delayed signals that REN_REF produces, and finally generates the control signal bunch SIGNAL＜n of each subarray 〉.Wherein, after entering the close-coupled electric charge and shifting refresh mode, chip selection signal BSEL becomes low level, so that Sheffer stroke gate is invalid, output control signal bunch SIGNAL＜n〉depend on three road time delayed signals that REN_REF produces.Three tunnel pulsewidth DL2 that produced by REN_REF this moment, the signal of the DL1 that mutually delays time and the SIGANL signal that is produced by iRREQ one tunnel become final output control signal bunch SIGNAL＜n 〉.
Although illustrate and described the preferred embodiments of the present invention, it will be apparent for a person skilled in the art that at it and can make a lot of variations and modification without departing from the invention aspect wider.The present invention is applicable to the dynamic RAM that adopts any unit; Be applicable to adopt any refresh scheme (distributed refresh, lump type refresh etc.).
Claims (10)
1. a close-coupled electric charge shifts refresh circuit, comprise that size is the array of M*N, be divided in column direction the subarray of t M * (N/t), each subarray numbering 1～n, the empty power end VHn of the sense amplifier of each subarray links to each other, and the empty power end VHn between subarray links to each other by charge transfer switch Tn, and M, N, n, t are natural number, it is characterized in that:
The empty power end of all sense amplifiers of each subarray links to each other, and be denoted as VHn, and the empty power end VHn between subarray links to each other by charge transfer switch Tn.
2. close-coupled electric charge according to claim 1 shifts refresh circuit, and it is characterized in that: the stray capacitance Cp of every adjacent subarray and charge transfer switch Tn have consisted of basic charge share model.
3. close-coupled electric charge according to claim 2 shifts refresh circuit, and it is characterized in that: stray capacitance Cp comprises bit line stray capacitance Cb and empty power end stray capacitance Cv, wherein Cp=Cb+Cv.
4. close-coupled electric charge according to claim 1 shifts refresh circuit, it is characterized in that: each subarray starts successively every set time Tdelay and refreshes, and their bit line amplifies and is divided into that the part of electric charge after shifting amplified and the full amplitude of oscillation amplification of sense amplifier enable signal after opening.
5. close-coupled electric charge according to claim 4 shifts refresh circuit, it is characterized in that: during each subarray refresh operation, and the opening time of sense amplifier when the part amplification time equals normal running with full amplitude of oscillation amplification time sum.
6. close-coupled electric charge according to claim 3 shifts refresh circuit, it is characterized in that: when entering refresh mode, each subarray is transferred to lower an array successively with the upper electric charge of its stray capacitance CP, simultaneously in order to add the fastrunning refresh operation, in the charge transfer process that every group of adjacent subarray carries out, make the electric charge of subarray stray capacitance CP not be transferred to another subarray with pausing.
7. a close-coupled electric charge shifts method for refreshing, be the array of M*N with size, be divided in column direction the subarray of t M * (N/t), each subarray numbering 1～n, the empty power end VHn of the sense amplifier of each subarray links to each other, and the empty power end VHn between subarray links to each other by charge transfer switch Tn, and M, N, n, t are natural number, it is characterized in that:
When entering refresh mode, each subarray is transferred to lower an array successively with the upper electric charge of its stray capacitance CP, simultaneously in order to add the fastrunning refresh operation, in the charge transfer process that every group of adjacent subarray carries out, make the electric charge of subarray stray capacitance CP not be transferred to another subarray with pausing.
8. a kind of close-coupled electric charge according to claim 7 shifts method for refreshing, it is characterized in that: during each subarray refresh operation, and the opening time of sense amplifier when the part amplification time equals normal running with full amplitude of oscillation amplification time sum.
9. a kind of close-coupled electric charge according to claim 7 shifts method for refreshing, it is characterized in that: each subarray starts successively every set time Tdelay and refreshes, and their bit line amplifies and is divided into that the part of electric charge after shifting amplified and the full amplitude of oscillation amplification of sense amplifier enable signal after opening.
10. a kind of close-coupled electric charge according to claim 9 shifts method for refreshing, it is characterized in that: during each subarray refresh operation, and the opening time of sense amplifier when the part amplification time equals normal running with full amplitude of oscillation amplification time sum.
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| CN201110285030.8A CN103021450B (en) | 2011-09-22 | 2011-09-22 | Close-coupled Charger transfer refresh circuit and method for refreshing thereof |
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| CN201110285030.8A CN103021450B (en) | 2011-09-22 | 2011-09-22 | Close-coupled Charger transfer refresh circuit and method for refreshing thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0203718A2 (en) * | 1985-05-28 | 1986-12-03 | Nortel Networks Corporation | Dynamic MOS memory reference voltage generator |
| US4653030A (en) * | 1984-08-31 | 1987-03-24 | Texas Instruments Incorporated | Self refresh circuitry for dynamic memory |
| CN1898748A (en) * | 2003-10-23 | 2007-01-17 | 英飞凌科技股份公司 | Method and circuit configuration for multiple charge recycling during refresh operations in a dram device |
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- 2011-09-22 CN CN201110285030.8A patent/CN103021450B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4653030A (en) * | 1984-08-31 | 1987-03-24 | Texas Instruments Incorporated | Self refresh circuitry for dynamic memory |
| US4653030B1 (en) * | 1984-08-31 | 1997-08-26 | Texas Instruments Inc | Self refresh circuitry for dynamic memory |
| EP0203718A2 (en) * | 1985-05-28 | 1986-12-03 | Nortel Networks Corporation | Dynamic MOS memory reference voltage generator |
| CN1898748A (en) * | 2003-10-23 | 2007-01-17 | 英飞凌科技股份公司 | Method and circuit configuration for multiple charge recycling during refresh operations in a dram device |
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