CN103019984A - Bus parallel expansion method of diagnosis system - Google Patents
Bus parallel expansion method of diagnosis system Download PDFInfo
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- CN103019984A CN103019984A CN2012104845900A CN201210484590A CN103019984A CN 103019984 A CN103019984 A CN 103019984A CN 2012104845900 A CN2012104845900 A CN 2012104845900A CN 201210484590 A CN201210484590 A CN 201210484590A CN 103019984 A CN103019984 A CN 103019984A
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Abstract
The invention discloses a bus parallel expansion method of a diagnosis system. According to the method, a bus length register, a bus length counter, a bus data register 1, a bus data register 2, a bus data register 3, a bus data register 4 and a parallel data bit expansion register are provided. The method is applied to bus parallel expansion of the diagnosis system and has the characteristics of simple logic and quick response.
Description
Technical field
The invention belongs to the machine diagnostic field, relate in particular to a kind of bus parallel extended method of diagnostic system.
Background technology
Modern machine diagnostic system equipment is more and more, it is more and more faster that data bus speed requires, these reliability and stability to system data bus have proposed very high requirement, although Extended serial-bus equipment is simple, but speed is extremely slow, the expansion of data bus need to be considered from parallel bus, but many hardware can not be increased again simultaneously.
Summary of the invention
The object of the present invention is to provide a kind of bus parallel extended method of diagnostic system, be used for the bus parallel expansion of diagnostic system.
The technical scheme that realizes above-mentioned purpose is: a kind of bus parallel extended method of diagnostic system comprises bus length register, bus length counter, bus data register 1, bus data register 2, bus data register 3, bus data register 4 and parallel data bit extended register;
Described bus length register is delivered to described bus length counter as setting value with bus extension length data L0～L3;
Described bus length counter is counted according to system clock cycle, reaches setting value and sends enable signal En to described parallel data bit extended register;
Described bus data register 1 is carried data D0～D7, to described parallel data bit extended register;
Described bus data register 2 is carried data D8～D15, to described parallel data bit extended register;
Described bus data register 3 is carried data D16～D23, to described parallel data bit extended register;
Described bus data register 4 is carried data D24～D31, to described parallel data bit extended register;
The data D0 that described parallel data bit extended register reception bus data register 1 is carried～D7, the data D8 that described bus data register 2 is carried～D15, the data D16 that described bus data register 3 is carried～D23, the data D24 that described bus data register 4 is carried～D31, at the enable signal En that receives that described bus length counter sends, growth data bus to 32 D0～D31.
Bus extension length data L0～L3 that above-mentioned bus length register is carried only has 4, every increase by 1, and representing highway width increases by 1 byte wide, is exactly 8 bit widths.
The invention has the beneficial effects as follows: use few hardware resource, realize the parallel data expansion on the diagnostic system bus, have logic simple, respond fast characteristics.
Description of drawings
Fig. 1 is structural representation of the present invention.
Embodiment
The invention will be further described below in conjunction with accompanying drawing.
Please refer to Fig. 1, provided a kind of bus parallel extended method of diagnostic system among the figure, wherein bus length register, bus length counter, bus data register 1, bus data register 2, bus data register 3, bus data register 4 and parallel data bit extended register are realized by a slice fpga chip of ATLERA company, and model is EP1K50;
4 bus length register is delivered to 4 bus length counters as setting value with bus extension length data L0～L3;
4 bus length counter is counted according to system clock cycle, reaches setting value and sends enable signal En to 32 parallel data bit extended register;
8 bus data register 1 is carried data D0～D7, to described parallel data bit extended register;
8 bus data register 2 is carried data D8～D15, to 32 parallel data bit extended register;
8 bus data register 3 is carried data D16～D23, to 32 parallel data bit extended register;
8 bus data register 4 is carried data D24～D31, to 32 parallel data bit extended register;
The data D0 that 32 parallel data bit extended register reception bus data register 1 is carried～D7, the data D8 that described bus data register 2 is carried～D15, the data D16 that described bus data register 3 is carried～D23, the data D24 that described bus data register 4 is carried～D31, at the enable signal En that receives that 4 bus length counters send, growth data bus to 32 D0～D31.
Bus extension length data L0～L3 that 4 bus length register is carried only has 4, every increase by 1, and representing highway width increases by 1 byte wide, is exactly 8 bit widths.
Principle of the present invention is: utilize the speed of parallel sequential logic to realize the fastest data bus transmitting extended, utilize the power of fpga logic chip to realize parallel data expansion on the diagnostic system bus, have logic simple, respond fast characteristics.
Below embodiment has been described in detail the present invention by reference to the accompanying drawings, and those skilled in the art can make the many variations example to the present invention according to the above description.Thereby some details among the embodiment should not consist of limitation of the invention, and the scope that the present invention will define with appended claims is as protection scope of the present invention.
Claims (2)
1. the bus parallel extended method of a diagnostic system, it is characterized in that, comprise bus length register, bus length counter, bus data register 1, bus data register 2, bus data register 3, bus data register 4 and parallel data bit extended register;
Described bus length register is delivered to described bus length counter as setting value with bus extension length data L0～L3;
Described bus length counter is counted according to system clock cycle, reaches setting value and sends enable signal En to described parallel data bit extended register;
Described bus data register 1 is carried data D0～D7, to described parallel data bit extended register;
Described bus data register 2 is carried data D8～D15, to described parallel data bit extended register;
Described bus data register 3 is carried data D16～D23, to described parallel data bit extended register;
Described bus data register 4 is carried data D24～D31, to described parallel data bit extended register;
The data D0 that described parallel data bit extended register reception bus data register 1 is carried～D7, the data D8 that described bus data register 2 is carried～D15, the data D16 that described bus data register 3 is carried～D23, the data D24 that described bus data register 4 is carried～D31, at the enable signal En that receives that described bus length counter sends, growth data bus to 32 D0～D31.
2. the bus parallel extended method of a kind of diagnostic system according to claim 1, it is characterized in that bus extension length data L0～L3 that described bus length register is carried only has 4, every increase by 1, representing highway width increases by 1 byte wide, is exactly 8 bit widths.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104845900A CN103019984A (en) | 2012-11-26 | 2012-11-26 | Bus parallel expansion method of diagnosis system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104845900A CN103019984A (en) | 2012-11-26 | 2012-11-26 | Bus parallel expansion method of diagnosis system |
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| Publication Number | Publication Date |
|---|---|
| CN103019984A true CN103019984A (en) | 2013-04-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012104845900A Pending CN103019984A (en) | 2012-11-26 | 2012-11-26 | Bus parallel expansion method of diagnosis system |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2417999Y (en) * | 1999-12-07 | 2001-02-07 | 中国科学院长春光学精密机械研究所 | Parallel/serial connection converter special for laser phototypesetter |
| CN1427424A (en) * | 2002-11-01 | 2003-07-02 | 深圳迈瑞生物医疗电子股份有限公司 | Method of high voltage potential meter numerical control resistance value and product |
| CN1433161A (en) * | 2002-01-08 | 2003-07-30 | 华为技术有限公司 | Data transmitting method and circuit for medium access control interface in APON system |
| CN2847443Y (en) * | 2005-11-17 | 2006-12-13 | 海信集团有限公司 | Digital tube driving circuit |
-
2012
- 2012-11-26 CN CN2012104845900A patent/CN103019984A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2417999Y (en) * | 1999-12-07 | 2001-02-07 | 中国科学院长春光学精密机械研究所 | Parallel/serial connection converter special for laser phototypesetter |
| CN1433161A (en) * | 2002-01-08 | 2003-07-30 | 华为技术有限公司 | Data transmitting method and circuit for medium access control interface in APON system |
| CN1427424A (en) * | 2002-11-01 | 2003-07-02 | 深圳迈瑞生物医疗电子股份有限公司 | Method of high voltage potential meter numerical control resistance value and product |
| CN2847443Y (en) * | 2005-11-17 | 2006-12-13 | 海信集团有限公司 | Digital tube driving circuit |
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Application publication date: 20130403 |