CN103001618A - Differential switch capacitor structure low in parasitic effect and high in quality factor - Google Patents

Abstract

The invention discloses a differential switch capacitor structure low in parasitic effect and high in quality factor. Compared with the conventional differential switch capacitor structure, the differential switch capacitor structure mainly has two improvements that PMOS (p-channel metal oxide semiconductor) tubes P1 and P2 are removed, parasitic effect caused by the PMOS tubes is eliminated; and an inverter and a resistor are serially connected between an input end of a digital signal D and a drain electrode of a switch radio-frequency tube, and parasitic effect of a switch tube is reduced. The improved differential switch capacitor structure has the advantages of low parasitic effect, high quality factor and wide tuning range.

Description

The differential switch capacitance structure that the low-quality factor of a kind of ghost effect is high

Technical field

The present invention relates generally to discrete capacitor design field, especially refers to the differential switch capacitance structure that a kind of ghost effect is low, quality factor are high.

Background technology

In recent years, along with the development that wireless communication technique is advanced by leaps and bounds, multiple standards compatibility and wideband communication system become inexorable trend.As the key modules of this system, voltage controlled oscillator requires to have enough wide frequency coverage and harsh phase noise performance.The tuning LC VCO maximum that realizes based on the standard CMOS process varactor can realize the frequency tuning range about 20%.Simultaneously, adopt large-sized varactor easily amplitude noise to be converted into phase noise, make the phase noise variation.For this reason, people have proposed employing numerical control switch capacitance technology and have realized variable capacitance.But traditional switched capacitor array is made of nmos pass transistor and capacitances in series, and the drain terminal parasitic capacitance was so that resonant tank Q value is low and phase noise performance is poor when conducting resistance was with disconnection when the NMOS pipe was opened.Therefore, the design parasitic effect is low, and the switching capacity that quality factor are high becomes the difficult problem of switching capacity design.

Fig. 1 has showed a kind of traditional differential switch capacitance structure of being realized by nmos switch pipe and metal capacitance.When switch controlling signal D is high level, nmos switch pipe N ₁, N ₂And N ₃Closure, PMOS switching tube P ₁And P ₂Disconnect, switching capacity is in closure state, this moment Switch capacitor structure equivalent electric circuit as shown in Figure 3, R wherein _ON1, R _ON2And R _ON3Equivalent resistance during three nmos switch pipe conductings of difference, this moment, switching capacity appearance value size can be expressed as:

C _ON≈C ₁//C ₂ (1)

Its quality factor q can be expressed as:

$Q=\frac{1}{{\mathrm{\&omega;}}_0\&CenterDot;({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="1211021107252.png"\; state="\{\{state\}\}">C</figure-callout>}}_1//C_2)\&CenterDot;((R_{\mathrm{ON}1}+R_{\mathrm{ON}2})//R_{\mathrm{ON}3})}---\left(2\right)$

ω in the formula ₀Be operating frequency, R _ION=[(μ _nC _Ox) (W _i/ L) (V _GS-V _TH)] ^-1Be switching tube N _iConducting resistance.From formula (2), can draw the conducting resistance R of switching tube during owing to conducting _IONExistence, the effective Q value of switching capacity reduces, thereby reduces the phase noise performance of LC oscillator.

When switch controlling signal D is low level, nmos switch pipe N _iClose PMOS switching tube P _iClosure, switching capacity is in off-state, this moment the switching capacity equivalent electric circuit as shown in Figure 4, this moment, switching capacity appearance value size can be expressed as:

C _OFF≈(C ₁//(C _N1par+C _par1))//(C ₂//(C _N2par+C _par2))(3)

C wherein _ParBe the bottom crown of metal capacitance C and the parasitic capacitance of ground formation, C _NparFor the drain electrode of nmos switch pipe produces edge capacitance, its value equals W _SwC _Dd, W wherein _SwThe width of switching tube, C _DdBe drain terminal edge unit width capacitance, unit is fF/ μ m.Because when switch disconnected, metal capacitance was not isolated in outside the resonator fully, access in the resonator afterwards but connect with parasitic capacitance, this effect greatly reduces the tuning range of electric capacity.

For the defective that the single-ended Switch capacitor structure of tradition exists, the designer has proposed the differential switch capacitance structure that a kind of ghost effect is low, quality factor are high shown in Figure 2.Switch controlling signal D receives the grid of nmos switch pipe N1, N2 and the input of inverter INV (001,002) simultaneously, and the drain electrode of nmos switch pipe N1 connects capacitor C ₁An end, capacitor C ₁The other end be output P, output and the resistance R of inverter INV (001) ₁An end join resistance R ₁The other end connect the drain terminal of nmos switch pipe N1, the drain electrode of nmos switch pipe N2 connects capacitor C ₂An end, capacitor C ₂The other end be output N, output and the resistance R of inverter INV (002) ₂An end join resistance R ₂The other end connect the drain terminal of nmos switch pipe N2, the drain electrode of nmos switch pipe N3 is connected to the drain electrode of nmos switch pipe N1, its source electrode is connected to the drain electrode of nmos switch pipe N2, the grid of nmos switch pipe N3 meets digital controlled signal D.

Equivalent circuit structure when Fig. 5 has provided the switch closure of differential switch capacitance structure of the present invention.Since when digital controlled signal D is high level, nmos switch pipe N _iOpen PMOS switching tube P _iDisconnect, this moment switching capacity effective appearance value and Fig. 1 in the same, and its effective quality factor can be expressed as:

$Q=\frac{1}{{\mathrm{\&omega;}}_0\&CenterDot;({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="1211021107252.png"\; state="\{\{state\}\}">C</figure-callout>}}_1//C_2)\&CenterDot;(((R_{\mathrm{ON}1}+R_{\mathrm{ON}2})//R_{\mathrm{ON}3})//(R_1+R_2))}---\left(4\right)$

Since digital signal D by inverter and resistance with E _PAnd E _NNode pulls down to ground, has reduced NMOS pipe N ₁, N ₂Conducting resistance, this moment E _PAnd E _NThe DC potential of two nodes is identical, so that the two is empty short, has reduced the equivalent resistance of N3 pipe conducting.Therefore, the equiva lent impedance of differential switch electric capacity of the present invention is very little under the opening, has increased the effective quality factor of switching capacity.

When switch controlling signal D is low level, nmos switch pipe N _iClose, switching capacity is in off-state, this moment the switching capacity equivalent electric circuit as shown in Figure 6 since this moment E _PAnd E _NNode is inverted on device and the resistance and comes VDD, so that the drain electrode of transistor N1, N2-substrate PN junction presents large partially anti-at this moment, so that the depletion region of PN junction increases, greatly reduced the parasitic capacitance of drain electrode to the impact of switching capacity, Simultaneous Switching electric capacity bottom crown parasitic capacitance C over the ground _ParAlso very little, can ignore.Switching tube N3 because the drain-source both end voltage is VDD, do not open by pipe yet, causes its equivalent resistance infinitely great.Therefore, the filtering characteristic that shows low pass of modified model switch capacitance structure can be isolated fully with resonant cavity under the closed condition, does not affect the frequency of oscillation of LC oscillator.

In sum, differential switch capacitance structure of the present invention has reduced the parasitic capacitance when closing, and the dead resistance when having reduced to open has improved switch electric tuning scope, has increased the quality factor of switched capacitor array.

Summary of the invention

The problem to be solved in the present invention is: the problem for prior art exists the invention provides the differential switch capacitance structure that a kind of ghost effect is low, quality factor are high.

For realizing above-mentioned technical problem, the solution that the present invention proposes is: NMOS pipe (N1), the 2nd NMOS pipe (N2), the 3rd NMOS pipe (N3), the first inverter INV (001), the second inverter INV (002), the first resistance (R ₁), the second resistance (R ₂), the first metal capacitance (C ₁), the second metal capacitance (C ₂), wherein the grid of NMOS pipe (N1) meets digital controlled signal D, and drain electrode meets the first metal capacitance (C ₁) an end, source electrode connects power supply ground, the input of the first inverter INV (001) meets digital controlled signal D, output meets the first resistance (R ₁) an end, the first resistance (R ₁) the drain electrode of another termination the one NMOS pipe (N1), the first metal capacitance (C ₁) another termination output P, the grid of the 2nd NMOS pipe (N2) meets digital controlled signal D, drain electrode meets the second metal capacitance (C ₂) an end, source electrode connects power supply ground, the input of the second inverter INV (002) meets digital controlled signal D, output meets the second resistance (R ₂) an end, the second resistance (R ₂) the drain electrode of another termination the 2nd NMOS pipe (N2), the second metal capacitance (C ₂) another termination output N, the drain electrode of the 3rd NMOS pipe (N3) connects the drain electrode of NMOS pipe (N1), source electrode connects the drain electrode of the 2nd NMOS pipe (N2), grid meets digital controlled signal D.

Compared with prior art, the invention has the advantages that:

1, reduced the ghost effect of differential switch capacitance structure.Compare with traditional differential switch electric capacity, switching tube has good switching characteristic in the Switch capacitor structure of the present invention.

2, the quality factor of differential switch capacitance structure have been increased.Compare with traditional differential switch capacitance structure, differential switch capacitance structure dead resistance of the present invention is little, has increased effective quality factor.

3, improved the tuning range of differential switch electric capacity.Compare with traditional differential switch capacitance structure, switched capacitor array ghost effect of the present invention is little, increases maximum effectively appearance value and the minimum effectively difference of appearance value, thereby has improved the tuning range of differential switch electric capacity.

Description of drawings

Fig. 1 is traditional differential switch capacitance structure schematic diagram;

Fig. 2 is differential switch capacitance structure schematic diagram of the present invention;

Fig. 3 is traditional differential switch electric capacity schematic equivalent circuit when closing;

Schematic equivalent circuit when Fig. 4 is traditional differential switch electric capacity unlatching;

Fig. 5 is differential switch electric capacity of the present invention schematic equivalent circuit when closing;

Schematic equivalent circuit when Fig. 6 is differential switch electric capacity unlatching of the present invention;

Embodiment

Below with reference to the drawings and specific embodiments the present invention is described in further details.

As shown in Figure 2, the present invention is the Kind of Switched Capacitor Array that a kind of ghost effect is low, quality factor are high, and it comprises NMOS pipe (N1), the 2nd NMOS pipe (N2), the 3rd NMOS pipe (N3), the first inverter INV (001), the second inverter INV (002), the first resistance (R ₁), the second resistance (R ₂), the first metal capacitance (C ₁), the second metal capacitance (C ₂), wherein the grid of NMOS pipe (N1) meets digital controlled signal D, and drain electrode meets the first metal capacitance (C ₁) an end, source electrode connects power supply ground, the input of the first inverter INV (001) meets digital controlled signal D, output meets the first resistance (R ₁) an end, the first resistance (R ₁) the drain electrode of another termination the one NMOS pipe (N1), the first metal capacitance (C ₁) another termination output P, the grid of the 2nd NMOS pipe (N2) meets digital controlled signal D, drain electrode meets the second metal capacitance (C ₂) an end, source electrode connects power supply ground, the input of the second inverter INV (002) meets digital controlled signal D, output meets the second resistance (R ₂) an end, the second resistance (R ₂) the drain electrode of another termination the 2nd NMOS pipe (N2), the second metal capacitance (C ₂) another termination output N, the drain electrode of the 3rd NMOS pipe (N3) connects the drain electrode of NMOS pipe (N1), source electrode connects the drain electrode of the 2nd NMOS pipe (N2), grid meets digital controlled signal D.

Operation principle: when switch controlling signal D was high level, switching tube N1, N2, N3 all opened, and node EP and EN current potential pulled down to ground, so that capacitor C 1 and C2 access resonator, its conducting resistance is that RON is very little, has reduced equivalent dead resistance, has increased the quality factor of switching capacity.When switch controlling signal D is low level, switching tube N1, N2, N3 all disconnect, this moment node EP and EN current potential by on move near VDD, so that the drain electrode of switching tube N1, N2 and substrate PN junction present large anti-partially state, CNipar is very little for the drain edge parasitic capacitance, and the drain-source voltage of Simultaneous Switching pipe N3 is all near VDD, so that the two is empty disconnected, reduce effective appearance value of the access resonator when switching capacity is closed, increased its tuning range.

Claims (4)

1. differential switch capacitance structure that ghost effect is low, quality factor are high is characterized in that: two switching capacity branch roads about it comprises, and input signal is digital controlled signal D, output signal is P and N.

2. differential switch capacitance structure according to claim 1, about the capacitor C 1 of two switching capacity branch roads identical with C2 appearance value, inverter INV(001) and inverter INV(002) measure-alike, switching tube N1 and N2 are measure-alike, resistance R ₁And R ₂Resistance is identical.

3. differential switch capacitance structure according to claim 1 is characterized in that: NMOS pipe (N1), the 2nd NMOS pipe (N2), the 3rd NMOS pipe (N3), the first inverter (001), the second inverter (002), the first resistance (R ₁), the second resistance (R ₂), the first metal capacitance (C ₁), the second metal capacitance (C ₂), wherein the grid of NMOS pipe (N1) meets digital controlled signal D, and drain electrode meets the first metal capacitance (C ₁) an end, source ground, the first inverter INV(001) input meet digital controlled signal D, output meets the first resistance (R ₁) an end, the first resistance (R ₁) the drain electrode of another termination the one NMOS pipe (N1), the first metal capacitance (C ₁) another termination output P, the grid of the 2nd NMOS pipe (N2) meets digital controlled signal D, drain electrode meets the second metal capacitance (C ₂) an end, source ground, the second inverter INV(002) input meet digital controlled signal D, output meets the second resistance (R ₂) an end, the second resistance (R ₂) the drain electrode of another termination the 2nd NMOS pipe (N2), the second metal capacitance (C ₂) another termination output N, the drain electrode of the 3rd NMOS pipe (N3) connects the drain electrode of NMOS pipe (N1), source electrode connects the drain electrode of the 2nd NMOS pipe (N2), grid meets digital controlled signal D.

4. differential switch capacitance structure according to claim 1, resistance R ₁And R ₂Resistance requires in M Ω level.

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