CN103000687A - Non-planar semiconductor structure and process for same - Google Patents
Non-planar semiconductor structure and process for same Download PDFInfo
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- CN103000687A CN103000687A CN 201110270877 CN201110270877A CN103000687A CN 103000687 A CN103000687 A CN 103000687A CN 201110270877 CN201110270877 CN 201110270877 CN 201110270877 A CN201110270877 A CN 201110270877A CN 103000687 A CN103000687 A CN 103000687A
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Abstract
The invention discloses a non-planar semiconductor structure and a process for the same. The non-planar semiconductor structure comprises a substrate, at least two fin-shaped structures, at least one insulating structure and a plurality of epitaxial layers. The fin-shaped structures are positioned on the substrate. The insulating structures are positioned among the fin-shaped structures and are provided with nitrogenous layers. The epitaxial layers respectively cover parts of the fin-shaped structures and are positioned on the nitrogenous layers.
Description
Technical field
The present invention relates to a kind of semiconductor structure and technique thereof, particularly relate to a kind of semiconductor structure and technique thereof that on the contact-making surface of insulation system and epitaxial loayer, forms nitrogenous layer.
Background technology
Along with dwindling of semiconductor element size, the usefulness of keeping the small size semiconductor element is the main target of present industry.In order to improve the usefulness of semiconductor element, develop gradually at present various fin-shaped field-effect transistor elements (Fin-shaped field effect transistor, FinFET).The fin-shaped field-effect transistor element comprises following several advantages.At first, the technique of fin-shaped field-effect transistor element can with traditional logic element process integration, therefore have suitable process compatibility; Secondly, because the three-dimensional shape of fin structure has increased the contact area of grid and substrate, therefore can increase grid for the control of channel region electric charge, what thereby the drain electrode that the reduction small-sized component is brought caused can be with reduction (Drain Induced Barrier Lowering, DIBL) effect and short-channel effect (short channel effect); In addition, because the grid of same length has larger channel width, therefore also can increase the magnitude of current between source electrode and drain electrode.
Known fin-shaped field-effect transistor element still has development space.For example, epitaxial loayer in the general fin-shaped field-effect transistor element coats the fin structure as source/drain region, with the cumulative volume of increase source/drain region, wherein epitaxial loayer is in the selectivity deposition and when coating the fin structure surface, and its lower surface can contact with the insulation system of below.Yet because epitaxial loayer and the difference of insulation system on material, the two is understood mutually exclusive and makes epitaxial loayer produce the take-off angle of the crystal plane that is close to 54.8 °, causes the two to fit; In other words, grow because the relative insulation system of epitaxial loayer meeting makes progress with the oblique angle, thereby limited to the cumulative volume that outer layer growth goes out.Moreover it is attached to it that this structure also can make follow-up metal silicide be difficult for.
Therefore, the present invention namely improves for known fin-shaped field-effect transistor element, with the usefulness of further lift element.
Summary of the invention
The present invention proposes a kind of semiconductor structure and technique thereof, its contact-making surface at insulation system and epitaxial loayer forms nitrogenous layer, thereby can increase the contact area of epitaxial loayer and insulation system, and then increase the cumulative volume of epitaxial loayer and metal silicide easily is formed on the epitaxial loayer.
The invention provides a kind of semiconductor structure, comprise substrate, at least two fin structures, at least one insulation system and a plurality of epitaxial loayer.Fin structure is positioned in the substrate.Insulation system is between fin structure, and insulation system has nitrogenous layer.Epitaxial loayer is the cover part fin structure respectively, and is positioned on the nitrogenous layer.
The invention provides a kind of semiconductor technology, comprise the steps.At first, provide substrate.Then, form at least two fin structures in substrate.Then, form oxide layer between fin structure.Afterwards, form nitrogenous layer, in oxide layer.Then, carry out epitaxy technique, to form a plurality of epitaxial loayers cover part fin structure.
Based on above-mentioned, the invention provides a kind of semiconductor structure and technique thereof, it forms nitrogenous layer between epitaxial loayer and insulation system (for example oxide layer), make between epitaxial loayer and the insulation system not can because of the mutually exclusive epitaxial loayer that produces with respect to the angle of oxide layer.Therefore, semiconductor structure of the present invention can increase the contact area of epitaxial loayer and oxide layer, thereby increases the cumulative volume of formed epitaxial loayer.So, can make the follow-up metal silicide that is formed on the epitaxial loayer be easier to adhere to, and can increase its surface area.
Description of drawings
Fig. 1 illustrates the generalized section of the semiconductor structure that contains silicon base of the embodiment of the invention.
Fig. 2 illustrates the generalized section of the semiconductor structure that contains the silicon-on-insulator substrate of another embodiment of the present invention.
Fig. 3-9 illustrates the generalized section of the semiconductor technology of the embodiment of the invention.
Figure 10 illustrates the generalized section of the semiconductor technology of another embodiment of the present invention.
Description of reference numerals
100a, 100b: semiconductor structure 110,212: substrate
120a, 120b, 220a, 220b: fin structure
122: pad oxide 124: nitration case
130: insulation system 140a, 140b: epitaxial loayer
150,150a, 150 ': nitrogenous layer 160: grid structure
162: gate dielectric 164: gate electrode
166: cap rock 168: clearance wall
210: silicon-on-insulator substrate 214: bottom oxide
216: silicon layer E1: etching photolithograhic technique
E2: epitaxy technique N: nitriding process
Embodiment
Fig. 1 illustrates the generalized section of the semiconductor structure that contains silicon base of the embodiment of the invention.Fig. 2 illustrates the generalized section of the semiconductor structure that contains the silicon-on-insulator substrate of another embodiment of the present invention.See also Fig. 1-2, semiconductor structure 100a and 100b all comprise substrate 110, two fin structure 120a and 120b, insulation system 130 and two epitaxial loayer 140a and 140b.Fin structure 120a and 120b are positioned in the substrate 110.Insulation system 130 is between fin structure 120a and 120b.Insulation system 130 has nitrogenous layer 150. Epitaxial loayer 140a and 140b be cover part fin structure 120a and 120b respectively, and is positioned on the nitrogenous layer 150.Fig. 1-2 only illustrates two fin structure 120a and 120b, but general semiconductor structure 100a and 100b can comprise more fin structures, and insulation system 130 is then between each fin structure.Certainly, will there be a plurality of epitaxial loayers to cover respectively these fin structures.Moreover in the embodiment of Fig. 1-2, semiconductor structure 100a and 100b can refer to fin-shaped field-effect transistor (Fin field-effect transistor) or three gate field effect transistors (Tri-gate MOSFET).As be fin-shaped field-effect transistor, the two side of fin structure 120a or 120b is then as the grid groove of semiconductor structure 100a or 100b, so semiconductor structure 100a or 100b have the bigrid raceway groove.As be three gate field effect transistors, the end face of fin structure 120a or 120b and two side be then as the grid groove of semiconductor structure 100a or 100b, so semiconductor structure 100a or 100b have three grid grooves.
Specifically, substrate 110 can comprise silicon base or silicon-on-insulator substrate etc., but the present invention is not as limit.As shown in Figure 1, take substrate 110 as example as silicon base.Two fin structure 120a and 120b directly extend from substrate 110, and wherein two fin structure 120a and 120b cover hard masks and utilize hard mask to carry out the photoetching etching and get in substrate 110, but the present invention is not as limit.130 of insulation systems are located between fin structure 120a and the 120b.Insulation system 130 can for example be oxide layer, and it can for example form with known shallow trench isolation technology.In the present embodiment, insulation system 130 has nitrogenous layer 150, its can be for example with Direct-Nitridation insulation system 130 surfaces or Direct precipitation nitration case on insulation system 130 and get, so nitrogenous layer 150 may comprise silicon nitride layer or silicon oxynitride layer, decides on actual demand and process.In addition, according to the difference of nitriding process, nitrogenous layer 150a also can also comprise between fin structure 120a and 120b and epitaxial loayer 140a and 140b. Epitaxial loayer 140a and 140b then distinguish cover part fin structure 120a and 120b, and are positioned on the nitrogenous layer 150.
Specific, nitrogenous layer 150 set positions are the contact-making surfaces close to epitaxial loayer 140a and 140b and insulation system 130.Thus, be doped into after the nitrogen-atoms, epitaxial loayer 140a and 140b and insulation system 130 just can not produce the rejection such as 54.8 ° of known described angle of approach, and can attach the superficial growth of this nitrogenous layer 150, and then can increase the contact area of epitaxial loayer 140a and 140b and insulation system 130, the cumulative volume that increase epitaxial loayer 140a and 140b are grown, thereby increase the surface area that is covered in the metal silicide (not illustrating) on epitaxial loayer 140a and the 140b.Moreover, because epitaxial loayer 140a of the present invention and 140b and insulation system 130 can more fit tightly, thereby can impel easier epitaxial loayer 140a and 140b and insulation system 130 surfaces of conformably being covered in fully of the metal levels such as titanium (Ti), cobalt (Co), nickel (Ni) of follow-up formation to carry out self-aligned metal silicate (Salicide) technique.
In addition, semiconductor structure 100a can comprise again grid structure 160, covers fin structure 120a and 120b between each epitaxial loayer 140a and the 140b.Specifically, grid structure 160 can comprise gate dielectric 162, gate electrode 164, cap rock 166 and clearance wall 168.Gate dielectric 162 covers fin structure 120a and 120b.Gate electrode 164 cover gate dielectric layers 162.Cap rock 166 cover gate electrodes 164.Clearance wall 168 is positioned at gate dielectric 162, gate electrode 164 and cap rock 166 sides.As with this structure, epitaxial loayer 140a and 140b then respectively with epitaxial loayer (not illustrating) with respect to grid structure 160 another sides, right as source/drain electrode.So, just, can form the multiple-grid utmost point field-effect transistor (Multi-gate MOSFET) of fin-shaped field-effect transistor or three gate field effect transistors (Tri-gate MOSFET) etc.Certainly, other elements also can be set again on this semiconductor structure 100a.In addition, the gate electrode 164 in the grid structure 160 can be metal gate electrode or polysilicon gate electrode.As be the polysilicon gate electrode, it can replace with metal gates in subsequent technique, and wherein subsequent technique can for example be rear grid (Gate last) technique.Rear grid technology can comprise again rear grid (the Gate last for high-k first) technique of preposition high-k or rear grid (the Gate last for high-k last) technique of rearmounted high-k.So being known by persons skilled in the art, the detailed process step repeats no more.
In addition, as shown in Figure 2, take substrate 110 as the silicon-on-insulator substrate as example.Its function class that can reach is similar to embodiment shown in Figure 1.Its insulation system 130 is directly to form one deck, and oxide layer for example is in substrate 110.Therefore, fin structure 120a and 120b then are formed on the insulation system 130, but not as shown in Figure 1, are extended by substrate 110.Yet because the structure of embodiment above insulation system 130 and fin structure 120a and 120b of Fig. 2 is still similar to the embodiment of Fig. 1, so also can reach the function of Fig. 1 embodiment, the present invention repeats no more.
Below provide semiconductor technology, in order to form above-mentioned semiconductor structure.Fig. 3-9 illustrates the generalized section of the semiconductor technology of the embodiment of the invention.Figure 10 illustrates the generalized section of the semiconductor technology of another embodiment of the present invention.
At first, take silicon base as example.As shown in Figure 3, provide substrate 110.Form mask layer (not illustrating) in substrate 110, wherein mask layer comprises that pad oxide (not illustrating) and nitration case (not illustrating) are positioned on the pad oxide.Carry out etching photolithograhic technique E1, patterned mask layer with the pad oxide 122 of formation patterning and the nitration case 124 of patterning, and exposes substrate 110 partly.Then, as shown in Figure 4, with the design transfer of pad oxide 122 and nitration case 124 to substrate 110 to form two fin structure 120a and 120b.In the present embodiment, forming two fin structure 120a and 120b.Then, as shown in Figure 5, utilize the techniques such as deposition, planarization and etch-back, form insulation system 130, oxide layer for example, between fin structure 120a and 120b, wherein insulation system 130 can for example form with shallow trench isolation structure.So, then can form two fin structure 120a and 120b in the substrate 110 and form insulation system 130 between fin structure 120a and 120b.Afterwards, pad oxide 122 and nitration case 124 can be removed, in subsequent technique, form three gate field effect transistors and make.In other embodiments, also can stay pad oxide 122 and nitration case 124, and in subsequent technique, form the fin-shaped field-effect transistor structure.
Perhaps, see also Fig. 6 A-6B, Fig. 6 A-6B is another exemplifying embodiment of present embodiment.At first, as shown in Figure 6A, take the silicon-on-insulator substrate as example, provide silicon-on-insulator substrate 210, it comprises that substrate 212, bottom oxide 214 are positioned in the substrate 212, and silicon layer 216 is positioned on the bottom oxide 214.Then, shown in Fig. 6 B, patterning silicon layer 216 to be forming fin structure 220a and 220b, and exposes part bottom oxide 214, between fin structure 220a and 220b.Thus, also can form two fin structure 220a and 220b in the substrate 212 and form insulation system (bottom oxide 214) between fin structure 220a and 220b.As shown in Figure 1,, and shown in Fig. 6 B, also can be positioned under the fin structure 220 with 214 of silicon-on-insulator substrate 210 formed bottom oxides only between fin structure 120a and 120b with the formed insulation system 130 of silicon base.Yet this two difference does not affect the follow-up semiconductor technology of the present invention.
Then, as shown in Figure 7, can form grid structure 160 on SI semi-insulation structure 130 and part fin structure 120a and 120b.The technique that forms grid structure 160 can comprise and sequentially deposits again patterning, and form gate dielectric 162 in SI semi-insulation structure 130 and part fin structure 120a and 120b is upper, gate electrode 164 on the gate dielectric 162, cap rock 166 on gate electrode 164 and clearance wall 168 in the side of gate dielectric 162, gate electrode 164 and cap rock 166, and the formation method of these material layers is known by one of ordinary skill in the art, so repeat no more.
As shown in Figure 8, form nitrogenous layer 150 in insulation system 130.In the present embodiment, carry out nitriding process N Direct-Nitridation insulation system 130, to form nitrogenous layer 150 in insulation system 130.But in other embodiments, also can deposit the formation nitrogenous layer on insulation system 130.In an embodiment, nitriding process N can comprise the deionization plasma nitridation process, contains the annealing process of ammonia, remote plasma nitriding process or hot nitriding process, but the present invention is not as limit.Under preferred exemplifying embodiment, after carrying out nitriding process N, can also comprise and carry out rear nitrogenize annealing process, wherein after the nitrogenize annealing process can be such as comprising the annealing process that contains ammonia etc.According to the method for different formation nitrogenous layers 150, the material of formed nitrogenous layer 150 may comprise silicon nitride layer or silicon oxynitride layer etc.In addition, nitriding process N can be all sidedly or partly nitrogenize insulation system 130 and fin structure 120a and 120b.Such as nitriding process N all sidedly nitrogenize insulation system 130 and fin structure 120a and 120b, will comprise also that then nitrogenous layer 150a is arranged in fin structure 120a and 120b.
As shown in Figure 9, carry out epitaxy technique E2, to form epitaxial loayer 140a and 140b in the side of grid structure 160, distinguish cover part fin structure 120a and 120b, and be positioned on the nitrogenous layer 150.That is the fin structure 120a and the 120b surface that are not covered by grid structure 160 all can form respectively epitaxial loayer 140a and 140b, epitaxial loayer 140a and 140b then decide on the electrical of multiple-grid utmost point field-effect transistor (Multi-gate MOSFET), can comprise silicon germanium extension layer or silicon carbon epitaxial layer etc.
Specific, nitrogenous layer 150 formed positions are the contact-making surfaces close to epitaxial loayer 140a and 140b and insulation system 130.Thus, be doped into after the nitrogen-atoms, epitaxial loayer 140a and 140b and insulation system 130 just can not produce the rejection of 54.8 ° of described angle of approach as is known, and can increase the contact area of epitaxial loayer 140a and 140b and insulation system 130, the cumulative volume that increase epitaxial loayer 140a and 140b are grown, thereby increase the surface area that is covered in the metal silicide (not illustrating) on epitaxial loayer 140a and the 140b.Moreover, because epitaxial loayer 140a of the present invention and 140b and insulation system 130 can fit tightly, thereby can impel easier epitaxial loayer 140a and 140b and insulation system 130 surfaces of conformably being covered in fully of the metal levels such as titanium (Ti), cobalt (Co), nickel (Ni) of follow-up formation to carry out self-aligning metal silicide technology.
In addition, present embodiment is after forming grid structure 160, carries out nitriding process N to form nitrogenous layer 150.In another embodiment, also can forming insulation system 130 (shown in Fig. 5 or Fig. 6 B) afterwards, namely carry out nitriding process N as shown in figure 10, in insulation system 130 and fin structure 120a and 120b, to form nitrogenous layer 150 ' comprehensively.In other words, the present invention also can be before forming grid structure 160, prior to forming nitrogenous layer 150 ' among insulation system 130 and fin structure 120a and the 120b.Certainly, nitrogenous layer 150 can be not only with nitriding process N and form, its also can be for example with chemical vapor deposition method (Chemical Vapor Deposition Process, CVD) Direct precipitation one deck nitrogenous layer in insulation system 130 and fin structure 120a and 120b.In addition, nitrogenous layer 150 ' can be formed among insulation system 130 and fin structure 120a and the 120b all sidedly, perhaps is formed in the insulation system 130 or fin structure 120a and 120b of part.
In sum, the invention provides a kind of semiconductor structure and technique thereof, it forms nitrogenous layer between epitaxial loayer and insulation system (for example oxide layer), make epitaxial loayer and insulation system can not produce as is known rejection, causes epitaxial loayer to produce oblique angle upwards with respect to oxide layer.Therefore, semiconductor structure of the present invention can increase the contact area of epitaxial loayer and insulation system, thereby increases the cumulative volume of formed epitaxial loayer.So, can make the follow-up metal silicide that is formed on the epitaxial loayer be easier to adhere to, and can increase its surface area.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (19)
1. non-flattening semiconductor structure comprises:
Substrate;
At least two fin structures are positioned in this substrate;
At least one insulation system, between these a plurality of fin structures, and this insulation system has nitrogenous layer; And
A plurality of epitaxial loayers, these a plurality of fin structures of difference cover part, and be positioned on this nitrogenous layer.
2. non-flattening semiconductor structure as claimed in claim 1, wherein this substrate comprises silicon base or silicon-on-insulator substrate.
3. non-flattening semiconductor structure as claimed in claim 1 also comprises grid structure, covers the fin structure between these a plurality of epitaxial loayers.
4. non-flattening semiconductor structure as claimed in claim 3, wherein this grid structure also comprises:
Gate dielectric covers this a plurality of fin structures;
Gate electrode covers this gate dielectric;
Cap rock covers this gate electrode; And
Clearance wall is positioned at this gate dielectric, this gate electrode and this cap rock side.
5. non-flattening semiconductor structure as claimed in claim 1, wherein this nitration case comprises silicon nitride layer or silicon oxynitride layer.
6. non-flattening semiconductor structure as claimed in claim 1, wherein this nitrogenous layer is also between these a plurality of fin structures and these a plurality of epitaxial loayers.
7. semiconductor technology comprises:
Substrate is provided;
Form at least two fin structures in this substrate;
Form oxide layer between these a plurality of fin structures;
Form nitrogenous layer, in this oxide layer; And
Carry out epitaxy technique, to form these a plurality of fin structures of a plurality of epitaxial loayers cover part.
8. semiconductor technology as claimed in claim 7, wherein this substrate comprises silicon base or silicon-on-insulator substrate.
9. semiconductor technology as claimed in claim 8 wherein forms the step of these a plurality of fin structures on this silicon base, comprising:
Form mask layer on this silicon base;
This mask layer of patterning also utilizes this this substrate of mask layer etching of patterning, to form these a plurality of fin structures.
10. semiconductor technology as claimed in claim 9, wherein this mask layer comprises pad oxide and nitration case.
11. semiconductor technology as claimed in claim 8, wherein this silicon-on-insulator substrate comprises:
Substrate;
Bottom oxide is positioned in this substrate; And
Silicon layer is positioned on this bottom oxide.
12. semiconductor technology as claimed in claim 11 wherein forms these a plurality of fin structures in this silicon-on-insulator substrate and form the step of this oxide layer between these a plurality of fin structures, comprising:
This silicon layer of patterning to be forming this a plurality of fin structures, and exposes partly this bottom oxide, between these a plurality of fin structures.
13. semiconductor technology as claimed in claim 7 wherein forms this nitrogenous layer and comprises and carry out nitriding process, the surface of this oxide layer of Direct-Nitridation is to form this nitrogenous layer in this oxide layer.
14. semiconductor technology as claimed in claim 13, wherein this nitriding process comprises the deionization plasma nitridation process, contains annealing process, remote plasma nitriding process or the hot nitriding process of ammonia.
15. semiconductor technology as claimed in claim 13 wherein after carrying out this nitriding process, also comprises and carries out rear nitrogenize annealing process.
16. semiconductor technology as claimed in claim 15 wherein should comprise the annealing process that contains ammonia by rear nitrogenize annealing process.
17. semiconductor technology as claimed in claim 7, wherein this nitrogenous layer comprises and is formed between this oxide layer and this epitaxial loayer and is formed between this epitaxial loayer and these a plurality of fin structures.
18. semiconductor technology as claimed in claim 7 after forming this oxide layer, also comprises:
Form grid structure on this oxide layer of part and these a plurality of fin structures of part, and these a plurality of epitaxial loayers are positioned at the side of this grid structure.
19. semiconductor technology as claimed in claim 7 after forming this nitration case, also comprises:
Form grid structure on this oxide layer of part and these a plurality of fin structures of part, and these a plurality of epitaxial loayers are positioned at the side of this grid structure.
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| CN104882379A (en) * | 2014-02-28 | 2015-09-02 | 中芯国际集成电路制造(上海)有限公司 | FinFET device and manufacturing method thereof |
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| CN105097530A (en) * | 2014-05-08 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and manufacture method thereof |
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