CN103000687B - Non-flattening semiconductor structure and its technique - Google Patents
Non-flattening semiconductor structure and its technique Download PDFInfo
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- CN103000687B CN103000687B CN201110270877.9A CN201110270877A CN103000687B CN 103000687 B CN103000687 B CN 103000687B CN 201110270877 A CN201110270877 A CN 201110270877A CN 103000687 B CN103000687 B CN 103000687B
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Abstract
The present invention discloses a kind of non-flattening semiconductor structure and its technique, and the non-flattening semiconductor structure includes substrate, at least two fin structures, at least an insulation system and multiple epitaxial layers.Fin structure is located in substrate.Insulation system is located between fin structure, and insulation system has nitrogenous layer.Epitaxial layer is covered each by part fin structure, and on nitrogenous layer.
Description
Technical field
The present invention relates to a kind of semiconductor structure and its technique, more particularly to a kind of connecing in insulation system and epitaxial layer
The semiconductor structure and its technique of nitrogenous layer are formed in contacting surface.
Background technology
With the diminution of semiconductor element size, the efficiency for maintaining small size semiconductor element is the main mesh of current industry
Mark.In order to improve the efficiency of semiconductor element, various fin-shaped field-effect transistor element (Fin-shaped have gradually been developed at present
Field effect transistor, FinFET).Fin-shaped field-effect transistor element includes following items advantage.First, fin-shaped
The technique of field effect transistor element can with traditional logic element process integration, therefore with suitable process compatibility；Secondly,
The contact area of grid and substrate is increased due to the three-dimensional shape of fin structure, therefore grid can be increased for channel region electricity
The control of lotus, so that the energy band for reducing the drain electrode initiation that small-sized component is brought reduces (Drain Induced Barrier
Lowering, DIBL) effect and short-channel effect (short channel effect)；Further, since the grid of same length
Have bigger channel width, therefore can also increase the magnitude of current between source electrode and drain electrode.
Known fin-shaped field-effect transistor element still has development space.For example, outer in general fin-shaped field-effect transistor element
Prolong fin structure of the layer cladding as source/drain region, to increase the cumulative volume of source/drain region, its epitaxial layers is selectively heavy
While accumulating and coat fin structure surface, its lower surface can be in contact with the insulation system of lower section.However, due to epitaxial layer with
Difference of the insulation system on material, the two can it is mutually exclusive and make epitaxial layer produce intimate 54.8 ° crystal plane angle of departure
Degree, causes the two to fit；In other words, because epitaxial layer meeting opposing insulation structure is grown up with oblique angle, thus limitation
The cumulative volume that outer layer growth goes out.Furthermore, it is attached to it that this structure also can be difficult follow-up metal silicide.
Therefore, the present invention is improved for known fin-shaped field-effect transistor element, with the effect of further lift elements
Energy.
The content of the invention
The present invention proposes a kind of semiconductor structure and its technique, and it forms on contact surface of the insulation system with epitaxial layer and contains
Nitrogen layer, thus the contact area of epitaxial layer and insulation system can be increased, and then increase the cumulative volume of epitaxial layer and make metal silication
Thing is easily formed on epitaxial layer.
The present invention provides a kind of semiconductor structure, including substrate, at least two fin structures, an at least insulation system and many
Individual epitaxial layer.Fin structure is located in substrate.Insulation system is located between fin structure, and insulation system has nitrogenous layer.Outward
Prolong layer and be covered each by part fin structure, and on nitrogenous layer.
The present invention provides a kind of semiconductor technology, comprises the steps.First, there is provided substrate.Then, at least two fins are formed
Shape structure is in substrate.Then, formation oxide layer is between fin structure.Afterwards, nitrogenous layer is formed, in oxide layer.Then,
Epitaxy technique is carried out, to form multiple epitaxial layer covering part fin structures.
Based on above-mentioned, the present invention provides a kind of semiconductor structure and its technique, and it is in epitaxial layer and insulation system (such as oxygen
Change layer) between form nitrogenous layer, make to be produced because mutually exclusive between epitaxial layer and insulation system epitaxial layer relative to oxygen
Change the angle of layer.Therefore, semiconductor structure of the invention can increase the contact area of epitaxial layer and oxide layer, thus increase institute shape
Into epitaxial layer cumulative volume.In this way, can make to be subsequently formed that attachment is easier in the metal silicide on epitaxial layer, and can increase
Its surface area.
Brief description of the drawings
Fig. 1 illustrates the generalized section of the semiconductor structure containing silicon base of the embodiment of the present invention.
Fig. 2 illustrates the generalized section of the semiconductor structure containing silicon-on-insulator substrate of another embodiment of the present invention.
Fig. 3-9 illustrates the generalized section of the semiconductor technology of the embodiment of the present invention.
Figure 10 illustrates the generalized section of the semiconductor technology of another embodiment of the present invention.
Description of reference numerals
100a、100b：Semiconductor structure 110,212：Substrate
120a、120b、220a、220b：Fin structure
122：Pad oxide 124：Nitration case
130：Insulation system 140a, 140b：Epitaxial layer
150、150a、150’：Nitrogenous layer 160：Grid structure
162：Gate dielectric 164：Gate electrode
166：Cap rock 168：Clearance wall
210：Silicon-on-insulator substrate 214：Bottom oxide
216：Silicon layer E1：Etching photoetching process
E2：Epitaxy technique N：Nitriding process
Specific embodiment
Fig. 1 illustrates the generalized section of the semiconductor structure containing silicon base of the embodiment of the present invention.Fig. 2 illustrates of the invention another
The generalized section of the semiconductor structure containing silicon-on-insulator substrate of one embodiment.Refer to Fig. 1-2, semiconductor structure 100a
And 100b all includes substrate 110, two fin structure 120a and 120b, insulation system 130 and two epitaxial layer 140a and 140b.Fin
Shape structure 120a and 120b are located in substrate 110.Insulation system 130 is located between fin structure 120a and 120b.Insulation system
130 have nitrogenous layer 150.Epitaxial layer 140a and 140b are covered each by part fin structure 120a and 120b, and positioned at nitrogenous layer
On 150.Fig. 1-2 only illustrates two fin structure 120a and 120b, but general semiconductor structure 100a and 100b may include more
Fin structure, and insulation system 130 is then located between each fin structure.Certainly, multiple epitaxial layers will are covered each by these fins
Shape structure.Furthermore, in the embodiment of Fig. 1-2, semiconductor structure 100a and 100b can refer to fin-shaped field-effect transistor (Fin
Field-effect transistor) or three gate field effect transistors (Tri-gate MOSFET).Such as it is fin-shaped field-effect crystal
Pipe, the two side of fin structure 120a or 120b is then as the grid groove of semiconductor structure 100a or 100b, therefore semiconductor
Structure 100a or 100b have bigrid raceway groove.Such as be three gate field effect transistors, the top surface of fin structure 120a or 120b and
Two side is then as the grid groove of semiconductor structure 100a or 100b, therefore semiconductor structure 100a or 100b have three grids
Raceway groove.
Specifically, substrate 110 may include silicon base or silicon-on-insulator substrate etc., but the present invention is not limited.Such as
Shown in Fig. 1, so that substrate 110 is as silicon base as an example.Two fin structure 120a and 120b directly extend from substrate 110, wherein two
Fin structure 120a and 120b are usually hard mask to be covered in substrate 110 and is carried out Lithography Etching using hard mask and is obtained, but
The present invention is not limited.Insulation system 130 is then located between fin structure 120a and 120b.Insulation system 130 may be, for example,
Oxide layer, it for example can be formed with known shallow ridges groove isolation technique.In the present embodiment, insulation system 130 has nitrogenous layer
150, it for example can be obtained with the surface of Direct-Nitridation insulation system 130 or Direct precipitation nitration case on insulation system 130, because
This nitrogenous layer 150 potentially includes silicon nitride layer or silicon oxynitride layer, depending on actual demand and process.In addition, according to nitrogen
The difference of chemical industry skill, nitrogenous layer 150a also can also include being located at fin structure 120a and 120b and epitaxial layer 140a and 140b it
Between.Epitaxial layer 140a and 140b are then covered each by part fin structure 120a and 120b, and on nitrogenous layer 150.
Particularly, the position set by nitrogenous layer 150 is close to epitaxial layer 140a and 140b and insulation system 130
Contact surface.Consequently, it is possible to be doped into after nitrogen-atoms, epitaxial layer 140a and 140b and insulation system 130 would not be produced as
Know the rejection of 54.8 ° described of angle of approach, and the superficial growth of the nitrogenous layer 150 can be attached, and then extension can be increased
The contact area of layer 140a and 140b and insulation system 130, the cumulative volume for being grown increase epitaxial layer 140a and 140b, because
And increase the surface area of the metal silicide (not illustrating) being covered on epitaxial layer 140a and 140b.Furthermore, due to of the invention
Epitaxial layer 140a and 140b and insulation system 130 can more be brought into close contact, thus can promote to be subsequently formed titanium (Ti), cobalt (Co),
The metal levels such as nickel (Ni) are easily conformably completely covered by epitaxial layer 140a and 140b and the surface of insulation system 130 to carry out certainly
Alignment metal silicide (Salicide) technique.
Additionally, semiconductor structure 100a can again include grid structure 160, the fin between each epitaxial layer 140a and 140b is covered
Shape structure 120a and 120b.Specifically, grid structure 160 may include gate dielectric 162, gate electrode 164, cap rock 166
And clearance wall 168.The covering fin structure of gate dielectric 162 120a and 120b.Gate electrode 164 covers gate dielectric 162.
Cap rock 166 covers gate electrode 164.Clearance wall 168 is located at gate dielectric 162, gate electrode 164 and the side of cap rock 166.Such as
For this structure, epitaxial layer 140a and 140b then respectively with the epitaxial layer (not illustrating) relative to the another side of grid structure 160,
As source/drain pair.In this way, fin-shaped field-effect transistor or three gate field effect transistors (Tri-gate MOSFET) just can be formed
Deng multi-gate field-effect transistor (Multi-gate MOSFET).Certainly, other elements can be also set again in this semiconductor structure
On 100a.Additionally, the gate electrode 164 in grid structure 160 can be metal gate electrode or polysilicon gate electrodes.Such as it is many
Polysilicon gate electrode, it can be replaced in subsequent technique with metal gates, and wherein subsequent technique may be, for example, post tensioned unbonded prestressed concrete (Gate
Last) technique.Post tensioned unbonded prestressed concrete technique may include post tensioned unbonded prestressed concrete (the Gate last for high-k of preposition high-k again
First) post tensioned unbonded prestressed concrete (Gate last for high-k last) technique of technique or rearmounted high-k.Detailed process is walked
Suddenly for persons skilled in the art are known therefore repeat no more.
In addition, as shown in Fig. 2 so that substrate 110 is silicon-on-insulator substrate as an example.What it to be reached is functionally similar to figure
Embodiment shown in 1.Its insulation system 130 is directly formed one layer, such as oxide layer, in substrate 110.Therefore, fin-shaped knot
Structure 120a and 120b are then formed on insulation system 130, rather than as shown in figure 1, are extended by substrate 110.However, due to Fig. 2
Embodiment of structure of the embodiment above insulation system 130 and fin structure 120a and 120b still to Fig. 1 it is similar, therefore also may be used
Reach the function of Fig. 1 embodiments, it is of the invention then repeat no more.
Semiconductor technology presented below, is used to form above-mentioned semiconductor structure.Fig. 3-9 illustrates the half of the embodiment of the present invention
The generalized section of semiconductor process.Figure 10 illustrates the generalized section of the semiconductor technology of another embodiment of the present invention.
First, by taking silicon base as an example.As shown in Figure 3, there is provided substrate 110.Mask layer (not illustrating) is formed in substrate 110
On, wherein mask layer includes that pad oxide (not illustrating) and nitration case (not illustrating) are located on pad oxide.It is etched light
Carving technology E1, patterned mask layer to form the pad oxide 122 of patterning and the nitration case 124 of patterning, and exposes portion
The substrate 110 divided.Then, as shown in figure 4, the pattern of pad oxide 122 and nitration case 124 is transferred to substrate 110 to be formed
Two fin structure 120a and 120b.In the present embodiment, two fin structure 120a and 120b are being formed.Then, as shown in figure 5, sharp
With deposition, planarization and the technique such as etch-back, form insulation system 130, such as oxide layer, fin structure 120a and 120b it
Between, wherein insulation system 130 can be formed for example with shallow trench isolation structure.In this way, can then form two fin structure 120a and 120b
In in substrate 110 and formed insulation system 130 between fin structure 120a and 120b.Afterwards, can by pad oxide 122 and
Nitration case 124 is removed, and makes to form three gate field effect transistors in subsequent technique.In other embodiments, pad can also be left
Oxide layer 122 and nitration case 124, and fin-shaped field-effect transistor structure is formed in subsequent technique.
Or, Fig. 6 A-6B are referred to, Fig. 6 A-6B are another implementation example of the present embodiment.First, as shown in Figure 6A, with
As a example by silicon-on-insulator substrate, there is provided silicon-on-insulator substrate 210, it includes that substrate 212, bottom oxide 214 are located at substrate 212
On, and silicon layer 216 is on bottom oxide 214.Then, as shown in Figure 6B, silicon layer 216 is patterned to form fin structure
220a and 220b, and part bottom oxide 214 is exposed, between fin structure 220a and 220b.Consequently, it is possible to can also be formed
Two fin structure 220a and 220b in substrate 212 and form insulation system (bottom oxide 214) in fin structure 220a and
Between 220b.As shown in figure 1, be only located between fin structure 120a and 120b with the insulation system 130 that silicon base is formed, and
As shown in Figure 6B, the bottom oxide 214 for being formed with silicon-on-insulator substrate 210 then can be also located at immediately below fin structure 220.
However, the difference both this, has no effect on the follow-up semiconductor technology of the present invention.
Then, as shown in fig. 7, grid structure 160 can be formed in SI semi-insulation structure 130 and part fin structure 120a and
On 120b.The technique for forming grid structure 160 may include that deposited in sequential is patterned again, and form gate dielectric 162 in part
On insulation system 130 and part fin structure 120a and 120b, gate electrode 164 on gate dielectric 162, cap rock 166 in
On gate electrode 164 and clearance wall 168 is in the side of gate dielectric 162, gate electrode 164 and cap rock 166, and these materials
The forming method of the bed of material is well known to one of ordinary skill in the art, therefore is repeated no more.
As shown in figure 8, formation nitrogenous layer 150 is in insulation system 130.In the present embodiment, nitriding process N is carried out direct
Nitridation insulation system 130, to form nitrogenous layer 150 in insulation system 130.But in other embodiments, also can deposit to be formed
Nitrogenous layer is on insulation system 130.In embodiment, nitriding process N may include deionization plasma nitridation process, containing ammonia
Annealing process, remote plasma nitriding process or tropical resources technique, but the present invention is not limited.Show in preferred implementation
Under example, after nitriding process N is carried out, can also include nitrogenizing annealing process after carrying out, wherein nitridation annealing process can be such as afterwards
Including the annealing process containing ammonia etc..According to the method for different formation nitrogenous layers 150, the material of the nitrogenous layer 150 for being formed
Potentially include silicon nitride layer or silicon oxynitride layer etc..In addition, nitriding process N can comprehensively or partly nitrogenize insulation system 130
And fin structure 120a and 120b.As nitriding process N comprehensively nitrogenizes insulation system 130 and fin structure 120a and 120b, then
To also include that nitrogenous layer 150a is located in fin structure 120a and 120b.
As shown in figure 9, epitaxy technique E2 is carried out, to form epitaxial layer 140a and 140b in the side of grid structure 160, point
Other covering part fin structure 120a and 120b, and on nitrogenous layer 150.That is, the fin-shaped not covered by grid structure 160
Structure 120a and 120b surfaces can respectively form epitaxial layer 140a and 140b, and epitaxial layer 140a and 140b then regard multi-gate
Effect transistor (Multi-gate MOSFET) it is electrical depending on, it may include silicon germanium extension layer or silicon carbon epitaxial layer etc..
Particularly, the position that nitrogenous layer 150 is formed is close to epitaxial layer 140a and 140b and insulation system 130
Contact surface.Consequently, it is possible to be doped into after nitrogen-atoms, epitaxial layer 140a and 140b and insulation system 130 would not be produced as
The rejection of 54.8 ° described of the angle of approach known, and the contact of epitaxial layer 140a and 140b and insulation system 130 can be increased
Area, the cumulative volume for being grown increase epitaxial layer 140a and 140b, thus increase are covered on epitaxial layer 140a and 140b
Metal silicide (not illustrating) surface area.Furthermore, because epitaxial layer 140a and 140b of the invention and insulation system 130 can
It is brought into close contact, thus the metal levels such as the titanium (Ti) being subsequently formed, cobalt (Co), nickel (Ni) can be promoted easily conformably to be completely covered
In epitaxial layer 140a and 140b and the surface of insulation system 130 carrying out self-aligning metal silicide technology.
In addition, the present embodiment is after grid structure 160 is formed, carry out nitriding process N to form nitrogenous layer 150.
In another embodiment, also can be as shown in Figure 10, after insulation system 130 (as shown in Fig. 5 or Fig. 6 B) is formed, i.e., comprehensively
Nitriding process N is carried out, to form nitrogenous layer 150 ' in insulation system 130 and fin structure 120a and 120b.In other words, this hair
It is bright also can formed grid structure 160 before, prior to forming nitrogenous layer in insulation system 130 and fin structure 120a and 120b
150’.Certainly, nitrogenous layer 150 can be not only and be formed with nitriding process N, and it also can for example with chemical vapor deposition method
(Chemical Vapor Deposition Process, CVD) one layer of nitrogenous layer of Direct precipitation is in insulation system 130 and fin-shaped
In structure 120a and 120b.Additionally, nitrogenous layer 150 ' can comprehensively be formed at insulation system 130 and fin structure 120a and 120b
In, or be formed in the insulation system 130 of part or fin structure 120a and 120b.
In sum, the present invention provides a kind of semiconductor structure and its technique, and it is in epitaxial layer and insulation system (such as oxygen
Change layer) between form nitrogenous layer, epitaxial layer and insulation system is not produced rejection as is known, cause epitaxial layer relative
Upward oblique angle is produced in oxide layer.Therefore, semiconductor structure of the invention can increase the contact surface of epitaxial layer and insulation system
Product, thus increase the cumulative volume of formed epitaxial layer.In this way, can make to be subsequently formed relatively holding in the metal silicide on epitaxial layer
Easily attachment, and its surface area can be increased.
The foregoing is only the preferred embodiments of the present invention, all equivalent variations done according to the claims in the present invention with repair
Decorations, should all belong to covering scope of the invention.
Claims (19)
1. a kind of non-flattening semiconductor structure, including：
Substrate；
Multiple fin structures, in the substrate；
An at least insulation system, between the plurality of fin structure, and the insulation system has a nitrogenous layer, and wherein this is nitrogenous
Layer is only located at a top surface of the insulation system；And
Multiple epitaxial layers, are covered each by the plurality of fin structure in part, and on the nitrogenous layer.
2. non-flattening semiconductor structure as claimed in claim 1, the wherein substrate include silicon base or silicon-on-insulator base
Bottom.
3. non-flattening semiconductor structure as claimed in claim 1, also including grid structure, covers between the plurality of epitaxial layer
Fin structure.
4. non-flattening semiconductor structure as claimed in claim 3, wherein grid structure also includes：
Gate dielectric, covers the plurality of fin structure；
Gate electrode, covers the gate dielectric；
Cap rock, covers the gate electrode；And
Clearance wall, positioned at the gate dielectric, the gate electrode and the cap rock side.
5. non-flattening semiconductor structure as claimed in claim 1, the wherein nitrogenous layer include silicon nitride layer or silicon oxynitride
Layer.
6. non-flattening semiconductor structure as claimed in claim 1, the wherein nitrogenous layer be also located at the plurality of fin structure and
Between the plurality of epitaxial layer.
7. a kind of semiconductor technology, including：
Substrate is provided；
Multiple fin structures are formed in the substrate；
Formation oxide layer is between the plurality of fin structure；
Nitrogenous layer is formed, in the top surface of the oxide layer；And
Epitaxy technique is carried out, to form multiple the plurality of fin structures of epitaxial layer covering part.
8. semiconductor technology as claimed in claim 7, the wherein substrate include silicon base or silicon-on-insulator substrate.
9. semiconductor technology as claimed in claim 8, wherein forming the plurality of fin structure in the step in the silicon base, wraps
Include：
Mask layer is formed in the silicon base；
Pattern the mask layer and the mask layer using patterning etches the substrate, to form the plurality of fin structure.
10. semiconductor technology as claimed in claim 9, the wherein mask layer include pad oxide and nitration case.
11. semiconductor technologies as claimed in claim 8, wherein the silicon-on-insulator substrate, including：
Substrate；
Bottom oxide, in the substrate；And
Silicon layer, on the bottom oxide.
12. semiconductor technologies as claimed in claim 11, wherein forming the plurality of fin structure in the silicon-on-insulator substrate
The step of going up and form the oxide layer between the plurality of fin structure, including：
The silicon layer is patterned to form the plurality of fin structure, and exposes the part bottom oxide, in the plurality of fin structure
Between.
13. semiconductor technologies as claimed in claim 7, wherein form the nitrogenous layer to include carrying out nitriding process, Direct-Nitridation
The surface of the oxide layer, to form the nitrogenous layer in the oxide layer.
14. semiconductor technologies as claimed in claim 13, the wherein nitriding process include deionization plasma nitridation process,
Annealing process containing ammonia, remote plasma nitriding process or tropical resources technique.
15. semiconductor technologies as claimed in claim 13, wherein after the nitriding process is carried out, also including carrying out after nitrogenize
Annealing process.
16. semiconductor technologies as claimed in claim 15, the wherein rear nitridation annealing process include the annealing process containing ammonia.
17. semiconductor technologies as claimed in claim 7, the wherein nitrogenous layer include being formed at the oxide layer and the epitaxial layer it
Between and be formed between the epitaxial layer and the plurality of fin structure.
18. semiconductor technologies as claimed in claim 7, after the oxide layer is formed, also include：
Formed grid structure in part the oxide layer and the plurality of fin structure in part on, and the plurality of epitaxial layer be located at the grid
The side of structure.
19. semiconductor technologies as claimed in claim 7, after the nitrogenous layer is formed, also include：
Formed grid structure in part the oxide layer and the plurality of fin structure in part on, and the plurality of epitaxial layer be located at the grid
The side of structure.
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| US9711645B2 (en) * | 2013-12-26 | 2017-07-18 | International Business Machines Corporation | Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment |
| CN104882379B (en) * | 2014-02-28 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET and its manufacturing method |
| CN105097530A (en) * | 2014-05-08 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and manufacture method thereof |
| CN105304490B (en) * | 2014-07-23 | 2020-09-15 | 联华电子股份有限公司 | Method for manufacturing semiconductor structure |
| US9865595B1 (en) * | 2016-12-14 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same |
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| US7314787B2 (en) * | 2004-03-10 | 2008-01-01 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
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