CN102999466A

CN102999466A - Simply-realized crystal-oscillation-free circuit of USB (Universal Serial Bus) 1.1 device interface

Info

Publication number: CN102999466A
Application number: CN2012104856445A
Authority: CN
Inventors: 不公告发明人
Original assignee: CHENGDU RUICHENG XINWEI TECHNOLOGY Co Ltd
Current assignee: Chengdu Rui core micro Polytron Technologies Inc
Priority date: 2012-11-26
Filing date: 2012-11-26
Publication date: 2013-03-27
Anticipated expiration: 2032-11-26
Also published as: CN102999466B

Abstract

The invention relates to a simply-realized crystal-oscillation-free circuit of a USB (Universal Serial Bus) 1.1 device interface. The simply-realized crystal-oscillation-free circuit comprises a high-frequency oscillator, a sampling clock frequency divider, a USB1.1 data receiver, a USB1.1 data state machine, a USB1.1 built-in clock judgment device and a Delta-Sigma frequency divider, wherein the high-frequency oscillator is used for providing a high-frequency clock, the USB1.1 data receiver is used for receiving effective information sent by a host, the USB1.1 data state machine is used for analyzing characteristic information, then a USB1.1 built-in clock judgment device takes the time span or the time interval of the characteristic information as a reference clock, and dynamically adjusts the frequency demultiplication number of the Delta-Sigma frequency divider through calculation, and finally, a high-precision built-in system clock is produced. When obtaining high performance, the simply-realized crystal-oscillation-free circuit realizes the crystal-oscillation-free technology of the USB 1.1 device interface, and meets the requirement on the low cost of the design of the USB1.1 interface to the maximum extent.

Description

The USB1.1 equipment interface exempt from crystal oscillator simple realization circuit

Technical field

The present invention relates to USB interface and use, the crystal oscillator of exempting from that is specifically related to a kind of USB1.1 of being applied to equipment interface is realized circuit.

Background technology

Along with the progress of technique and technology, it is ripe that the 4th generation of USB series interfaces---USB3.0 technology also is tending towards, but a lot of application, since not high to the data transmission rate requirement, also need to use the USB1.1 interface.The low threshold trend of USB1.1 interface circuit design must be brought the competition of more and more fierce price competition and performance, and its cost cutting has become an important ring of USB1.1 Related product cost cutting.

The USB1.1 equipment interface needs a high-quality crystal oscillator as the input clock source in great majority are used, and produces high-precision system clock.The cost of high-quality crystal oscillator has occupied very large proportion in the holistic cost of USB1.1 equipment interface, in order to reduce significantly its design cost, the crystal oscillator scheme of exempting from of the various USB1.1 of being applied to equipment interfaces is arisen at the historic moment.

The crystal oscillator scheme of exempting from that the USB1.1 equipment interface is existing mainly comprises: reference clock calibration method, external devices calibration method, volume production write calibration method etc.The common defective of these schemes is: along with the variation of external environment condition, system clock can produce very important frequency shift (FS) after frequency calibration, and this will cause the USB1.1 equipment interface to have relatively poor compatibility; Simultaneously, essential testing procedure has also increased testing cost, is unfavorable for the reduction of holistic cost.

Summary of the invention

The objective of the invention is, what a kind of USB1.1 of being applied to equipment interface was provided exempts from crystal oscillator simple realization circuit.This circuit can be saved external crystal-controlled oscillation for the USB1.1 equipment interface, can satisfy typical performance requirement simultaneously, and implementation method is very simple, has farthest reduced design cost.

The technical solution used in the present invention is, a kind of USB1.1 of being applied to equipment interface exempt from crystal oscillator simple realization circuit, it is characterized in that: the described crystal oscillator simple realization circuit of exempting from comprises a high frequency oscillator, a sampling clock frequency divider, a USB1.1 data sink, a USB1.1 data mode machine, the built-in clock decision device of a USB1.1, a Delta_Sigma frequency divider.

One 1A output terminal of described high frequency oscillator links to each other with a 2A input end of described sampling clock frequency divider; One 2B input end of described sampling clock frequency divider links to each other with USB1.1 mode control signal SPEED, and a 2C output terminal of described sampling clock frequency divider links to each other with a 5A input end of a 4A input end of described USB1.1 data mode machine and the built-in clock decision device of described USB1.1; One 3A input end of described USB1.1 data sink links to each other with data bus DP signal, one 3B input end of described USB1.1 data sink links to each other with data bus DM signal, one 3C output terminal of described USB1.1 data sink links to each other with a 4D input end of described USB1.1 data mode machine, one 3D output terminal of described USB1.1 data sink links to each other with a 4C input end of described USB1.1 data mode machine, and a 3E output terminal of described USB1.1 data sink links to each other with a 4B input end of described USB1.1 data mode machine; One 4E input end of described USB1.1 data mode machine links to each other with a 5B input end of the built-in clock decision device of described USB1.1; One 5C output terminal of the built-in clock decision device of described USB1.1 links to each other with a 6C input end of described Delta_Sigma frequency divider; One 6B output terminal of described Delta_Sigma frequency divider is system clock CLK_SYS.

The invention provides a kind of easy USB1.1 equipment interface and exempt from crystal oscillator realization circuit.Compare with conventional art, the present invention is when obtaining superior performance, realized the crystal oscillator technology of exempting from of USB1.1 equipment interface with the cost of economizing as far as possible, farthest satisfied in the USB1.1 Interface design for demand cheaply, USB interface exempt from have revolutionary breakthrough in the crystal oscillator design field.

Description of drawings

Fig. 1 is the structured flowchart that the present invention exempts from crystal oscillator simple realization circuit.

Among Fig. 1: 1. high frequency oscillator; 2. sampling clock frequency divider; 3.USB1.1 data sink; 4.USB1.1 data mode machine; 5. the built-in clock decision device of USB1.1; 6. Delta_Sigma frequency divider.

Embodiment

The present invention is further elaborated below in conjunction with the drawings and specific embodiments.

See Fig. 1, the crystal oscillator simple realization circuit of exempting among the present invention comprises: high frequency oscillator (1), sampling clock frequency divider (2), USB1.1 data sink (3), USB1.1 data mode machine (4), the built-in clock decision device of USB1.1 (5) and Delta_Sigma frequency divider (6).

The 1A output terminal of high frequency oscillator (1) links to each other with the 2A input end of sampling clock frequency divider (2); The 2B input end of sampling clock frequency divider (2) links to each other with USB1.1 mode control signal SPEED, and the 2C output terminal of described sampling clock frequency divider (2) links to each other with the 4A input end of USB1.1 data mode machine (4) and the 5A input end of the built-in clock decision device of USB1.1 (5); The 3A input end of USB1.1 data sink (3) links to each other with data bus DP signal, the 3B input end of USB1.1 data sink (3) links to each other with data bus DM signal, the 3C output terminal of USB1.1 data sink (3) links to each other with the 4D input end of USB1.1 data mode machine (4), the 3D output terminal of USB1.1 data sink (3) links to each other with the 4C input end of USB1.1 data mode machine (4), and the 3E output terminal of USB1.1 data sink (3) links to each other with the 4B input end of USB1.1 data mode machine (4); The 4E input end of USB1.1 data mode machine (4) links to each other with the 5B input end of the built-in clock decision device of USB1.1 (5); The 5C output terminal of the built-in clock decision device of USB1.1 (5) links to each other with the 6C input end of Delta_Sigma frequency divider (6); The 6B output terminal of Delta_Sigma frequency divider (6) is system clock CLK_SYS.

High frequency oscillator (1) in the present invention role is: a high frequency clock signal is provided, this signal is via producing system clock CLK_SYS behind the Delta_Sigma frequency divider (6), this clock has higher precision under the dynamic calibration pattern, can satisfy the USB1.1 equipment interface for the demand of clock accuracy.On the other hand, the high frequency clock signal that high frequency oscillator (1) generates is sent into sampling clock frequency divider (2), for the subsequent dynamic calibration process provides sampling clock.Exempt from the crystal oscillator design for the requirement of system clock precision in order to satisfy, the output clock frequency of high frequency oscillator (1) generally is designed to more than the 250MHz.

Sampling clock frequency divider (2) is distinguished the mode of operation of USB1.1 equipment interface, when USB1.1 equipment uses as low-speed device, mode control signal SPEED is low level, the high frequency clock that sampling clock frequency divider (2) is sent into high frequency oscillator (1) carries out 8 frequency divisions, then as the sampling clock of USB1.1 data mode machine (4) and the judgement clock of the built-in clock decision device of USB1.1 (5); When USB1.1 equipment uses as full speed equipment, mode control signal SPEED is high level, and the high frequency clock that high frequency oscillator (1) produces is directly as the sampling clock of USB1.1 data mode machine (4) and the judgement clock of the built-in clock decision device of USB1.1 (5).

USB1.1 data sink (3) generally comprises a USB1.1 differential data receiver and two single-ended receivers of USB1.1, USB1.1 differential data receiver receives the DP/DM differential signal, obtains differential data that main frame sends as the 3C end of USB1.1 data sink (3); Two single-ended receivers of USB1.1 are the single-ended signal DP and the DM that send of Receiving Host respectively, receive single-ended data respectively as the 3D end and 3E end of USB1.1 data sink (3).Above-mentioned differential data and single-ended data are the valid data information that USB1.1 data mode machine (4) provides main frame to send.

The valid data information that USB1.1 data mode machine (4) is sent here USB1.1 data sink (3) is processed, in the processing procedure, the 2C end of sampling clock frequency divider (2) is sent into signal as sampling clock, parses the characteristic information KEY_WORD that carries in the valid data information and sends into the built-in clock decision device of USB1.1 (5).Effective parsing of KEY_WORD is to exempt from one of key of crystal oscillator technology realization among the present invention, and when USB1.1 equipment used as low-speed device, KEY_WORD was generally packet packet header " JKJKJKJJ "; When USB1.1 equipment used as full speed equipment, KEY_WORD can be packet packet header " KJKJKJKK ", the sync packet key word that also can send for main frame.

The built-in clock decision device of USB1.1 (5) take counting KEY_WORD time span or its interval time length as reference time, judge the frequency separation of judgement clock.When USB1.1 equipment used as low-speed device, KEY_WORD was generally packet packet header " JKJKJKJJ ", and then be the time span of " JKJKJKJJ " reference time.When USB1.1 equipment used as full speed equipment, if KEY_WORD packet packet header " KJKJKJKK ", then be the time span of " KJKJKJKK " reference time; If the sync packet key word that the KEY_WORD main frame sends, then be the time interval of adjacent key word reference time.Because KEY_WORD derives from the data message that main frame sends, therefore its time length or interval time length can be used as and use reference time, the built-in clock decision device of USB1.1 (5) generates the fractional frequency division number by internal arithmetic mechanism and sends into Delta_Sigma frequency divider (6).

Delta_Sigma frequency divider (6) receives the fractional frequency division number that the built-in clock decision device of USB1.1 (5) judgement generates, with this fractional frequency division number the generated clock of high frequency oscillator (1) is carried out frequency division, because it is very high that fractional frequency division is counted precision, so can produce the higher system clock CLK_SYS of precision for the USB1.1 equipment interface.

The dynamic process of exempting from the crystal oscillator realization comprises: the data that USB1.1 data sink (3) Receiving Host sends, USB1.1 data mode machine (4) parses the KEY_WORD of receive data, then the built-in clock decision device of USB1.1 (5) is with KEY_WORD time span or length interval time reference time the most, produce the fractional frequency division number by internal arithmetic and send into Delta_Sigma frequency divider (6), last Delta_Sigma frequency divider (6) carries out corresponding Delta_Sigma fractional frequency division to the generated clock of high frequency oscillator (1).Said process dynamically carries out, and therefore when realizing the High Definition Systems clock, makes clock frequency not be subjected to the interference of environmental factor variation.Owing to exempt from only to use in the crystal oscillator implementation procedure high frequency oscillator, data sink and some Digital Logic, do not use and take the more phase-locked loop circuit of chip area, therefore has low-down design cost, exempting from crystal oscillating circuit with tradition compares, the present invention has realized the crystal oscillator technology of exempting from of superior performance with minimum design cost, has obtained breakthrough in the demand of USB1.1 equipment interface cost cutting.

Claims

One kind be applied to the USB1.1 equipment interface exempt from crystal oscillator simple realization circuit, it is characterized in that: the described crystal oscillator simple realization circuit of exempting from comprises a high frequency oscillator, a sampling clock frequency divider, a USB1.1 data sink, a USB1.1 data mode machine, the built-in clock decision device of a USB1.1, a Delta_Sigma frequency divider.
2. built-in crystal oscillator is realized circuit as described in claim 1, and it is characterized in that: a 1A output terminal of described high frequency oscillator links to each other with a 2A input end of described sampling clock frequency divider; One 2B input end of described sampling clock frequency divider links to each other with USB1.1 mode control signal SPEED, and a 2C output terminal of described sampling clock frequency divider links to each other with a 5A input end of a 4A input end of described USB1.1 data mode machine and the built-in clock decision device of described USB1.1; One 3A input end of described USB1.1 data sink links to each other with data bus DP signal, one 3B input end of described USB1.1 data sink links to each other with data bus DM signal, one 3C output terminal of described USB1.1 data sink links to each other with a 4D input end of described USB1.1 data mode machine, one 3D output terminal of described USB1.1 data sink links to each other with a 4C input end of described USB1.1 data mode machine, and a 3E output terminal of described USB1.1 data sink links to each other with a 4B input end of described USB1.1 data mode machine; One 4E input end of described USB1.1 data mode machine links to each other with a 5B input end of the built-in clock decision device of described USB1.1; One 5C output terminal of the built-in clock decision device of described USB1.1 links to each other with a 6C input end of described Delta_Sigma frequency divider; One 6B output terminal of described Delta_Sigma frequency divider is system clock CLK_SYS.