CN102981995B - The built-in crystal oscillator realizing circuit of USB device interface and method - Google Patents
The built-in crystal oscillator realizing circuit of USB device interface and method Download PDFInfo
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Abstract
A built-in crystal oscillator realizing circuit for USB device interface, described built-in crystal oscillator realizing circuit comprises a high frequency oscillator, a sampling clock frequency divider, a usb data receiver, a usb data state machine, a USB embedded clock decision device, an input clock frequency divider, a low bandwidth phaselocked loop.Described high frequency oscillator provides high frequency clock, the effective information that described usb data receiver Receiving Host sends, characteristic information is parsed by described usb data state machine, then described USB embedded clock decision device with the time span of characteristic information or the time interval for reference clock, by the input clock frequency of low bandwidth phaselocked loop described in computing dynamic conditioning, last described low bandwidth phaselocked loop produces the built-in system clock of high precision low noise.Built-in crystal oscillator realizing circuit provided by the invention possesses low cost and high performance characteristic simultaneously.A built-in crystal oscillator implementation method for USB device interface, can realize the built-in crystal oscillator of USB1.0, USB1.1 and USB2.0 equipment interface, have extremely strong practicality, and the method also has the advantage of environment resistant interference.
Description
Technical field
The present invention relates to USB interface application, be specifically related to a kind of built-in crystal oscillator realizing circuit and the method that are applied to USB device interface.
Background technology
USB interface, because its characteristic such as low cost, two-forty, is applied to field of data transmission more and more widely.But along with the progress of technique and technology, price competition and the performance competitive of USB interface relevant device are more and more fierce, and the cost cutting of USB interface also becomes the important ring in cost of products reduction demand.
In most applications, USB device interface needs a high-quality crystal oscillator as its input clock source, produces high-precision system clock, to ensure USB device and main-machine communication quality.High-quality crystal oscillator due to cost cutting extremely limited, and in the holistic cost of USB device interface, account for very large proportion, therefore in order to reduce its design cost significantly, need in USB device interface, realize built-in crystal oscillator scheme, to save the cost overhead of external crystal-controlled oscillation.
The built-in crystal oscillator scheme of the existing main flow of USB device interface mainly comprises: reference clock calibration method, external devices calibration method, volume production write calibration method etc.The common defect of these schemes is: along with the change of external environment condition after frequency calibration, system clock can produce very important frequency shift (FS), and this has poor compatibility by causing USB device interface; Meanwhile, required testing procedure too increases testing cost, is unfavorable for the reduction of holistic cost.
Along with the price competition of USB interface is more and more fiery, require that its design cost is more and more lower, and performance index can not reduce, the built-in crystal oscillator scheme of existing main flow is no longer satisfied the demand.
Summary of the invention
The object of the invention is, a kind of built-in crystal oscillator realizing circuit and method of USB device interface is provided.This circuit can be that USB1.1 equipment interface and USB2.0 equipment interface save external crystal-controlled oscillation, greatly reduces the design cost of USB device interface, can meet high-quality performance requirement simultaneously.
Another object of the present invention is, provides a kind of built-in crystal oscillator implementation method of USB device interface.The method is based on the dynamic clock calibration techniques of one, and the use of this technology achieves the built-in crystal oscillator of USB device interface, and its embedded clock has high precision, can meet the performance requirement of USB device interface for system clock.
The technical solution used in the present invention is, a built-in crystal oscillator realizing circuit for USB device interface, is characterized in that: described built-in crystal oscillator realizing circuit comprises a high frequency oscillator, a sampling clock frequency divider, a usb data receiver, a usb data state machine, a USB embedded clock decision device, an input clock frequency divider, a low bandwidth phaselocked loop.
One 1A output terminal of described high frequency oscillator is connected with a 2A input end of described sampling clock frequency divider; One 2B output terminal of described sampling clock frequency divider is connected with a 5A input end of described USB embedded clock decision device; One 3A input end of described usb data receiver is connected with data bus DP signal, one 3B input end of described usb data receiver is connected with data bus DM signal, one 3C output terminal of described usb data receiver is connected with a 7B output terminal of described low bandwidth phaselocked loop, and a 3D output terminal of described usb data receiver is connected with a 4A input end of described usb data state machine; One 4B input end of described usb data state machine is connected with a 7B output terminal of described low bandwidth phaselocked loop, and a 4C output terminal of described usb data state machine is connected with a 5B input end of described USB embedded clock decision device; One 5C output terminal of described USB embedded clock decision device is connected with a 6C input end of described input clock frequency divider; One 6B output terminal of described input clock frequency divider is connected with a 7A input end of described low bandwidth phaselocked loop; One 7B output terminal of described low bandwidth phaselocked loop is system clock CLK_SYS.
Another technical scheme that the present invention adopts is, a kind of built-in crystal oscillator implementation method of USB device interface, and the method is based on the dynamic clock calibration techniques of one, and its calibration process is implemented according to following steps:
Steps A: system reset terminates;
Step B: described high frequency oscillator produces high frequency clock, described sampling clock frequency divider generates judgement clock and sends into described USB embedded clock decision device, configure the initial divider ratio of described input clock frequency divider, described low bandwidth phaselocked loop generates the system clock CLK_SYS of original frequency;
Step C:USB equipment interface has completed at full speed or high speed handshake procedure, and described usb data receiver starts order bag that Receiving Host sends and packet;
Step D: described usb data state machine parses the characteristic information KEY_WORD carried in receiving package information, sends into described USB embedded clock decision device, and proceeds to step e by KEY_WORD;
Step e: described USB embedded clock decision device is to count KEY_WORD time span or its interval time lengths for reference time, judge the frequency separation of adjudicating clock, union goes out to adjudicate the difference of clock frequency and ideal frequency, if the difference of frequency is within the scope of usb protocol permissible accuracy, then redirect enters step H; If the difference of frequency does not also meet usb protocol permissible accuracy scope, then proceed to step F;
Step F: described USB embedded clock decision device with the input clock of low bandwidth phaselocked loop described in the mode FEEDBACK CONTROL changing input clock divide ratio, and proceeds to step G;
Step G: the change of described low bandwidth phaselocked loop response input clock, generate the system clock CLK_SYS after this calibration after experience loop stability process, redirect enters step D;
Step H: the output system clock CLK_SYS frequency stabilization of described low bandwidth phaselocked loop, and precision meets usb protocol requirement, and dynamic calibration process reaches equilibrium state;
Step I: the change of external environmental factor causes new calibration process to start, and proceeds to step D.
The invention provides a kind of built-in crystal oscillator realizing circuit of the USB device interface based on Dynamic Calibration Technique, this circuit is while saving external crystal-controlled oscillation, and its built-in system generated also meets high-precision performance requirement.Compared with the built-in crystal oscillating circuit of conventional USB device interface, built-in crystal oscillating circuit provided by the invention has lower cost and the performance index of Geng Gao.
Present invention also offers a kind of built-in crystal oscillator implementation method of the USB device interface based on Dynamic Calibration Technique, adopt the method can realize the built-in crystal oscillator of USB1.0, USB1.1 and USB2.0 equipment interface, there is extremely strong practicality; The method of Dynamic Calibration Technique is adopted also to have the advantage of environment resistant interference.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the built-in crystal oscillator realizing circuit of the present invention.
Fig. 2 is the workflow diagram of the built-in crystal oscillator implementation method of the present invention.
In Fig. 1: 1. high frequency oscillator; 2. sampling clock frequency divider; 3. usb data receiver; 4. usb data state machine; 5. USB embedded clock decision device; 6. input clock frequency divider; 7. low bandwidth phaselocked loop.
In Fig. 2: A. system reset terminates; B. the system clock CLK_SYS of original frequency is generated; C. usb data receiver starts Receiving Host transmission bag; D. usb data state machine parses characteristic information KEY_WORD; E. USB embedded clock decision device judges the amount of judgement clock deviation ideal value; F. frequency departure amount is to the FEEDBACK CONTROL of low bandwidth phaselocked loop input clock; G. the system clock CLK_SYS after this calibration is generated; H. dynamic calibration process reaches equilibrium state, produces high-accuracy stable system clock; I. the change of external environmental factor causes new calibration process to start.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is further elaborated.
See Fig. 1, the built-in crystal oscillator realizing circuit in the present invention comprises: high frequency oscillator (1), sampling clock frequency divider (2), usb data receiver (3), usb data state machine (4), USB embedded clock decision device (5), input clock frequency divider (6) and input clock frequency divider (6).
The 1A output terminal of high frequency oscillator (1) is connected with the 2A input end of sampling clock frequency divider (2); The 2B output terminal of sampling clock frequency divider (2) is connected with the 5A input end of USB embedded clock decision device (5); The 3A input end of usb data receiver (3) is connected with data bus DP signal, the 3B input end of usb data receiver (3) is connected with data bus DM signal, the 3C output terminal of usb data receiver (3) is connected with the 7B output terminal of low bandwidth phaselocked loop (7), and the 3D output terminal of usb data receiver (3) is connected with the 4A input end of usb data state machine (4); The 4B input end of usb data state machine (4) is connected with the 7B output terminal of low bandwidth phaselocked loop (7), and the 4C output terminal of usb data state machine (4) is connected with the 5B input end of USB embedded clock decision device (5); The 5C output terminal of USB embedded clock decision device (5) is connected with the 6C input end of input clock frequency divider (6); The 6B output terminal of input clock frequency divider (6) is connected with the 7A input end of low bandwidth phaselocked loop (7); The 7B output terminal of low bandwidth phaselocked loop (7) is system clock CLK_SYS.
High frequency oscillator (1) in the present invention role is: provide a high frequency clock signal, this signal sends into low bandwidth phaselocked loop (7) after input clock frequency divider (6) frequency division, produce system clock CLK_SYS, this clock has high precision under dynamic calibration pattern, can meet the demand of usb protocol for system clock accuracy.On the other hand, the high frequency clock signal that high frequency oscillator (1) generates sends into sampling clock frequency divider (2), for subsequent dynamic calibration process provides sampling clock.Because low bandwidth phaselocked loop (7) is inhibited for the noise of low frequency input clock, therefore the output clock of high frequency oscillator (1) there is no need to be designed to high frequency, input clock frequency divider (6) can carry out fractional frequency division to it, makes low bandwidth phaselocked loop (7) produce the system clock of high precision low noise.Generally the clock frequency of high frequency oscillator (1) is designed to more than 50MHz.
The mode of operation of USB device interface distinguished by sampling clock frequency divider (2), when USB device uses as low-speed device, full-speed device or high-speed equipment, selects each self-corresponding divide ratio, thus generates the judgement clock under corresponding different working modes.
The mode of operation of USB device interface distinguished by usb data receiver (3), when USB device uses as low-speed device or full-speed device, comprise a USB1.1 differential data receiver and two USB1.1 single ended receiver, the differential signal that sends of Receiving Host and single-ended signal respectively, and provide the valid data information that main frame sends for usb data state machine (4); When USB device uses as high-speed equipment, the multiphase clock generated by low bandwidth phaselocked loop carries out high speed to differential data bus DP/DM and receives, simultaneously for usb data state machine (4) provides the valid data information that main frame sends.
Usb data state machine (4) processes the valid data information that usb data receiver (3) is sent here, in processing procedure, usb data state machine (4) parses the characteristic information KEY_WORD that carries in valid data information and sends into USB embedded clock decision device (5).When USB device uses as low-speed device, KEY_WORD is generally packet header " JKJKJKJJ "; When USB device uses as full-speed device, KEY_WORD can be packet header " KJKJKJKK ", the sync packet key word that also can send for main frame; When USB device uses as high-speed equipment, KEY_WORD is the sync packet key word that sends of main frame or other sync packet features.
USB embedded clock decision device (5), to count KEY_WORD time span or its interval time lengths for reference time, judges the bias of the corresponding ideal frequency of frequency of adjudicating clock.When USB device uses as low-speed device, KEY_WORD is generally packet header " JKJKJKJJ ", then reference time is the time span of " JKJKJKJJ "; When USB device uses as full-speed device, if KEY_WORD packet header " KJKJKJKK ", then reference time is the time span of " KJKJKJKK "; If the sync packet key word that KEY_WORD main frame sends, then reference time is the time interval of adjacent key word; When USB device uses as high-speed equipment, KEY_WORD is the sync packet key word that sends of main frame or other sync packet features, then reference time is the time interval of adjacent sync bag key word or other sync packet features.Because KEY_WORD derives from order or data message that main frame sends, therefore its time span or interval time lengths can use as reference time, USB1.1 embedded clock decision device (5) generates fractional frequency division number by internal arithmetic mechanism and sends into input clock frequency divider (6), as the input clock of low bandwidth phaselocked loop (7) after frequency division.
Input clock frequency divider (6) receives the fractional frequency division number that USB embedded clock decision device (5) judgement generates, frequency division is carried out with the generated clock of this fractional frequency division number to high frequency oscillator (1), because fractional frequency division number precision is very high, so the very high input clock of precision can be produced send into low bandwidth phaselocked loop (7).The noise produced for input clock frequency divider (6) due to low bandwidth phaselocked loop (7) is inhibited, therefore can meet the demand of low noise while generating High Definition Systems clock.
Low bandwidth phaselocked loop (7) achieves the function of high precision low frequency clock multiplier tremendously high frequency clock, while frequency multiplication, further suppress the noise of input clock, makes built-in crystal oscillator realizing circuit of the present invention possess the characteristic of high precision and low noise simultaneously.
Built-in crystal oscillator realizing circuit provided by the invention, USB device interface is not only made to save external crystal-controlled oscillation, the embedded clock simultaneously generated possesses the characteristic of high precision and low noise simultaneously, compared with the embedded clock circuit of conventional USB device interface, built-in crystal oscillating circuit provided by the invention has lower cost and the performance index of Geng Gao.
See Fig. 2, the built-in crystal oscillator implementation method that the present invention adopts, the method is based on the built-in crystal oscillator realizing circuit in Fig. 1, and achieve the dynamic calibration mechanism of embedded clock, its calibration process is implemented according to following steps:
Steps A: system reset terminates;
Step B: high frequency oscillator (1) produces high frequency clock, sampling clock frequency divider (2) generates judgement clock CLK_COUNTER and sends into USB embedded clock decision device (5), the initial divider ratio of configuration input clock frequency divider (6), low bandwidth phaselocked loop (7) generates the system clock CLK_SYS of original frequency;
Step C:USB equipment interface has completed at full speed or high speed handshake procedure, the order bag that usb data receiver (3) beginning Receiving Host sends and packet;
Step D:USB data state machine (4) parses the characteristic information KEY_WORD carried in receiving package information, KEY_WORD is sent into USB embedded clock decision device (5), and proceeds to step e;
Step e: USB embedded clock decision device (5) is to count KEY_WORD time span or its interval time lengths for reference time, judge the frequency separation of adjudicating clock CLK_COUNTER, union goes out to adjudicate the difference of clock frequency and ideal frequency, if the difference of frequency is within the scope of usb protocol permissible accuracy, then redirect enters step H; If the difference of frequency does not also meet usb protocol permissible accuracy scope, then proceed to step F;
Step F: USB embedded clock decision device (5) to change the input clock CLK_IN of mode FEEDBACK CONTROL low bandwidth phaselocked loop (7) of input clock divide ratio, and proceeds to step G;
Step G: the change of low bandwidth phaselocked loop (7) response input clock CLK_IN, generate the system clock CLK_SYS after this calibration after experience loop stability process, redirect enters step D;
Step H: the output system clock CLK_SYS frequency stabilization of low bandwidth phaselocked loop (7), and precision meets usb protocol requirement, and dynamic calibration process reaches equilibrium state;
Step I: the change of external environmental factor causes new calibration process to start, and proceeds to step D.
Built-in crystal oscillator implementation method based on Dynamic Calibration Technique provided by the invention, can realize the built-in crystal oscillator of USB1.0, USB1.1 and USB2.0 equipment interface, have extremely strong practicality, adopts the method for Dynamic Calibration Technique also to have the advantage of environment resistant interference.
Claims (2)
1. a built-in crystal oscillator realizing circuit for USB device interface, is characterized in that: described built-in crystal oscillator realizing circuit comprises a high frequency oscillator, a sampling clock frequency divider, a usb data receiver, a usb data state machine, a USB embedded clock decision device, an input clock frequency divider, a low bandwidth phaselocked loop;
The mode of operation of USB device interface distinguished by usb data receiver (3), when USB device uses as low-speed device or full-speed device, comprise a USB1.1 differential data receiver and two USB1.1 single ended receiver, the differential signal that sends of Receiving Host and single-ended signal respectively, and provide the valid data information that main frame sends for usb data state machine (4); When USB device uses as high-speed equipment, the multiphase clock generated by low bandwidth phaselocked loop carries out high speed to differential data bus DP/DM and receives, simultaneously for usb data state machine (4) provides the valid data information that main frame sends;
Usb data state machine (4) processes the valid data information that usb data receiver (3) is sent here, in processing procedure, usb data state machine (4) parses the characteristic information KEY_WORD that carries in valid data information and sends into USB embedded clock decision device (5), when USB device uses as low-speed device, KEY_WORD is packet header " JKJKJKJJ "; When USB device uses as full-speed device, KEY_WORD is the sync packet key word that packet header " KJKJKJKK " or main frame send; When USB device uses as high-speed equipment, KEY_WORD is the sync packet key word that sends of main frame or other sync packet features;
USB embedded clock decision device (5), to count KEY_WORD time span or its interval time lengths for reference time, judges the bias of the corresponding ideal frequency of frequency of adjudicating clock; When USB device uses as low-speed device, KEY_WORD is packet header " JKJKJKJJ ", then reference time is the time span of " JKJKJKJJ "; When USB device uses as full-speed device, if KEY_WORD packet header " KJKJKJKK ", then reference time is the time span of " KJKJKJKK "; If the sync packet key word that KEY_WORD main frame sends, then reference time is the time interval of adjacent key word; When USB device uses as high-speed equipment, KEY_WORD be the sync packet key word that sends of main frame or other sync packet features time, then reference time is the time interval of adjacent sync bag key word or other adjacent sync bag features;
One 1A output terminal of described high frequency oscillator is connected with a 2A input end of described sampling clock frequency divider; One 2B output terminal of described sampling clock frequency divider is connected with a 5A input end of described USB embedded clock decision device; One 3A input end of described usb data receiver is connected with data bus DP signal, one 3B input end of described usb data receiver is connected with data bus DM signal, one 3C output terminal of described usb data receiver is connected with a 7B output terminal of described low bandwidth phaselocked loop, and a 3D output terminal of described usb data receiver is connected with a 4A input end of described usb data state machine; One 4B input end of described usb data state machine is connected with a 7B output terminal of described low bandwidth phaselocked loop, and a 4C output terminal of described usb data state machine is connected with a 5B input end of described USB embedded clock decision device; One 5C output terminal of described USB embedded clock decision device is connected with a 6C input end of described input clock frequency divider; One 6B output terminal of described input clock frequency divider is connected with a 7A input end of described low bandwidth phaselocked loop; One 7B output terminal of described low bandwidth phaselocked loop is system clock CLK_SYS.
2. a built-in crystal oscillator implementation method for USB device interface, is characterized in that:
The method adopts the built-in crystal oscillator realizing circuit structure of a kind of USB device interface as claimed in claim 1, and the method is based on the dynamic clock calibration techniques of one, and its calibration process is implemented according to following steps:
Steps A: system reset terminates;
Step B: described high frequency oscillator produces high frequency clock, described sampling clock frequency divider generates judgement clock and sends into described USB embedded clock decision device, configure the initial divider ratio of described input clock frequency divider, described low bandwidth phaselocked loop generates the system clock CLK_SYS of original frequency;
Step C:USB equipment interface has completed at full speed or high speed handshake procedure, and described usb data receiver starts order bag that Receiving Host sends and packet;
When USB device uses as low-speed device or full-speed device, usb data receiver (3) comprises a USB1.1 differential data receiver and two USB1.1 single ended receiver, the differential signal that sends of Receiving Host and single-ended signal respectively, and provide the valid data information that main frame sends for usb data state machine (4);
When USB device uses as high-speed equipment, the multiphase clock generated by low bandwidth phaselocked loop carries out high speed to differential data bus DP/DM and receives, simultaneously for usb data state machine (4) provides the valid data information that main frame sends;
Step D: described usb data state machine parses the characteristic information KEY_WORD carried in receiving package information, sends into described USB embedded clock decision device, and proceeds to step e by KEY_WORD;
When USB device uses as low-speed device, KEY_WORD is packet header " JKJKJKJJ ";
When USB device uses as full-speed device, KEY_WORD is packet header " KJKJKJKK ", or the sync packet key word that main frame sends;
When USB device uses as high-speed equipment, KEY_WORD is the sync packet key word that sends of main frame or other sync packet features;
Step e: described USB embedded clock decision device is to count KEY_WORD time span or its interval time lengths for reference time, judge the frequency separation of adjudicating clock, union goes out to adjudicate the difference of clock frequency and ideal frequency, if the difference of frequency is within the scope of usb protocol permissible accuracy, then redirect enters step H; If the difference of frequency does not also meet usb protocol permissible accuracy scope, then proceed to step F;
When USB device uses as low-speed device, KEY_WORD is packet header " JKJKJKJJ ", then reference time is the time span of " JKJKJKJJ ";
When USB device uses as full-speed device, if KEY_WORD packet header " KJKJKJKK ", then reference time is the time span of " KJKJKJKK "; If the sync packet key word that KEY_WORD main frame sends, then reference time is the time interval of adjacent key word;
When USB device uses as high-speed equipment, KEY_WORD be the sync packet key word that sends of main frame or other sync packet features time, then reference time is the time interval of adjacent sync bag key word or other adjacent sync bag features;
Step F: described USB embedded clock decision device with the input clock of low bandwidth phaselocked loop described in the mode FEEDBACK CONTROL changing input clock divide ratio, and proceeds to step G;
Step G: the change of described low bandwidth phaselocked loop response input clock, generate the system clock CLK_SYS after this calibration after experience loop stability process, redirect enters step D;
Step H: the output system clock CLK_SYS frequency stabilization of described low bandwidth phaselocked loop, and precision meets usb protocol requirement, and dynamic calibration process reaches equilibrium state;
Step I: the change of external environmental factor causes new calibration process to start, and proceeds to step D.
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Denomination of invention: Circuit and method for realizing built-in crystal oscillator of USB (Universal Serial Bus) equipment port Effective date of registration: 20180702 Granted publication date: 20150916 Pledgee: Agricultural Bank of China Limited by Share Ltd Chengdu Shuangliu Branch Pledgor: Chengdu Rui core micro Polytron Technologies Inc Registration number: 2018510000065 |
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Date of cancellation: 20210811 Granted publication date: 20150916 Pledgee: Agricultural Bank of China Limited by Share Ltd. Chengdu Shuangliu Branch Pledgor: CHENGDU ANALOG CIRCUIT TECHNOLOGY Inc. Registration number: 2018510000065 |