CN102984105B - System and method capable of achieving interference offset and basestation locking based on field programmable gate array (FPGA) - Google Patents

Abstract

The invention discloses a system and method capable of achieving interference offset and scan signal based on a field programmable gate array (FPGA). The output end of a first low noise amplifier is sequentially connected with a first filter, a first lower converter and an analog-digital converter. The output end of a second low noise amplifier is sequentially connected with a second filter and a second lower converter. The output end of the second lower converter is connected with the analog-digital converter. A first output end and a second output end of the analog-digital converter are connected with a second FPGA through a first FPGA. The output end of the second FPGA is respectively connected with a first digital-to-analog converter (DAC), a second DAC and a serial digital analog converter. The output end of the first DAC is sequentially connected with a first intelligent quotient (IQ) modulator, a third filter and a first power amplifier. The output end of the second DAC is sequentially connected with a second IQ modulator, a fourth filter and a second power amplifier. The output end of the serial digital analog converter is connected with a voltage controlled oscillator. The system and method capable of achieving interference offset and scan signal based on FPGA has the advantages of being simple in implementation model, low in cost, compatible with multiple system formats and is widely used in communication industry.

Description

Based on the system and method that the realized Interference Cancellation of FPGA locks with base station

Technical field

The present invention relates to a kind of system and method realizing base station locking, particularly based on the system and method that the realized Interference Cancellation of FPGA locks with base station.

Background technology

In digital radio repeater, amplify all Received signal strength owing to not carrying out to received signal screening simultaneously, can cause occurring pilot pollution, therefore in communication process, need to adopt base station lock-in techniques to carry out base station locking.Uplink and downlink signals is mainly separated disparate modules platform processes by existing scheme, and the repeater of the different systems systems such as corresponding CDMA2000, WCDMA, TD-SCDMA, need to develop different base station lock fixed systems, manufacturing cost is high.

Summary of the invention

In order to solve above-mentioned technical problem, the invention provides a kind of low cost, can the system that locks of the realized Interference Cancellation based on FPGA and the base station of repeater of compatible multiple systems standard.Present invention also offers a kind of low cost, can the method that locks of the realized Interference Cancellation based on FPGA and the base station of repeater of compatible multiple systems standard.

The technical solution adopted for the present invention to solve the technical problems is:

Based on the system that the realized Interference Cancellation of FPGA locks with base station, comprising:

First low noise amplifier, the second low noise amplifier, for cooperative achievement Interference Cancellation and base station locking a FPGA and the 2nd FPGA, the descending input signal of input termination of described first low noise amplifier, the output of described first low noise amplifier is connected with the first filter, the first low-converter and analog to digital converter in turn;

The input of described second low noise amplifier connects row input signal, and the output of described second low noise amplifier is connected with the second filter and the second low-converter in turn, and the output of described second low-converter is connected with analog to digital converter;

First output of described analog to digital converter is all connected with the 2nd FPGA by a FPGA with the second output, and the output of described 2nd FPGA is connected to the first digital to analog converter, the second digital to analog converter and serial digital to analog converter;

The output of described first digital to analog converter is connected with the first I/Q modulator, the 3rd filter and the first amplifirer in turn, the output of described second digital to analog converter is connected with the second I/Q modulator, the 4th filter and the second amplifirer in turn, and the output of described serial digital to analog converter is connected with VCXO.

Further, also comprise the first phase-locked loop and the second phase-locked loop, the output of described first phase-locked loop is connected with the first low-converter and the first I/Q modulator respectively, and the output of described second phase-locked loop is connected with the second low-converter and the second I/Q modulator respectively.

Further, also comprise CPU, the output of described CPU is connected with analog to digital converter, a FPGA, the 2nd FPGA, the first digital to analog converter and the second digital to analog converter respectively.

Further, the first automatic gain control circuit is connected with between the output of described first low noise amplifier and the input of the first filter, the second automatic gain control circuit is connected with between the output of described second low noise amplifier and the input of the second filter, be connected with the 3rd automatic gain control circuit between the output of described 3rd filter and the input of the first amplifirer, between the output of described 4th filter and the input of the second amplifirer, be connected with the 4th automatic gain control circuit.

Further, the output of described CPU is also connected with the first automatic gain control circuit, the second automatic gain control circuit, the 3rd automatic gain control circuit and the 4th automatic gain control circuit respectively.

The present invention solves another technical scheme that its technical problem adopts:

Based on the method that the realized Interference Cancellation of FPGA locks with base station, comprising:

Upward signal handling process:

S11, receive up input signal after successively low noise amplification, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain upstream digital input signal;

S12, Digital Down Convert, Interference Cancellation and auto level control process are carried out successively to upstream digital input signal after, then carry out Digital Up Convert, obtain up intermediate-freuqncy signal;

S13, digital-to-analogue conversion and IQ modulation treatment are carried out successively to up intermediate-freuqncy signal after, obtain orthogonal up analog signal;

S14, up analog signal is carried out filtering and power amplification process successively after send;

And downstream signal handling process:

S21, receive descending input signal after successively low noise amplification, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain downstream digital input signal;

S22, Digital Down Convert, Interference Cancellation and auto level control process are carried out successively to downstream digital input signal after, then carry out base station locking processing and Digital Up Convert successively, obtain descending intermediate-freuqncy signal;

S23, digital-to-analogue conversion and IQ modulation treatment are carried out successively to descending intermediate-freuqncy signal after, obtain orthogonal downstream analog signal;

S24, downstream analog signal is carried out filtering and power amplification process successively after send;

Further, described step S11, it is specially:

After receiving up input signal, successively low noise amplification, automatic growth control, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain upstream digital input signal;

Described step S14, it is specially:

Send after up analog signal is carried out filtering, automatic growth control and power amplification process successively.

Further, described step S21, it is specially:

After receiving descending input signal, successively low noise amplification, automatic growth control, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain downstream digital input signal;

Described step S24, it is specially:

Send after downstream analog signal is carried out filtering, automatic growth control and power amplification process successively.

Further, base station locking processing described in described step S22, comprises frequency offset correction process, cell synchronisation procedure and pilot counteracting and flows through journey;

Described frequency offset correction process comprises:

S221, carry out frequency deviation estimation, calculate amounts of frequency offset, and amounts of frequency offset is sent to Serial DAC;

This amounts of frequency offset is converted into voltage change by S222, Serial DAC, and this voltage change is sent to VCXO;

S223, VCXO receive described voltage change and carry out frequency adjustment according to this voltage change, complete frequency offset correction.

Further, frequency deviation described in described step S221 is estimated, adopts following formula:

$f=\frac{1}{k}\arg \left\{z\right\}$

Wherein, f is frequency deviation estimated value, and k is shift register lengths, and Z is correlation.

The invention has the beneficial effects as follows: the system that the realized Interference Cancellation based on FPGA of the present invention and base station lock, Interference Cancellation and base station lock function can be realized, the pilot pollution problem caused because of base station selection can be solved simultaneously, simultaneously native system can compatible processing upward signal and downstream signal, implementation is simple, reduce production cost, as long as and the filter changed in native system, can compatible multiple systems standard.

Another beneficial effect of the present invention is: the method that the realized Interference Cancellation based on FPGA of the present invention and base station lock, Interference Cancellation can be realized and base station locks, the pilot pollution problem caused because of base station selection can be solved simultaneously, this method can process upward signal and downstream signal simultaneously simultaneously, implementation is simple, reduce production cost, as long as and in implementation process, change filter, can compatible multiple systems standard.

Accompanying drawing explanation

Below in conjunction with drawings and Examples, the invention will be further described.

Fig. 1 is the structured flowchart of the system that the realized Interference Cancellation based on FPGA of the present invention locks with base station;

Fig. 2 be the system that locks with base station of the realized Interference Cancellation that the present invention is based on FPGA the structured flowchart of embodiment;

Fig. 3 method that to be the realized Interference Cancellation based on FPGA of the present invention lock with base station carries out the hierarchical correlator structure used in appraising frequency bias process;

Fig. 4 is that the realized Interference Cancellation based on FPGA of the present invention carries out adopting discontinuous assembled scheme to calculate the method schematic diagram of time slot head in frequency offset correction process with the method that base station locks;

Fig. 5 is the phase place change schematic diagram in frequency offset correction process between two continuous print partial correlation values;

Fig. 6 is the method schematic diagram adopting in time slot assembled scheme of checking the mark to calculate time slot head in frequency offset correction process;

Fig. 7 is the method schematic diagram carrying out frequency deviation fine tuning in frequency offset correction process.

Embodiment

For the ease of following description, first provide following explanation of nouns:

ADC(Analog-to-Digital Converter): analog to digital converter;

DAC(Digital-to-Analog Converter): digital to analog converter;

DDC(Digital down converter): digital down converter;

DUC(Digital Up Converter): digital up converter;

LNA(Low-Noise Amplifier): low noise amplifier;

PA(Power Amplifier): power amplifier;

AGC(Automatic Gain Control): automatic growth control;

FPGA(Field Programmable Gate Array): field programmable gate array;

ICS(Interference Cancellation System): interference cancellation systems;

IQ(IN phase Orthogonal): inphase quadrature;

CPU(Central Processing Unit): central processing unit;

The main flow flush bonding processor of ARM7: Britain ARM company designs, kernel is three class pipeline and the variational OR structure of 0.9MIPS/MHz.

In the accompanying drawings, in order to make picture more succinct, to low noise amplifier, automatic gain control circuit, digital to analog converter and power amplifier, adopt respectively be called for short LNA accordingly, agc circuit, DAC and PA represent.

With reference to Fig. 1, the invention provides the system that a kind of realized Interference Cancellation based on FPGA locks with base station, comprise: the first low noise amplifier, the second low noise amplifier, for cooperative achievement Interference Cancellation and base station locking a FPGA and the 2nd FPGA, the descending input signal of input termination of described first low noise amplifier, the output of described first low noise amplifier is connected with the first filter, the first low-converter and analog to digital converter in turn;

The input of described second low noise amplifier connects row input signal, and the output of described second low noise amplifier is connected with the second filter and the second low-converter in turn, and the output of described second low-converter is connected with analog to digital converter;

First output of described analog to digital converter is all connected with the 2nd FPGA by a FPGA with the second output, and the output of described 2nd FPGA is connected to the first digital to analog converter, the second digital to analog converter and serial digital to analog converter;

The output of described first digital to analog converter is connected with the first I/Q modulator, the 3rd filter and the first amplifirer in turn, the output of described second digital to analog converter is connected with the second I/Q modulator, the 4th filter and the second amplifirer in turn, and the output of described serial digital to analog converter is connected with VCXO.

Be used herein two FPGA associated treatment, complete the process such as Interference Cancellation and base station locking, there are 81 data wires between two FPGA, in associated treatment process, carried out the mutual transmission of deal with data by these 81 data wires, and then realize the distribution of FPGA resource.

In Fig. 1, DL_in refers to descending input signal, and UL_in refers to up input signal, and DL_out refers to descending output signal, and UL_out refers to up output signal.

Be further used as preferred embodiment, with reference to Fig. 2, also comprise the first phase-locked loop and the second phase-locked loop, the output of described first phase-locked loop is connected with the first low-converter and the first I/Q modulator respectively, and the output of described second phase-locked loop is connected with the second low-converter and the second I/Q modulator respectively.

Be further used as preferred embodiment, also comprise CPU, the output of described CPU is connected with analog to digital converter, a FPGA, the 2nd FPGA, the first digital to analog converter and the second digital to analog converter respectively.

Be further used as preferred embodiment, the first automatic gain control circuit is connected with between the output of described first low noise amplifier and the input of the first filter, the second automatic gain control circuit is connected with between the output of described second low noise amplifier and the input of the second filter, be connected with the 3rd automatic gain control circuit between the output of described 3rd filter and the input of the first amplifirer, between the output of described 4th filter and the input of the second amplifirer, be connected with the 4th automatic gain control circuit.

Be further used as preferred embodiment, the output of described CPU is also connected with the first automatic gain control circuit, the second automatic gain control circuit, the 3rd automatic gain control circuit and the 4th automatic gain control circuit respectively.

Preferably, described CPU adopts ARM7 processor.

Present invention also offers a kind of method that realized Interference Cancellation based on FPGA locks with base station, comprising:

Upward signal handling process:

S11, receive up input signal after successively low noise amplification, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain upstream digital input signal;

S12, Digital Down Convert, Interference Cancellation and auto level control process are carried out successively to upstream digital input signal after, then carry out Digital Up Convert, obtain up intermediate-freuqncy signal;

S13, digital-to-analogue conversion and IQ modulation treatment are carried out successively to up intermediate-freuqncy signal after, obtain orthogonal up analog signal;

S14, up analog signal is carried out filtering and power amplification process successively after send;

And downstream signal handling process:

S21, receive descending input signal after successively low noise amplification, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain downstream digital input signal;

S22, Digital Down Convert, Interference Cancellation and auto level control process are carried out successively to downstream digital input signal after, then carry out base station locking processing and Digital Up Convert successively, obtain descending intermediate-freuqncy signal;

S23, digital-to-analogue conversion and IQ modulation treatment are carried out successively to descending intermediate-freuqncy signal after, obtain orthogonal downstream analog signal;

S24, downstream analog signal is carried out filtering and power amplification process successively after send;

Be further used as preferred embodiment, described step S11, it is specially:

After receiving up input signal, successively low noise amplification, automatic growth control, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain upstream digital input signal;

Described step S14, it is specially:

Send after up analog signal is carried out filtering, automatic growth control and power amplification process successively.

Be further used as preferred embodiment, described step S21, it is specially:

After receiving descending input signal, successively low noise amplification, automatic growth control, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain downstream digital input signal;

Described step S24, it is specially:

Send after downstream analog signal is carried out filtering, automatic growth control and power amplification process successively.

Be further used as preferred embodiment, base station locking processing described in described step S22, comprise frequency offset correction process, cell synchronisation procedure and pilot counteracting and flow through journey;

Described frequency offset correction process comprises:

S221, carry out frequency deviation estimation, calculate amounts of frequency offset, and amounts of frequency offset is sent to Serial DAC;

This amounts of frequency offset is converted into voltage change by S222, Serial DAC, and this voltage change is sent to VCXO;

S223, VCXO receive described voltage change and carry out frequency adjustment according to this voltage change, complete frequency offset correction.

Be further used as preferred embodiment, frequency deviation described in described step S221 is estimated, adopts following formula:

$f=\frac{1}{k}\arg \left\{z\right\}$

Wherein, f is frequency deviation estimated value, and k is shift register lengths, and Z is correlation.

The size of system frequency deviation has not only had influence on the stable of cell synchronous, also affects the realization of pilot counteracting simultaneously.The VCXO that native system adopts is the crystal oscillator being with voltage-controlled pin, and when there being magnitude of voltage to act on voltage-controlled pin, crystal oscillator will change system frequency according to this magnitude of voltage, namely carry out frequency adjustment, thus complete frequency offset correction.

Frequency offset correction utilizes Received signal strength, refers to descending input signal here, and the correlation with local Primary Synchronisation Code and local scrambler, extracts the information of frequency deviation, thus change the frequency of system crystal oscillator, reduces frequency deviation.

For the signal of different system standard, as WCDMA, CDMA200 and GSM signal etc., frequency deviation estimating method also slightly difference, provides the frequency deviation estimating method of WCDMA signal here:

First, carry out frequency coarse adjustment, use the related operation with Primary Synchronisation Code, suppose that Received signal strength is r [i], sampling instant is t=iT _c, T _cfor the chip lengths of WCDMA, r [i] can be expressed as:

$r\left[i\right]=\sqrt{P\left[i\right]/2}\mathrm{\α}\left[i\right]e^{\mathrm{j\θ}\left[i\right]}\mathrm{Cpsch}[i-k]+n\left[i\right]$

Wherein, P [i] is the power of Primary Synchronisation Code, and α [i] is the change in gain because channel fading produces, and θ [i] is the phase distortion produced due to the difference on the frequency between channel and VCXO, the Primary Synchronisation Code that Cpsch [i] designs for reducing matched filter complexity, kT _cbe the time delay because channel and receiving filter produce, n [i] comprises intra-cell interference, presence of intercell interference and terminal noise.

Transmit in first time slot of Primary Synchronisation Code only in a frame 10 time slots, P [i] can with 2560 for the cycle, and its expression formula is:

$P\left[i\right]=\left\{\begin{array}{c}P,0\&le;i<256\\ \mathrm{0,258}\&le;i<2560\end{array}\right.$

Primary Synchronisation Code can be the code X of 16 by two parts length ₁, X ₂generate:

Cpsch[i]＝(1+j)X ₁[i(div)16]X ₂[i(mod)16]

Wherein, X ₁for

X ₁=[1,1,1,-1,-1,1,-1,-1,1,1,1,-1,1,-1,1,1]

X ₂for

X ₂=[1,1,1,1,1,1,-1,-1,1,-1,1,-1,1,-1,-1,1]

I (div) 16 and i (mod) 16 is respectively the quotient and the remainder of i/16.

Reference Fig. 3, Fig. 3 are the hierarchical correlator structure used in calculating process, and when the unsteadiness of VCXO reaches 10ppm, it is the most appropriate for using 64 chips to carry out related operation.A _k,jj=0 in [i], 1,2,3, represent a jth partial correlation values of a corresponding kth time slot.

$a_{k,j}\left[i\right]=\frac{1}{64}{\mathrm{\&Sigma;}}_{l=64j}^{64(j+1)-1}r[i+1]X_1\left[l\left(\mathrm{div}\right)16\right]X_2\left[l\left(\mathrm{mod}\right)16\right]+\mathrm{\&eta;}\left[i\right]$

Wherein η [i] is the distracter that n [i] and Cpsch [i] related operation produce.In order to time slot head reliably be detected, a _kj[i] should add up over multiple slots.

With reference to the method figure for adopting discontinuous assembled scheme to calculate time slot head in Fig. 4, figure, the output Znon [i] on Ns time slot can be expressed as:

$\mathrm{Znon}\left[i\right]={\mathrm{\&Sigma;}}_{k=0}^{\mathrm{Ns}-1}{\mathrm{\&Sigma;}}_{j=0}^3{\left|\right|a_{k,j}\left[i\right]\left|\right|}^2$

When there being an initialization frequency deviation, the phase place change between two continuous print partial correlation values and the relation of frequency deviation can refer to shown in Fig. 5.

Reference Fig. 6, Fig. 6 are the method adopting in time slot assembled scheme of checking the mark to calculate time slot head, and the output on Ns time slot is that Zdiff [i] can be expressed as:

$\mathrm{Zdiff}\left[i\right]={\mathrm{\&Sigma;}}_{k=0}^{\mathrm{Ns}-1}{\mathrm{\&Sigma;}}_{j=0}^2{a}_{k,j}^{*}\left[i\right]\&CenterDot;a_{k,j+1}\left[i\right]$

According to Fig. 5, frequency deviation estimated value is

$f_0=\frac{1}{64T_c}\arg \left\{Z_{\mathrm{diff}}\right[i_{\mathrm{MAX}}\left]\right\}$

Wherein i _mAXfor the maximum in Fig. 4 detected by method, namely time slot head, calculates Z _diff[i _mAX] after, the size of frequency deviation is calculated according to cordic algorithm:

$\left\{\begin{array}{c}{x}_{k+1}=x_k-{\mathrm{\&delta;}}_k{y}_k{2}^{-k}\\ y_{k+1}=y_k+{\mathrm{\&delta;}}_k{x}_k{2}^{-k}\\ z_{k+1}=z_k-{\mathrm{\&delta;}}_k{\mathrm{\&epsiv;}}_k\end{array}\right.$

Wherein, ε _k=tan ^-12 ^-k, k>=0, ${\mathrm{\&delta;}}_k=\left\{\begin{array}{c}1,y_k<0\\ -1,y_k>0\end{array}\right.$

Wherein, x ₀, y ₀original input signal, z ₀=0, through n iteration, result is:

z _n+1≈tan ^-1(y ₀/x ₀)

After scrambler identification, carry out the fine tuning of frequency deviation.

Scrambler is defined as

Sdl,n(i)=Zn(i)+j Zn((i+131072)mod(218-1))，i=0,1，...,38399

Wherein,

zn(i)=x((i+n)mod(218-1))+y(i)mod2，i=0，...,218-2

x(i+18)=x(i+7)+x(i)mod2，i=0,…,218-20

Initial value x (0)=1, x (1)=x (2)=...=x (16)=x (17)=0.

y(0)=y(1)=…=y(16)=y(17)=1

When calculating correlation, if the data entered are d, then d can be expressed as

d[i]＝data[i]S _dl，n[i]e ^jθ[i]

Wherein data [i] is the base band data without scrambling, S _{dl, n}[i] is the scrambler for scrambling, and θ [i] is difference on the frequency due to channel and VCXO and produces the distortion of phase place.

With reference to the operation method of the frequency deviation fine tuning in Fig. 7, can calculate correlation Z, its expression formula is:

$Z={\mathrm{\&Sigma;}}_{i=1}^{N}d\left[i\right]S_{\mathrm{dl},n}^{\&prime;}\left[i\right]d{[i-k]}^{*}{S}_{\mathrm{dl},n}^{\&prime;}{[i-k]}^{*}$

Wherein N is accumulative frequency, and N value more large Doppler estimation is more accurate, and k is shift register lengths, and k more large Doppler estimation is more accurate, S _{dl, n}[i] is local generation scrambler, and scrambling code number is the same with the scrambler of d [i].A1 [i], a1 [i-k] and a2 [i] M signal for producing in processing procedure in Fig. 7.

Therefore, frequency deviation estimated value is:

$f=\frac{1}{k}\arg \left\{z\right\}$

After calculating frequency deviation estimated value, fine tuning can be carried out to VCXO.

It is consistent with the frequency of base station in order to the frequency of system be adjusted to that frequency deviation is estimated, like this, signal processing can be more accurate.

The system that realized Interference Cancellation based on FPGA of the present invention and base station lock is applied on repeater, for the base station locking processing of CDMA2000, its realization flow comprises frequency offset estimation procedure, cell synchronisation procedure, pilot counteracting process, the signal that repeater receives, includes the signal of multiple different base station.There is a pilot generator in system FPGA program inside, the pilot signal corresponding with input signal can be produced.First we do Cell searching according to the signal received, and finds local all communities (being assumed to be 3).CDMA2000 community distinguishes according to the bias of its pilot PN sequence.Cell searching realizes mainly through matched filter, according to the structural design matched filter of 1X pilot channel, obtains pilot tone relevant peaks, exports the bias calculating current cell pilot PN sequence according to CDMA2000 1x demodulation.

According to the community searched out, the corresponding pilot frequency sequence of our regeneration, choosing 2 needs the district pilots sequence suppressed to carry out channel estimating together with Received signal strength.The local pilot generator signal drawn is carried out the estimation of channel by us, and the impulse response obtaining channel goes out, then simulates through the channel impulse response estimated want repressed pilot signal from input signal; Then Received signal strength is with subtracting each other, and draw difference, its effect is the tap coefficient constantly adjusting channel impulse response, and order is more close to real channel.Meanwhile, be also through the signal that pilot tone suppresses, then gone out by antenna transmission.

More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and these equivalent modification or replacement are all included in the application's claim limited range.

Claims (7)

1. based on the system that the realized Interference Cancellation of FPGA locks with base station, it is characterized in that, comprise: the first low noise amplifier, the second low noise amplifier, for cooperative achievement Interference Cancellation and base station locking a FPGA and the 2nd FPGA, the output of described first low noise amplifier is connected with the first filter, the first low-converter and analog to digital converter in turn;

The output of described second low noise amplifier is connected with the second filter and the second low-converter in turn, and the output of described second low-converter is connected with analog to digital converter;

First output of described analog to digital converter is all connected with the 2nd FPGA by a FPGA with the second output, and the output of described 2nd FPGA is connected to the first digital to analog converter, the second digital to analog converter and serial digital to analog converter;

The output of described first digital to analog converter is connected with the first I/Q modulator, the 3rd filter and the first amplifirer in turn, the output of described second digital to analog converter is connected with the second I/Q modulator, the 4th filter and the second amplifirer in turn, and the output of described serial digital to analog converter is connected with VCXO;

Also comprise the first phase-locked loop and the second phase-locked loop, the output of described first phase-locked loop is connected with the first low-converter and the first I/Q modulator respectively, and the output of described second phase-locked loop is connected with the second low-converter and the second I/Q modulator respectively;

Also comprise CPU, the output of described CPU is connected with analog to digital converter, a FPGA, the 2nd FPGA, the first digital to analog converter and the second digital to analog converter respectively;

The first automatic gain control circuit is connected with between the output of described first low noise amplifier and the input of the first filter, the second automatic gain control circuit is connected with between the output of described second low noise amplifier and the input of the second filter, be connected with the 3rd automatic gain control circuit between the output of described 3rd filter and the input of the first amplifirer, between the output of described 4th filter and the input of the second amplifirer, be connected with the 4th automatic gain control circuit.

2. the system that locks of the realized Interference Cancellation based on FPGA according to claim 1 and base station, is characterized in that: the output of described CPU is also connected with the first automatic gain control circuit, the second automatic gain control circuit, the 3rd automatic gain control circuit and the 4th automatic gain control circuit respectively.

3., based on the method that the realized Interference Cancellation of FPGA locks with base station, it is characterized in that, comprising:

Upward signal handling process:

S11, receive up input signal after successively low noise amplification, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain upstream digital input signal;

S12, Digital Down Convert, Interference Cancellation and auto level control process are carried out successively to upstream digital input signal after, then carry out Digital Up Convert, obtain up intermediate-freuqncy signal;

S13, digital-to-analogue conversion and IQ modulation treatment are carried out successively to up intermediate-freuqncy signal after, obtain orthogonal up analog signal;

S14, up analog signal is carried out filtering and power amplification process successively after send;

And downstream signal handling process:

S21, receive descending input signal after successively low noise amplification, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain downstream digital input signal;

S22, Digital Down Convert, Interference Cancellation and auto level control process are carried out successively to downstream digital input signal after, then carry out base station locking processing and Digital Up Convert successively, obtain descending intermediate-freuqncy signal;

S23, digital-to-analogue conversion and IQ modulation treatment are carried out successively to descending intermediate-freuqncy signal after, obtain orthogonal downstream analog signal;

S24, downstream analog signal is carried out filtering and power amplification process successively after send.

4. the method that locks of the realized Interference Cancellation based on FPGA according to claim 3 and base station, is characterized in that:

Described step S11, it is specially:

After receiving up input signal, successively low noise amplification, automatic growth control, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain upstream digital input signal;

Described step S14, it is specially:

Send after up analog signal is carried out filtering, automatic growth control and power amplification process successively.

5. the method that locks of the realized Interference Cancellation based on FPGA according to claim 3 and base station, is characterized in that:

Described step S21, it is specially:

After receiving descending input signal, successively low noise amplification, automatic growth control, filtering, down-conversion and analog-to-digital conversion process are carried out to it, obtain downstream digital input signal;

Described step S24, it is specially:

Send after downstream analog signal is carried out filtering, automatic growth control and power amplification process successively.

6. the method that locks of the realized Interference Cancellation based on FPGA according to claim 3 and base station, is characterized in that base station locking processing described in described step S22 comprises frequency offset correction process, cell synchronisation procedure and pilot counteracting and flows through journey;

Described frequency offset correction process comprises:

S221, carry out frequency deviation estimation, calculate amounts of frequency offset, and amounts of frequency offset is sent to Serial DAC;

This amounts of frequency offset is converted into voltage change by S222, Serial DAC, and this voltage change is sent to VCXO;

S223, VCXO receive described voltage change and carry out frequency adjustment according to this voltage change, complete frequency offset correction.

7. the method that lock of the realized Interference Cancellation based on FPGA according to claim 6 and base station, it is characterized in that, the estimation of frequency deviation described in described step S221, adopts following formula:

Wherein, f is frequency deviation estimated value, and k is shift register lengths, and Z is correlation.