CN102984105A - System and method capable of achieving interference offset and scanning signal based on field programmable gate array (FPGA) - Google Patents

Abstract

The invention discloses a system and method capable of achieving interference offset and scan signal based on a field programmable gate array (FPGA). The output end of a first low noise amplifier is sequentially connected with a first filter, a first lower converter and an analog-digital converter. The output end of a second low noise amplifier is sequentially connected with a second filter and a second lower converter. The output end of the second lower converter is connected with the analog-digital converter. A first output end and a second output end of the analog-digital converter are connected with a second FPGA through a first FPGA. The output end of the second FPGA is respectively connected with a first digital-to-analog converter (DAC), a second DAC and a serial digital analog converter. The output end of the first DAC is sequentially connected with a first intelligent quotient (IQ) modulator, a third filter and a first power amplifier. The output end of the second DAC is sequentially connected with a second IQ modulator, a fourth filter and a second power amplifier. The output end of the serial digital analog converter is connected with a voltage controlled oscillator. The system and method capable of achieving interference offset and scan signal based on FPGA has the advantages of being simple in implementation model, low in cost, compatible with multiple system formats and is widely used in communication industry.

Description

Based on the Interference Cancellation realized of FPGA and the system and method for base station locking

Technical field

The present invention relates to a kind of system and method for realizing the base station locking, particularly based on the Interference Cancellation realized of FPGA and the system and method for base station locking.

Background technology

In digital radio repeater, amplify simultaneously all owing to can not screen to received signal and receive signal, can cause occurring pilot pollution, therefore in communication process, need to adopt the base station lock-in techniques to carry out the base station locking.Existing scheme mainly is that uplink and downlink signals is separated the disparate modules platform processes, and the repeater of the different systems systems such as corresponding CDMA2000, WCDMA, TD-SCDMA, needs the different base station lock fixed system of exploitation, and manufacturing cost is high.

Summary of the invention

In order to solve above-mentioned technical problem, the invention provides a kind of cheaply, repeater that can compatible multiple systems standard based on the Interference Cancellation realized of FPGA and the system of base station locking.The present invention also provide a kind of cheaply, repeater that can compatible multiple systems standard based on the Interference Cancellation realized of FPGA and the method for base station locking.

The technical solution adopted for the present invention to solve the technical problems is:

Based on the Interference Cancellation realized of FPGA and the system of base station locking, comprising:

The first low noise amplifier, the second low noise amplifier, be used for a collaborative FPGA and the 2nd FPGA that realizes Interference Cancellation and base station locking, the descending input signal of input termination of described the first low noise amplifier, the output of described the first low noise amplifier is connected with the first filter, the first low-converter and analog to digital converter in turn;

The input of described the second low noise amplifier connects capable input signal, and the output of described the second low noise amplifier is connected with the second filter and the second low-converter in turn, and the output of described the second low-converter is connected with analog to digital converter;

The first output of described analog to digital converter all is connected with the 2nd FPGA by a FPGA with the second output, and the output of described the 2nd FPGA is connected with respectively the first digital to analog converter, the second digital to analog converter and serial digital to analog converter;

The output of described the first digital to analog converter is connected with an IQ modulator, the 3rd filter and the first amplifirer in turn, the output of described the second digital to analog converter is connected with the 2nd IQ modulator, the 4th filter and the second amplifirer in turn, and the output of described serial digital to analog converter is connected with VCXO.

Further, also comprise the first phase-locked loop and the second phase-locked loop, the output of described the first phase-locked loop is connected with the first low-converter and an IQ modulator respectively, and the output of described the second phase-locked loop is connected with the second low-converter and the 2nd IQ modulator respectively.

Further, also comprise CPU, the output of described CPU is connected with analog to digital converter, a FPGA, the 2nd FPGA, the first digital to analog converter and the second digital to analog converter respectively.

Further, be connected with the first automatic gain control circuit between the input of the output of described the first low noise amplifier and the first filter, be connected with the second automatic gain control circuit between the input of the output of described the second low noise amplifier and the second filter, be connected with the 3rd automatic gain control circuit between the input of the output of described the 3rd filter and the first amplifirer, be connected with the moving gain control circuit of four selfs between the input of the output of described the 4th filter and the second amplifirer.

Further, the output of described CPU also is connected with the moving gain control circuit of the first automatic gain control circuit, the second automatic gain control circuit, the 3rd automatic gain control circuit and four selfs respectively.

The present invention solves another technical scheme that its technical problem adopts:

Based on the Interference Cancellation realized of FPGA and the method for base station locking, comprising:

The upward signal handling process:

Behind S11, the up input signal of reception it is carried out low noise amplification, filtering, down-conversion and analog-to-digital conversion process successively, obtain the upstream digital input signal;

S12, the upstream digital input signal carried out successively Digital Down Convert, Interference Cancellation and automatic electric-level control and processes after, carry out again Digital Up Convert, obtain up intermediate-freuqncy signal;

S13, up intermediate-freuqncy signal carried out digital-to-analogue conversion and IQ modulation treatment successively after, obtain the up analog signal of quadrature;

S14, up analog signal is carried out sending after filtering and power amplification are processed successively;

And downstream signal handling process:

Behind S21, the descending input signal of reception it is carried out low noise amplification, filtering, down-conversion and analog-to-digital conversion process successively, obtain descending digital input signals;

S22, descending digital input signals carried out successively Digital Down Convert, Interference Cancellation and automatic electric-level control and processes after, carry out successively again base station locking processing and Digital Up Convert, obtain descending intermediate-freuqncy signal;

S23, descending intermediate-freuqncy signal carried out digital-to-analogue conversion and IQ modulation treatment successively after, obtain the descending analog signal of quadrature;

S24, descending analog signal is carried out sending after filtering and power amplification are processed successively;

Further, described step S11, it is specially:

After receiving up input signal it is carried out low noise amplification, automatic gain control, filtering, down-conversion and analog-to-digital conversion process successively, obtain the upstream digital input signal;

Described step S14, it is specially:

Up analog signal is carried out sending after filtering, automatic gain control and power amplification are processed successively.

Further, described step S21, it is specially:

After receiving descending input signal it is carried out low noise amplification, automatic gain control, filtering, down-conversion and analog-to-digital conversion process successively, obtain descending digital input signals;

Described step S24, it is specially:

Descending analog signal is carried out sending after filtering, automatic gain control and power amplification are processed successively.

Further, base station locking processing described in the described step S22 comprises that frequency offset correction process, cell synchronous process and pilot counteracting flow through journey;

Described frequency offset correction process comprises:

S221, carry out frequency deviation and estimate, calculate amounts of frequency offset, and amounts of frequency offset is sent to Serial DAC;

S222, Serial DAC are converted into voltage change with this amounts of frequency offset, and this voltage change is sent to VCXO;

S223, VCXO receive described voltage change and carry out the frequency adjustment according to this voltage change, finish frequency offset correction.

Further, frequency deviation described in the described step S221 is estimated, is adopted following formula:

$f=\frac{1}{k}\arg \left\{z\right\}$

Wherein, f is the frequency deviation estimated value, and k is shift register length, and Z is correlation.

The invention has the beneficial effects as follows: of the present invention based on the Interference Cancellation realized of FPGA and the system of base station locking, can realize Interference Cancellation and base station lock function, simultaneously can solve the pilot pollution problem that causes because of base station selection, but while native system compatible processing upward signal and downstream signal, implementation is simple, lowered production cost, and if the filter in the change native system, can compatible multiple systems standard.

Another beneficial effect of the present invention is: of the present invention based on the Interference Cancellation realized of FPGA and the method for base station locking, can realize the locking of Interference Cancellation and base station, simultaneously can solve the pilot pollution problem that causes because of base station selection, this method can be processed upward signal and downstream signal simultaneously simultaneously, implementation is simple, lowered production cost, and as long as in implementation process, change filter, can compatible multiple systems standard.

Description of drawings

The invention will be further described below in conjunction with drawings and Examples.

Fig. 1 is of the present invention based on the Interference Cancellation realized of FPGA and the structured flowchart of the system of base station locking;

Fig. 2 be the Interference Cancellation realized that the present invention is based on FPGA with the system of base station locking the structured flowchart of embodiment;

To be the Interference Cancellation realized based on FPGA of the present invention carry out the hierarchical correlator structure used in the appraising frequency bias process with the method for base station locking to Fig. 3;

Fig. 4 is that the Interference Cancellation realized based on FPGA of the present invention carries out adopting in the frequency offset correction process discontinuous assembled scheme to calculate the method schematic diagram of time slot head with the method for base station locking;

Fig. 5 is that the phase place between two continuous part correlations changes schematic diagram in the frequency offset correction process;

Fig. 6 adopts the assembled scheme of checking the mark in the time slot to calculate the method schematic diagram of time slot head in the frequency offset correction process;

Fig. 7 is the method schematic diagram that carries out the frequency deviation fine tuning in the frequency offset correction process.

Embodiment

For the ease of following description, the following explanation of nouns of given first:

ADC(Analog-to-Digital Converter): analog to digital converter;

DAC(Digital-to-Analog Converter): digital to analog converter;

DDC(Digital down converter): digital down converter;

DUC(Digital Up Converter): digital up converter;

LNA(Low-Noise Amplifier): low noise amplifier;

PA(Power Amplifier): power amplifier;

AGC(Automatic Gain Control): automatic gain control;

FPGA(Field Programmable Gate Array): field programmable gate array;

ICS(Interference Cancellation System): interference cancellation systems;

IQ(IN phase Orthogonal): inphase quadrature;

CPU(Central Processing Unit): central processing unit;

ARM7: the main flow flush bonding processor of Britain ARM company design, kernel is three class pipeline and the variational OR structure of 0.9MIPS/MHz.

In the accompanying drawings, in order to make picture more succinct, to low noise amplifier, automatic gain control circuit, digital to analog converter and power amplifier, adopt respectively the corresponding LNA of abbreviation, agc circuit, DAC and PA to represent.

With reference to Fig. 1, the invention provides a kind of based on the Interference Cancellation realized of FPGA and the system of base station locking, comprise: the first low noise amplifier, the second low noise amplifier, be used for a collaborative FPGA and the 2nd FPGA that realizes Interference Cancellation and base station locking, the descending input signal of input termination of described the first low noise amplifier, the output of described the first low noise amplifier is connected with the first filter, the first low-converter and analog to digital converter in turn;

The input of described the second low noise amplifier connects capable input signal, and the output of described the second low noise amplifier is connected with the second filter and the second low-converter in turn, and the output of described the second low-converter is connected with analog to digital converter;

The first output of described analog to digital converter all is connected with the 2nd FPGA by a FPGA with the second output, and the output of described the 2nd FPGA is connected with respectively the first digital to analog converter, the second digital to analog converter and serial digital to analog converter;

The output of described the first digital to analog converter is connected with an IQ modulator, the 3rd filter and the first amplifirer in turn, the output of described the second digital to analog converter is connected with the 2nd IQ modulator, the 4th filter and the second amplifirer in turn, and the output of described serial digital to analog converter is connected with VCXO.

Here two FPGA associated treatment have been used, finish the processing such as Interference Cancellation and base station locking, there are 81 data wires between two FPGA, in the associated treatment process, carry out the mutual transmission of deal with data by these 81 data wires, and then realize the distribution of FPGA resource.

Among Fig. 1, DL_in refers to descending input signal, and UL_in refers to up input signal, and DL_out refers to descending output signal, and UL_out refers to up output signal.

Be further used as preferred embodiment, with reference to Fig. 2, also comprise the first phase-locked loop and the second phase-locked loop, the output of described the first phase-locked loop is connected with the first low-converter and an IQ modulator respectively, and the output of described the second phase-locked loop is connected with the second low-converter and the 2nd IQ modulator respectively.

Be further used as preferred embodiment, also comprise CPU, the output of described CPU is connected with analog to digital converter, a FPGA, the 2nd FPGA, the first digital to analog converter and the second digital to analog converter respectively.

Be further used as preferred embodiment, be connected with the first automatic gain control circuit between the input of the output of described the first low noise amplifier and the first filter, be connected with the second automatic gain control circuit between the input of the output of described the second low noise amplifier and the second filter, be connected with the 3rd automatic gain control circuit between the input of the output of described the 3rd filter and the first amplifirer, be connected with the moving gain control circuit of four selfs between the input of the output of described the 4th filter and the second amplifirer.

Be further used as preferred embodiment, the output of described CPU also is connected with the moving gain control circuit of the first automatic gain control circuit, the second automatic gain control circuit, the 3rd automatic gain control circuit and four selfs respectively.

Preferably, described CPU adopts the ARM7 processor.

It is a kind of based on the Interference Cancellation realized of FPGA and the method for base station locking that the present invention also provides, and comprising:

The upward signal handling process:

Behind S11, the up input signal of reception it is carried out low noise amplification, filtering, down-conversion and analog-to-digital conversion process successively, obtain the upstream digital input signal;

S12, the upstream digital input signal carried out successively Digital Down Convert, Interference Cancellation and automatic electric-level control and processes after, carry out again Digital Up Convert, obtain up intermediate-freuqncy signal;

S13, up intermediate-freuqncy signal carried out digital-to-analogue conversion and IQ modulation treatment successively after, obtain the up analog signal of quadrature;

S14, up analog signal is carried out sending after filtering and power amplification are processed successively;

And downstream signal handling process:

Behind S21, the descending input signal of reception it is carried out low noise amplification, filtering, down-conversion and analog-to-digital conversion process successively, obtain descending digital input signals;

S22, descending digital input signals carried out successively Digital Down Convert, Interference Cancellation and automatic electric-level control and processes after, carry out successively again base station locking processing and Digital Up Convert, obtain descending intermediate-freuqncy signal;

S23, descending intermediate-freuqncy signal carried out digital-to-analogue conversion and IQ modulation treatment successively after, obtain the descending analog signal of quadrature;

S24, descending analog signal is carried out sending after filtering and power amplification are processed successively;

Be further used as preferred embodiment, described step S11, it is specially:

After receiving up input signal it is carried out low noise amplification, automatic gain control, filtering, down-conversion and analog-to-digital conversion process successively, obtain the upstream digital input signal;

Described step S14, it is specially:

Up analog signal is carried out sending after filtering, automatic gain control and power amplification are processed successively.

Be further used as preferred embodiment, described step S21, it is specially:

After receiving descending input signal it is carried out low noise amplification, automatic gain control, filtering, down-conversion and analog-to-digital conversion process successively, obtain descending digital input signals;

Described step S24, it is specially:

Descending analog signal is carried out sending after filtering, automatic gain control and power amplification are processed successively.

Be further used as preferred embodiment, base station locking processing described in the described step S22 comprises that frequency offset correction process, cell synchronous process and pilot counteracting flow through journey;

Described frequency offset correction process comprises:

S221, carry out frequency deviation and estimate, calculate amounts of frequency offset, and amounts of frequency offset is sent to Serial DAC;

S222, Serial DAC are converted into voltage change with this amounts of frequency offset, and this voltage change is sent to VCXO;

S223, VCXO receive described voltage change and carry out the frequency adjustment according to this voltage change, finish frequency offset correction.

Be further used as preferred embodiment, frequency deviation described in the described step S221 is estimated, is adopted following formula:

$f=\frac{1}{k}\arg \left\{z\right\}$

Wherein, f is the frequency deviation estimated value, and k is shift register length, and Z is correlation.

The size of system frequency deviation has not only had influence on the stable of cell synchronous, also affects the realization of pilot counteracting simultaneously.The VCXO that native system adopts is the crystal oscillator with voltage-controlled pin, and when having magnitude of voltage to act on voltage-controlled pin, crystal oscillator will change system frequency according to this magnitude of voltage, namely carry out the frequency adjustment, thereby finish frequency offset correction.

Frequency offset correction is to utilize to receive signal, refers to descending input signal here, with the correlation of local Primary Synchronisation Code and local scrambler, extracts the information of frequency deviation, thereby changes the frequency of system's crystal oscillator, reduces frequency deviation.

For the signal of different system standard, such as WCDMA, CDMA200 and GSM signal etc., frequency deviation estimating method is also slightly variant, and the frequency deviation estimating method of WCDMA signal is provided here:

At first, carry out the frequency coarse adjustment, the related operation of use and Primary Synchronisation Code, supposing to receive signal is r[i], sampling instant is t=iT _c, T _cBe the chip lengths of WCDMA, r[i] can be expressed as:

$r\left[i\right]=\sqrt{P\left[i\right]/2}\mathrm{\α}\left[i\right]e^{\mathrm{j\θ}\left[i\right]}\mathrm{Cpsch}[i-k]+n\left[i\right]$

Wherein, P[i] be the power of Primary Synchronisation Code, α [i] is the change in gain that produces owing to channel fading, θ [i] is the phase distortion that produces owing to the difference on the frequency between channel and the VCXO, Cpsch[i] Primary Synchronisation Code that designs for reducing the matched filter complexity, kT _cThe time-delay owing to channel and receiving filter generation, n[i] comprise in the residential quarter and disturb presence of intercell interference and terminal noise.

Primary Synchronisation Code only transmits P[i in first time slot in 10 time slots of a frame] can be take 2560 as the cycle, its expression formula is:

$P\left[i\right]=\left\{\begin{array}{c}P,0\&le;i<256\\ \mathrm{0,258}\&le;i<2560\end{array}\right.$

Primary Synchronisation Code can be 16 code X by two parts length ₁, X ₂Generate:

Cpsch[i]＝(1+j)X ₁[i(div)16]X ₂[i(mod)16]

Wherein, X ₁For

X ₁=[1,1,1,-1,-1,1,-1,-1,1,1,1,-1,1,-1,1,1]

X ₂For

X ₂=[1,1,1,1,1,1,-1,-1,1,-1,1,-1,1,-1,-1,1]

I (div) 16 and i (mod) 16 are respectively the quotient and the remainder of i/16.

With reference to Fig. 3, Fig. 3 is the hierarchical correlator structure of using in the calculating process, and when the unsteadiness of VCXO reached 10ppm, it was the most appropriate using 64 chips to carry out related operation.a _{K, j}J=0 in [i], 1,2,3, represent j part correlation of corresponding k time slot.

$a_{k,j}\left[i\right]=\frac{1}{64}{\mathrm{\&Sigma;}}_{l=64j}^{64(j+1)-1}r[i+1]X_1\left[l\left(\mathrm{div}\right)16\right]X_2\left[l\left(\mathrm{mod}\right)16\right]+\mathrm{\&eta;}\left[i\right]$

Wherein η [i] is n[i] and Cpsch[i] distracter that produces of related operation.In order to detect reliably time slot head, a _Kj[i] should be cumulative at a plurality of time slots.

With reference to Fig. 4, among the figure for adopting discontinuous assembled scheme to calculate the method figure of time slot head, the output Znon[i on Ns time slot] can be expressed as:

$\mathrm{Znon}\left[i\right]={\mathrm{\&Sigma;}}_{k=0}^{\mathrm{Ns}-1}{\mathrm{\&Sigma;}}_{j=0}^3{\left|\right|a_{k,j}\left[i\right]\left|\right|}^2$

When an initialization frequency deviation was arranged, the phase place between two continuous part correlations changed and the relation of frequency deviation can be with reference to shown in Figure 5.

With reference to Fig. 6, Fig. 6 is output as Zdiff[i for adopting the assembled scheme of checking the mark in the time slot to calculate the method for time slot head on Ns the time slot] can be expressed as:

$\mathrm{Zdiff}\left[i\right]={\mathrm{\&Sigma;}}_{k=0}^{\mathrm{Ns}-1}{\mathrm{\&Sigma;}}_{j=0}^2{a}_{k,j}^{*}\left[i\right]\&CenterDot;a_{k,j+1}\left[i\right]$

According to Fig. 5, the frequency deviation estimated value is

$f_0=\frac{1}{64T_c}\arg \left\{Z_{\mathrm{diff}}\right[i_{\mathrm{MAX}}\left]\right\}$

I wherein _MAXBe the detected maximum of method among Fig. 4, namely the time slot head calculates Z _Diff[i _MAX] after, calculate the size of frequency deviation according to the cordic algorithm:

$\left\{\begin{array}{c}{x}_{k+1}=x_k-{\mathrm{\&delta;}}_k{y}_k{2}^{-k}\\ y_{k+1}=y_k+{\mathrm{\&delta;}}_k{x}_k{2}^{-k}\\ z_{k+1}=z_k-{\mathrm{\&delta;}}_k{\mathrm{\&epsiv;}}_k\end{array}\right.$

Wherein, ε _k=tan ^-12 ^-k, k 〉=0, ${\mathrm{\&delta;}}_k=\left\{\begin{array}{c}1,y_k<0\\ -1,y_k>0\end{array}\right.$

Wherein, x ₀, y ₀Original input signal, z ₀=0, through n iteration, the result is:

z _n+1≈tan ^-1(y ₀/x ₀)

After the scrambler identification, carry out the fine tuning of frequency deviation.

Scrambler is defined as

Sdl,n(i)=Zn(i)+j?Zn((i+131072)mod(218-1))，i=0,1，...,38399

Wherein,

zn(i)=x((i+n)mod(218-1))+y(i)mod2，i=0，...,218-2

x(i+18)=x(i+7)+x(i)mod2，i=0,…,218-20

Initial value x (0)=1, x (1)=x (2)=...=x (16)=x (17)=0.

y(0)=y(1)=…=y(16)=y(17)=1

When calculating correlation, establishing the data that enter is d, and then d can be expressed as

d[i]＝data[i]S _dl，n[i]e ^jθ[i]

Data[i wherein] be the base band data without scrambling, S _{Dl, n}[i] is the scrambler for scrambling, and θ [i] is the distortion that produces phase place owing to the difference on the frequency of channel and VCXO.

Operation method with reference to the frequency deviation fine tuning among Fig. 7 can calculate correlation Z, and its expression formula is:

$Z={\mathrm{\&Sigma;}}_{i=1}^{N}d\left[i\right]S_{\mathrm{dl},n}^{\&prime;}\left[i\right]d{[i-k]}^{*}{S}_{\mathrm{dl},n}^{\&prime;}{[i-k]}^{*}$

Wherein N is accumulative frequency, and the larger frequency deviation of N value is estimated more accurate, and k is shift register length, and the larger frequency deviation of k is estimated more accurate, S _{Dl, n}[i] is local scrambler, the scrambling code number and d[i of generating] scrambler the same.A1[i among Fig. 7], a1[i-k] and a2[i] be the M signal that produces in the processing procedure.

Therefore, the frequency deviation estimated value is:

$f=\frac{1}{k}\arg \left\{z\right\}$

After calculating the frequency deviation estimated value, can carry out fine tuning to VCXO.

It is consistent with the frequency of base station for the frequency of system is adjusted to that frequency deviation is estimated, like this, signal processing can be more accurate.

The Interference Cancellation realized based on FPGA of the present invention is applied on the repeater with the system that the base station locks, base station locking processing for CDMA2000, its realization flow comprises frequency offset estimation procedure, the cell synchronous process, the pilot counteracting process, the signal that the repeater receives has comprised the signal of a plurality of different base stations.In system FPGA program inside a pilot generator is arranged, can produce the pilot signal corresponding with input signal.We at first do Cell searching according to the signal that receives, and find local all residential quarters (being assumed to be 3).The CDMA2000 residential quarter is to distinguish according to the bias of its pilot PN sequence.Cell searching mainly realizes that by matched filter the structural design matched filter according to the 1X pilot channel obtains the pilot tone relevant peaks, calculates the bias of current area pilot PN sequence according to CDMA2000 1x demodulation output.

According to the residential quarter that searches out, the corresponding pilot frequency sequence of our regeneration is chosen the district pilots sequence of 2 needs inhibition and is received signal and carries out together channel estimating.The local pilot generator signal that we will draw carries out the estimation of channel, and the impulse response of obtaining channel goes out, and simulates through the channel impulse response of estimating and want repressed pilot signal from input signal; Then receive signal with subtracting each other, draw difference, its effect is the tap coefficient of constantly adjusting channel impulse response, and order is more near real channel.Simultaneously, also be the signal that suppresses through pilot tone, gone out by antenna transmission again.

More than be that better enforcement of the present invention is specified, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite of spirit of the present invention, the modification that these are equal to or replacement all are included in the application's claim limited range.

Claims (10)

1. based on the Interference Cancellation realized of FPGA and the system of base station locking, it is characterized in that, comprise: the first low noise amplifier, the second low noise amplifier, be used for a collaborative FPGA and the 2nd FPGA that realizes Interference Cancellation and base station locking, the output of described the first low noise amplifier is connected with the first filter, the first low-converter and analog to digital converter in turn;

The output of described the second low noise amplifier is connected with the second filter and the second low-converter in turn, and the output of described the second low-converter is connected with analog to digital converter;

The first output of described analog to digital converter all is connected with the 2nd FPGA by a FPGA with the second output, and the output of described the 2nd FPGA is connected with respectively the first digital to analog converter, the second digital to analog converter and serial digital to analog converter;

The output of described the first digital to analog converter is connected with an IQ modulator, the 3rd filter and the first amplifirer in turn, the output of described the second digital to analog converter is connected with the 2nd IQ modulator, the 4th filter and the second amplifirer in turn, and the output of described serial digital to analog converter is connected with VCXO.

2. according to claim 1 based on the Interference Cancellation realized of FPGA and the system of base station locking, it is characterized in that: also comprise the first phase-locked loop and the second phase-locked loop, the output of described the first phase-locked loop is connected with the first low-converter and an IQ modulator respectively, and the output of described the second phase-locked loop is connected with the second low-converter and the 2nd IQ modulator respectively.

3. according to claim 2 based on the Interference Cancellation realized of FPGA and the system of base station locking, it is characterized in that: also comprise CPU, the output of described CPU is connected with analog to digital converter, a FPGA, the 2nd FPGA, the first digital to analog converter and the second digital to analog converter respectively.

4. according to claim 3 based on the Interference Cancellation realized of FPGA and the system of base station locking, it is characterized in that: be connected with the first automatic gain control circuit between the input of the output of described the first low noise amplifier and the first filter, be connected with the second automatic gain control circuit between the input of the output of described the second low noise amplifier and the second filter, be connected with the 3rd automatic gain control circuit between the input of the output of described the 3rd filter and the first amplifirer, be connected with the moving gain control circuit of four selfs between the input of the output of described the 4th filter and the second amplifirer.

5. according to claim 4 based on the Interference Cancellation realized of FPGA and the system of base station locking, it is characterized in that: the output of described CPU also is connected with the moving gain control circuit of the first automatic gain control circuit, the second automatic gain control circuit, the 3rd automatic gain control circuit and four selfs respectively.

6. based on the Interference Cancellation realized of FPGA and the method for base station locking, it is characterized in that, comprising:

The upward signal handling process:

Behind S11, the up input signal of reception it is carried out low noise amplification, filtering, down-conversion and analog-to-digital conversion process successively, obtain the upstream digital input signal;

S12, the upstream digital input signal carried out successively Digital Down Convert, Interference Cancellation and automatic electric-level control and processes after, carry out again Digital Up Convert, obtain up intermediate-freuqncy signal;

S13, up intermediate-freuqncy signal carried out digital-to-analogue conversion and IQ modulation treatment successively after, obtain the up analog signal of quadrature;

S14, up analog signal is carried out sending after filtering and power amplification are processed successively;

And downstream signal handling process:

Behind S21, the descending input signal of reception it is carried out low noise amplification, filtering, down-conversion and analog-to-digital conversion process successively, obtain descending digital input signals;

S22, descending digital input signals carried out successively Digital Down Convert, Interference Cancellation and automatic electric-level control and processes after, carry out successively again base station locking processing and Digital Up Convert, obtain descending intermediate-freuqncy signal;

S23, descending intermediate-freuqncy signal carried out digital-to-analogue conversion and IQ modulation treatment successively after, obtain the descending analog signal of quadrature;

S24, descending analog signal is carried out sending after filtering and power amplification are processed successively.

7. according to claim 6 based on the Interference Cancellation realized of FPGA and the method for base station locking, it is characterized in that:

Described step S11, it is specially:

After receiving up input signal it is carried out low noise amplification, automatic gain control, filtering, down-conversion and analog-to-digital conversion process successively, obtain the upstream digital input signal;

Described step S14, it is specially:

Up analog signal is carried out sending after filtering, automatic gain control and power amplification are processed successively.

8. according to claim 6 based on the Interference Cancellation realized of FPGA and the method for base station locking, it is characterized in that:

Described step S21, it is specially:

After receiving descending input signal it is carried out low noise amplification, automatic gain control, filtering, down-conversion and analog-to-digital conversion process successively, obtain descending digital input signals;

Described step S24, it is specially:

Descending analog signal is carried out sending after filtering, automatic gain control and power amplification are processed successively.

9. according to claim 6 based on the Interference Cancellation realized of FPGA and the method for base station locking, it is characterized in that base station locking processing described in the described step S22 comprises that frequency offset correction process, cell synchronous process and pilot counteracting flow through journey;

Described frequency offset correction process comprises:

S221, carry out frequency deviation and estimate, calculate amounts of frequency offset, and amounts of frequency offset is sent to Serial DAC;

S222, Serial DAC are converted into voltage change with this amounts of frequency offset, and this voltage change is sent to VCXO;

S223, VCXO receive described voltage change and carry out the frequency adjustment according to this voltage change, finish frequency offset correction.

10. according to claim 9 based on the Interference Cancellation realized of FPGA and the method for base station locking, it is characterized in that frequency deviation described in the described step S221 is estimated, adopted following formula:

Wherein, f is the frequency deviation estimated value, and k is shift register length, and Z is correlation.

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