CN102968956A - Scanning driver for active organic electroluminescent display and driving method thereof - Google Patents
Scanning driver for active organic electroluminescent display and driving method thereof Download PDFInfo
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- CN102968956A CN102968956A CN2012105053330A CN201210505333A CN102968956A CN 102968956 A CN102968956 A CN 102968956A CN 2012105053330 A CN2012105053330 A CN 2012105053330A CN 201210505333 A CN201210505333 A CN 201210505333A CN 102968956 A CN102968956 A CN 102968956A
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Abstract
The invention discloses a scanning driver for an active organic electroluminescent display. The scanning driver comprises N levels of unit scanning drivers, wherein each unit scanning driver comprises an input signal sampling module, a signal coupling module, a circuit output level, and a circuit charge discharge module. The scanning driver only needs thin film transistors of one transmission type, so that improvement optimization is made on aspects of reduction of electric leakage access and extra power consumption. Each unit scanning driver only needs one external input, one clock control wire, one positive wire and two negative power wires, so driving difficulty is greatly reduced. Moreover, the output end is directly connected with a direct-current power supply, so that a coupling effect which is generated to output-stage transistor stray capacitance by clock jump and power consumption which is generated by charge-discharge of a capacitor are avoided.
Description
Technical field
The present invention relates to the turntable driving technology of light emitting diode indicator, particularly the scanner driver of active organic electroluminescent display and driving method thereof.
Background technology
Organic Light Emitting Diode (Organic Light Emitting Diode, OLED) display is the display technique of future generation that has very much development potentiality.Scanner driver scans every delegation pixel, guarantees that the every frame data of display upgrade.For the active organic LED display, each image element circuit needs peripheral sweep signal control luma data to write and upgrades, and realizes Presentation Function, is the indispensable part of active demonstration, the scanner driver technical indicator mainly contains: speed, power consumption and driving force etc.
Traditional scanner driver adopts CMOS technique, is made into chip, then by the COG machine chip is pressed in the contact-key of display periphery.Because chip cost is high, it is large that chip area and array lead-in wire consume area, needs specific COG machine to press chip, causes the very large cost consumption of whole process, and be unfavorable for realizing narrow frame, do not meet the human eye aesthetic conceptions.
Along with the development of display technique, more and more higher to the requirement of scanner driver, not only on function, to meet the demand of driving, it is fewer and feweri also will to consume area, realizes flexible or folding.The integrated scanning driver becomes the focus of nearest research on active organic light emitting diode display glass substrate, integrated scanning driver on glass substrate, not only reduce cost, reduce substrate area consumption, reduce processing step, can also be produced on scanner driver on the flexible base, board, realize flexible the demonstration.But the problem that the thing followed has to solve, the thin film transistor (TFT) of making on the glass substrate, mobility is low, and transport-type is single, full N-type or full P type pipe, the problems such as threshold voltage shift can appear in long-time making alive, can make the scanner driver malfunction, power consumption sudden change, output voltage swing some destructive results such as diminish, therefore when the design scanner driver, also be a very large challenge.
Summary of the invention
For the above-mentioned shortcoming and deficiency that overcomes prior art, the object of the present invention is to provide a kind of scanner driver of active organic electroluminescent display, only the scanner driver of the active organic electroluminescent display of the thin film transistor (TFT) of a kind of transport-type of need.
Another object of the present invention is to provide the driving method of above-mentioned source display of organic electroluminescence.
Purpose of the present invention is achieved through the following technical solutions:
The scanner driver of active organic electroluminescent display comprises N level unit scan driver; Each unit scan driver comprises an input end IN, a clock signal input terminal CLK, a reset terminal RESET, the first output terminal COUT and the second output terminal OUT; The input end IN of first order unit scan driver receives the beginning input signal; The output signal of the first output terminal COUT of the 1st ~ N-1 level unit scan driver is as the input signal of next stage unit scan input end IN; The output signal of the first output terminal COUT of the 2nd ~ N level unit scan driver is as the enabling signal of upper level unit scan driver reset terminal RESET;
Each unit scan driver comprises:
The input sample module comprises the first, second, third and the 4th transistor; Wherein first, second transistor conducting when the clock noble potential is controlled the 3rd, the 4th transistor turns situation, thereby input signal is sampled;
The signal coupling module comprises the 5th transistor and a capacitor C p, and sampled signal is controlled the 5th transistorized conducting state, and capacitor C p is according to the clock signal sampled signal that is coupled, the control output signal;
The output stage of circuit comprises the the the 6th, the 7th, the 8th, the 9th, the tenth, the 11 transistor; Wherein the six, the seven transistor consists of not gate, anti-phase for sampled signal; Eight, the 9th, the tenth, the 11 transistor consists of two output terminals, the 8th, the tenth transistor connects positive supply, and high level output is provided; Nine, the 11 transistor connects respectively two negative levels, and the output of negative level is provided;
Circuit charge discharging resisting module comprises the 12, the 13, the 14, the 15 transistor; The 12, the 13, the 14, the 15 transistor consists of maintenance and the bleed-off circuit to sampled signal, and the 13 transistor is controlled by input signal, and when guaranteeing the input signal high level, output stage is low level; The 12, the 14, the 15 transistor is controlled by the output signal of next stage unit scan driver, when the output signal of next stage scanner driver when being high, and the 12, the 14, the 15 transistor turns, the electric charge of releasing.
For the 1st ~ N level unit scan driver: the source electrode of the first transistor connects drain electrode and the 3rd transistorized grid of transistor seconds, and the grid of the first transistor connects the clock control line, and the first transistor drain electrode connects the input signal cable of this grade unit scan driver; The grid of transistor seconds connects the clock control line, and the source electrode of transistor seconds connects the drain electrode of the 4th transistorized grid and the tenth two-transistor; The 3rd transistorized drain electrode connects positive power line, and the 3rd transistorized source electrode connects the 4th transistor drain; The 4th transistorized source electrode connects the 13, the 14 transistorized drain electrode, and the end of the the the 5th, the 7th, the 8th, the tenth transistorized grid and capacitor C p;
The 5th transistorized drain electrode connects clock signal, and the 5th transistorized source electrode connects the 15 transistorized drain electrode, and the other end of capacitor C p;
The 6th transistorized drain and gate meets positive supply VDD, and the 6th transistorized source electrode connects the 7th transistorized drain electrode and the 9th, the 11 transistorized grid; The 7th transistorized source electrode meets the first negative supply VSSL; The 8th transistorized drain electrode meets positive supply VDD; The 9th transistorized source electrode meets the first negative supply VSSL, and the tenth transistorized drain electrode meets positive supply VDD, and the 11 transistorized source electrode meets the second negative supply VSS;
The grid of the tenth two-transistor connects the RESET signal of next stage unit scan driver output, and the source electrode of the tenth two-transistor meets the second negative supply VSS; The 13 transistor gate connects the input signal cable of this grade scanner driver, and source electrode meets the first negative supply VSSL; The 14 transistorized source electrode meets the first negative supply VSSL, and the 15 transistorized source electrode meets the second negative supply VSS;
To the 1st grade of unit scan driver: the 8th transistorized source electrode connects the 9th transistorized drain electrode, and the input end of next stage unit scan driver; The tenth transistorized source electrode connects the 11 transistorized drain electrode and pel array; The 14 transistorized grid connects the RESET signal of next stage unit scan driver output;
For N level unit scan driver: the 8th transistorized source electrode connects the 9th transistorized drain electrode, and the RESET of upper level unit scan driver end; The tenth transistorized source electrode connects the 11 transistorized drain electrode;
For the 2nd ~ N-1 level unit scan driver; The 8th transistorized source electrode connects the 9th transistorized drain electrode, and the RESET of upper level unit scan driver end, the input end of next stage unit scan driver; The tenth transistorized source electrode connects the 11 transistorized drain electrode and pel array; The 14 transistorized grid connects the RESET signal of next stage unit scan driver output; The 15 transistorized grid connects the RESET signal of next stage unit scan driver output.
The first ~ 15 transistor in the described unit scan driver is the N-type transistor.
The driving method of the scanner driver of described active organic electroluminescent display may further comprise the steps:
The front semiperiod of clock signal is low level, and second cycle is high level; The pulse width of VIN signal is the clock signal of one-period;
In the n cycle of clock signal, when clock signal saltus step high level, n level unit scan driver receives input signal, begins to carry out the input sample stage;
Enter n+1 during the cycle in clock signal, n level unit scan driver finishes the input sample stage, carries out signal coupling output; Simultaneously, n+1 level unit scan driver begins to carry out the input sample stage when clock signal enters second cycle in n+1 cycle take the output signal of the first output terminal COUT of n level unit scan driver as input signal;
In the n+2 cycle of clock signal, n+1 level unit scan driver finishes the input sample stage, carries out the signal coupling output stage; Simultaneously, n level unit scan driver is with the output signal of the first output terminal COUT of the n+1 level unit scan driver enabling signal as reset terminal RESET, the first output terminal COUT of n level unit scan driver and the output signal of the second output terminal OUT all are set to negative potential, begin to carry out signal and release the stage; N=1 wherein ... N-1.
Compared with prior art, the present invention has the following advantages and beneficial effect:
1, the scanner driver of active organic electroluminescent display of the present invention only needs a kind of thin film transistor (TFT) of transport-type, can satisfy the driving demand of display, in the scope of threshold voltage shift, normal operation, and have less electric leakage path, can reduce extra power consumption.
2, the unit scan driver of the scanner driver of active organic electroluminescent display of the present invention, only need peripheral input, a clock control line, one positive power line, article two, negative power line lowers the driving difficulty greatly, and output terminal access direct supply, the coupling effect of having avoided the clock saltus step that the output stage transistor stray capacitance is produced, and the power consumption that produces of capacitor charge and discharge.
Description of drawings
Fig. 1 is the integral body signal schematic diagram of the scanner driver of active organic electroluminescent display of the present invention.
Fig. 2 is the sequential chart of the scanner driver of active organic electroluminescent display of the present invention.
Fig. 3 is the schematic diagram of the unit scan driver of active organic electroluminescent display of the present invention.
Fig. 4 is the sequential chart of the unit scan driver of active organic electroluminescent display of the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment
As shown in Figure 1, the scanner driver of active organic electroluminescent display comprises N level unit scan driver (the 1st grade of unit scan driver 11, the 2nd grade of unit scan driver 12 shown in the figure; 3rd level unit scan driver 13; The 4th grade of unit scan driver 14; The 5th grade of unit scan driver 15; The 6th grade of unit scan driver 16); Each unit scan driver comprises an input end IN, a clock signal input terminal CLK, a reset terminal RESET, the first output terminal COUT and the second output terminal OUT; The input end IN of first order unit scan driver receives the beginning input signal; The output signal of the first output terminal COUT of the 1st ~ N-1 level unit scan driver is as the input signal of next stage unit scan driver input end IN; The output signal of the first output terminal COUT of the 2nd ~ N level unit scan driver is as the enabling signal of upper level unit scan driver reset terminal RESET; The second output terminal OUT(1 of 1 ~ N-1 level unit scan driver) ~ OUT(N-1) connect respectively sweep trace SCAN (1) ~ (N-1).
As shown in Figure 2, each unit scan driver comprises:
The output stage 03 of circuit comprises the 6th transistor T 6, the 7th transistor T 7, the 8th transistor T 8, the 9th transistor T 9, the tenth transistor T 10, the 11 transistor T 11; Wherein the six, the seven transistor consists of not gate, anti-phase for sampled signal; Eight, the 9th, the tenth, the 11 transistor consists of two output terminals, the 8th, the tenth transistor connects positive supply, and high level output is provided; Nine, the 11 transistor connects respectively two negative levels, and the output of negative level is provided;
Circuit charge discharging resisting module 04 comprises the tenth two-transistor T12, the 13 transistor T 13, the 14 transistor T 14, the 15 transistor T 15; The 12, the 13, the 14, the 15 transistor consists of maintenance and the bleed-off circuit to sampled signal, and the 13 transistor is controlled by input signal, and when guaranteeing the input signal high level, output stage is low level; The 12, the 14, the 15 transistor is controlled by the output signal of next stage unit scan driver, when the output signal of next stage scanner driver when being high, and the 12, the 14, the 15 transistor turns, the electric charge of releasing.
For the 1st ~ N level unit scan driver: the source electrode of the first transistor connects drain electrode and the 3rd transistorized grid of transistor seconds, and the grid of the first transistor connects the clock control line, and the first transistor drain electrode connects the input signal cable of this grade unit scan driver; The grid of transistor seconds connects the clock control line, and the source electrode of transistor seconds connects the drain electrode of the 4th transistorized grid and the tenth two-transistor; The 3rd transistorized drain electrode connects positive power line, and the 3rd transistorized source electrode connects the 4th transistor drain; The 4th transistorized source electrode connects the 13, the 14 transistorized drain electrode, and the end C of the the the 5th, the 7th, the 8th, the tenth transistorized grid and capacitor C p end;
The 5th transistorized drain electrode connects clock signal, and the 5th transistorized source electrode connects the 15 transistorized drain electrode, and the other end D of capacitor C p end;
The 6th transistorized drain and gate meets positive supply VDD, and the 6th transistorized source electrode connects the 7th transistorized drain electrode and the 9th, the 11 transistorized grid; The 7th transistorized source electrode meets the first negative supply VSSL; The 8th transistorized drain electrode meets positive supply VDD; The 9th transistorized source electrode meets the first negative supply VSSL, and the tenth transistorized drain electrode meets positive supply VDD, and the 11 transistorized source electrode meets the second negative supply VSS;
The grid of the tenth two-transistor connects the RESET signal of next stage unit scan driver output, and the source electrode of the tenth two-transistor meets the second negative supply VSS; The 13 transistor gate connects the input signal cable of this grade scanner driver, and source electrode meets the first negative supply VSSL; The 14 transistorized source electrode meets the first negative supply VSSL, and the 15 transistorized source electrode meets the second negative supply VSS;
To the 1st grade of unit scan driver: the 8th transistorized source electrode connects the 9th transistorized drain electrode, and the input end of next stage unit scan driver; The tenth transistorized source electrode connects the 11 transistorized drain electrode and pel array; The 14 transistorized grid connects the RESET signal of next stage unit scan driver output;
For N level unit scan driver: the 8th transistorized source electrode connects the 9th transistorized drain electrode, and the RESET of upper level unit scan driver end; The tenth transistorized source electrode connects the 11 transistorized drain electrode;
For the 2nd ~ N-1 level unit scan driver; The 8th transistorized source electrode connects the 9th transistorized drain electrode, and the RESET of upper level unit scan driver end, the input end of next stage unit scan driver; The tenth transistorized source electrode connects the 11 transistorized drain electrode and pel array; The 14 transistorized grid connects the RESET signal of next stage unit scan driver output; The 15 transistorized grid connects the RESET signal of next stage unit scan driver output.
The first ~ 15 transistor in the said units scanner driver is the N-type transistor.
As shown in Figure 3, the driving method of the scanner driver of the active organic electroluminescent display of present embodiment may further comprise the steps:
The front semiperiod of clock signal is low level, and second cycle is high level; The pulse width of VIN signal is the clock signal of one-period; In the n cycle of clock signal, when clock signal saltus step high level, n level unit scan driver receives input signal, begins to carry out the input sample stage; Enter n+1 during the cycle in clock signal, n level unit scan driver finishes the input sample stage, carries out signal coupling output; Simultaneously, n+1 level unit scan driver begins to carry out the input sample stage when clock signal enters second cycle in n+1 cycle take the output signal of the first output terminal COUT (n) of n level unit scan driver as input signal; In the n+2 cycle of clock signal, n+1 level unit scan driver finishes the input sample stage, carries out the signal coupling output stage; Simultaneously, n level unit scan driver is with the output signal of the first output terminal COUT (n+1) of the n+1 level unit scan driver enabling signal as reset terminal RESET, the first output terminal COUT(n of n level unit scan driver) and the second output terminal OUT(n) output signal all be set to negative potential, begin to carry out signal and release the stage; N=1 wherein ... N-1.
As shown in Figure 4, the input sample stage is specially: clock control line traffic control the first and second transistorized on off states, clock signal is by high level step-down level, input signal uprises level by low level, this moment first, transistor seconds turn-offs, A, 2 of B keep low level to keep the 3rd, the 4th transistor off state, the 13 transistor turns, C point current potential is pulled down to the first negative supply VSSL, the so that the 5th, the 7th, the the 8th and the tenth transistor is closed, E is charged to positive supply VDD through the 6th transistor, so that the 9th and the 11 transistor turns, output signal is low level; Input signal continues to keep high level, clock signal uprises level by low level, the simultaneously conducting of first, second transistor, 2 Gather and input signals of A, B, so that simultaneously conducting of the third and fourth transistor, because the 13 transistor is transfused to signal and opens, C point current potential is kept the level of the first negative supply VSSL, and output signal keeps low level state.
As shown in Figure 4, the signal coupling output stage: when input signal by high level step-down level, clock signal is also by high level step-down level, so first, second, the 13 transistor all turn-offs, A, 2 of B keep high level, the third and fourth transistor keeps conducting state, positive supply VDD is charged to the positive supply level to the C point, simultaneously the 5th transistor is opened, and capacitor C p is keeping C point current potential, this moment the 8th transistor and the tenth transistor turns, the 7th transistor turns, E point current potential is pulled down to the first negative supply VSSL level, so that the 9th and the 11 transistor is closed, positive supply VDD charges to output terminal by the 8th and the tenth transistor, the output high level; When input signal keeps low level, clock signal is also uprised by low, the 5th transistor continues to keep conducting, the the 9th and the 11 transistor keeps closing, clock signal is to the D end charging of capacitor C p, C point thereupon saltus step is higher level, so that the 8th transistor and the tenth transistor have better conducting state, so that the level of output terminal COUT and OUT equals the positive supply level.
As shown in Figure 4, signal is released the stage: input signal continues to keep low level, the signal of this one-level unit scan driver of output RESET signal back of the next stage unit scan driver module of releasing, open the 12, the 14, the 15 transistor, with the B point, the C point, charge discharging resisting to the first negative voltage VSSL on the D point, with the second negative voltage VSS, while E point potential rise, the the 9th and the 11 transistor is opened, and output terminal COUT current potential is pulled down to the first negative voltage VSSL, and OUT is pulled down to the second negative voltage VSS.
Above-described embodiment is the better embodiment of the present invention; but embodiments of the present invention are not limited by the examples; other any do not deviate from change, the modification done under Spirit Essence of the present invention and the principle, substitutes, combination, simplify; all should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (4)
1. the scanner driver of active organic electroluminescent display is characterized in that, comprises N level unit scan driver; Each unit scan driver comprises an input end IN, a clock signal input terminal CLK, a reset terminal RESET, the first output terminal COUT and the second output terminal OUT; The input end IN of first order unit scan driver receives the beginning input signal; The output signal of the first output terminal COUT of the 1st ~ N-1 level unit scan driver is as the input signal of the input end IN of next stage unit scan driver; The output signal of the first output terminal COUT of the 2nd ~ N level unit scan driver is as the enabling signal of upper level unit scan driver reset terminal RESET;
Each unit scan driver comprises:
The input sample module comprises the first, second, third and the 4th transistor; Wherein first, second transistor conducting when the clock noble potential is controlled the 3rd, the 4th transistor turns situation, thereby input signal is sampled;
The signal coupling module comprises the 5th transistor and a capacitor C p, and sampled signal is controlled the 5th transistorized conducting state, and capacitor C p is according to the clock signal sampled signal that is coupled, the control output signal;
The output stage of circuit comprises the the the 6th, the 7th, the 8th, the 9th, the tenth, the 11 transistor; Wherein the six, the seven transistor consists of not gate, anti-phase for sampled signal; Eight, the 9th, the tenth, the 11 transistor consists of two output terminals, the 8th, the tenth transistor connects positive supply, and high level output is provided; Nine, the 11 transistor connects respectively two negative levels, and the output of negative level is provided;
Circuit charge discharging resisting module comprises the 12, the 13, the 14, the 15 transistor; The 12, the 13, the 14, the 15 transistor consists of maintenance and the bleed-off circuit to sampled signal, and the 13 transistor is controlled by input signal, and when guaranteeing the input signal high level, output stage is low level; The 12, the 14, the 15 transistor is controlled by the output signal of next stage unit scan driver, when the output signal of next stage scanner driver when being high, and the 12, the 14, the 15 transistor turns, the electric charge of releasing.
2. the scanner driver of active organic electroluminescent display according to claim 1 is characterized in that,
For the 1st ~ N level unit scan driver: the source electrode of the first transistor connects drain electrode and the 3rd transistorized grid of transistor seconds, and the grid of the first transistor connects the clock control line, and the first transistor drain electrode connects the input signal cable of this grade unit scan driver; The grid of transistor seconds connects the clock control line, and the source electrode of transistor seconds connects the drain electrode of the 4th transistorized grid and the tenth two-transistor; The 3rd transistorized drain electrode connects positive power line, and the 3rd transistorized source electrode connects the 4th transistor drain; The 4th transistorized source electrode connects the 13, the 14 transistorized drain electrode, and the end of the the the 5th, the 7th, the 8th, the tenth transistorized grid and capacitor C p;
The 5th transistorized drain electrode connects clock signal, and the 5th transistorized source electrode connects the 15 transistorized drain electrode, and the other end of capacitor C p;
The 6th transistorized drain and gate meets positive supply VDD, and the 6th transistorized source electrode connects the 7th transistorized drain electrode and the 9th, the 11 transistorized grid; The 7th transistorized source electrode meets the first negative supply VSSL; The 8th transistorized drain electrode meets positive supply VDD; The 9th transistorized source electrode meets the first negative supply VSSL, and the tenth transistorized drain electrode meets positive supply VDD, and the 11 transistorized source electrode meets the second negative supply VSS;
The grid of the tenth two-transistor connects the RESET signal of next stage unit scan driver output, and the source electrode of the tenth two-transistor meets the second negative supply VSS; The 13 transistor gate connects the input signal cable of this grade scanner driver, and source electrode meets the first negative supply VSSL; The 14 transistorized source electrode meets the first negative supply VSSL, and the 15 transistorized source electrode meets the second negative supply VSS;
To the 1st grade of unit scan driver: the 8th transistorized source electrode connects the 9th transistorized drain electrode, and the input end of next stage unit scan driver; The tenth transistorized source electrode connects the 11 transistorized drain electrode and pel array; The 14 transistorized grid connects the RESET signal of next stage unit scan driver output;
For N level unit scan driver: the 8th transistorized source electrode connects the 9th transistorized drain electrode, and the RESET of upper level unit scan driver end; The tenth transistorized source electrode connects the 11 transistorized drain electrode;
For the 2nd ~ N-1 level unit scan driver; The 8th transistorized source electrode connects the 9th transistorized drain electrode, and the RESET of upper level unit scan driver end, the input end of next stage unit scan driver; The tenth transistorized source electrode connects the 11 transistorized drain electrode and pel array; The 14 transistorized grid connects the RESET signal of next stage unit scan driver output; The 15 transistorized grid connects the RESET signal of next stage unit scan driver output.
3. the scanner driver of active organic electroluminescent display according to claim 1 is characterized in that, the first ~ 15 transistor in the described unit scan driver is the N-type transistor.
4. the driving method of the scanner driver of active organic electroluminescent display as claimed in claim 1 is characterized in that, may further comprise the steps:
The front semiperiod of clock signal is low level, and second cycle is high level; The pulse width of VIN signal is the clock signal of one-period;
In the n cycle of clock signal, when clock signal saltus step high level, n level unit scan driver receives input signal, begins to carry out the input sample stage;
Enter n+1 during the cycle in clock signal, n level unit scan driver finishes the input sample stage, carries out signal coupling output; Simultaneously, n+1 level unit scan driver begins to carry out the input sample stage when clock signal enters second cycle in n+1 cycle take the output signal of the first output terminal COUT of n level unit scan driver as input signal;
In the n+2 cycle of clock signal, n+1 level unit scan driver finishes the input sample stage, carries out the signal coupling output stage; Simultaneously, n level unit scan driver is with the output signal of the first output terminal COUT of the n+1 level unit scan driver enabling signal as reset terminal RESET, the first output terminal COUT of n level unit scan driver and the output signal of the second output terminal OUT all are set to negative potential, begin to carry out signal and release the stage; N=1 wherein ... N-1.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103927972A (en) * | 2013-12-05 | 2014-07-16 | 华南理工大学 | Grid drive unit, grid scanning driver and driving method of grid scanning driver |
| CN104575435A (en) * | 2015-02-05 | 2015-04-29 | 京东方科技集团股份有限公司 | Display substrate gate line drive method as well as display substrate gate line drive unit and display device |
| CN106297726A (en) * | 2016-09-08 | 2017-01-04 | 京东方科技集团股份有限公司 | Sampling hold circuit, discharge control method and display device |
| CN115862514A (en) * | 2022-12-16 | 2023-03-28 | Tcl华星光电技术有限公司 | Grid driving circuit and display panel |
| CN116168658A (en) * | 2023-02-20 | 2023-05-26 | 深圳新视光电科技有限公司 | LCD color difference adjusting method, device, equipment and medium based on radial reflection |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1705042A (en) * | 2004-05-31 | 2005-12-07 | Lg.菲利浦Lcd株式会社 | Shift register |
| CN1921016A (en) * | 2005-08-22 | 2007-02-28 | 三星Sdi株式会社 | Shift register circuit |
| US20070274433A1 (en) * | 2006-05-25 | 2007-11-29 | Mitsubishi Electric Corporation | Shift register circuit and image display apparatus equipped with the same |
-
2012
- 2012-11-30 CN CN201210505333.0A patent/CN102968956B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1705042A (en) * | 2004-05-31 | 2005-12-07 | Lg.菲利浦Lcd株式会社 | Shift register |
| CN1921016A (en) * | 2005-08-22 | 2007-02-28 | 三星Sdi株式会社 | Shift register circuit |
| US20070274433A1 (en) * | 2006-05-25 | 2007-11-29 | Mitsubishi Electric Corporation | Shift register circuit and image display apparatus equipped with the same |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103927972A (en) * | 2013-12-05 | 2014-07-16 | 华南理工大学 | Grid drive unit, grid scanning driver and driving method of grid scanning driver |
| CN103927972B (en) * | 2013-12-05 | 2016-03-02 | 华南理工大学 | Drive element of the grid and gated sweep driver and driving method thereof |
| CN104575435A (en) * | 2015-02-05 | 2015-04-29 | 京东方科技集团股份有限公司 | Display substrate gate line drive method as well as display substrate gate line drive unit and display device |
| CN106297726A (en) * | 2016-09-08 | 2017-01-04 | 京东方科技集团股份有限公司 | Sampling hold circuit, discharge control method and display device |
| CN106297726B (en) * | 2016-09-08 | 2018-10-23 | 京东方科技集团股份有限公司 | Sampling hold circuit, discharge control method and display device |
| CN115862514A (en) * | 2022-12-16 | 2023-03-28 | Tcl华星光电技术有限公司 | Grid driving circuit and display panel |
| CN115862514B (en) * | 2022-12-16 | 2024-03-15 | Tcl华星光电技术有限公司 | Gate driving circuit and display panel |
| CN116168658A (en) * | 2023-02-20 | 2023-05-26 | 深圳新视光电科技有限公司 | LCD color difference adjusting method, device, equipment and medium based on radial reflection |
| CN116168658B (en) * | 2023-02-20 | 2023-08-15 | 深圳新视光电科技有限公司 | LCD color difference adjusting method, device, equipment and medium based on radial reflection |
| CN116682355A (en) * | 2023-07-06 | 2023-09-01 | 上海和辉光电股份有限公司 | Scanning control line driving module and display panel |
| CN116682355B (en) * | 2023-07-06 | 2023-11-28 | 上海和辉光电股份有限公司 | Scanning control line driving module and display panel |
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| CN102968956B (en) | 2014-12-31 |
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