CN102968956A - Scanning driver for active organic electroluminescent display and driving method thereof - Google Patents

Scanning driver for active organic electroluminescent display and driving method thereof Download PDF

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CN102968956A
CN102968956A CN2012105053330A CN201210505333A CN102968956A CN 102968956 A CN102968956 A CN 102968956A CN 2012105053330 A CN2012105053330 A CN 2012105053330A CN 201210505333 A CN201210505333 A CN 201210505333A CN 102968956 A CN102968956 A CN 102968956A
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transistor
scan driver
signal
connected
output
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CN2012105053330A
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CN102968956B (en
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吴为敬
张立荣
周雷
徐苗
王磊
彭俊彪
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华南理工大学
广州新视界光电科技有限公司
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Abstract

The invention discloses a scanning driver for an active organic electroluminescent display. The scanning driver comprises N levels of unit scanning drivers, wherein each unit scanning driver comprises an input signal sampling module, a signal coupling module, a circuit output level, and a circuit charge discharge module. The scanning driver only needs thin film transistors of one transmission type, so that improvement optimization is made on aspects of reduction of electric leakage access and extra power consumption. Each unit scanning driver only needs one external input, one clock control wire, one positive wire and two negative power wires, so driving difficulty is greatly reduced. Moreover, the output end is directly connected with a direct-current power supply, so that a coupling effect which is generated to output-stage transistor stray capacitance by clock jump and power consumption which is generated by charge-discharge of a capacitor are avoided.

Description

有源有机电致发光显示器的扫描驱动器及其驱动方法 Active scanning drive the organic electroluminescent display and a driving method

技术领域 FIELD

[0001] 本发明涉及发光二极管显示器的扫描驱动技术,特别涉及有源有机电致发光显示器的扫描驱动器及其驱动方法。 [0001] The present invention relates to a scan driving light emitting diode display technology, particularly relates to an active scanning driver and a driving method of an organic electroluminescent display.

背景技术 Background technique

[0002] 有机发光二极管(Organic Light Emitting Diode,0LED)显示器是非常具有发展潜力的下一代显示技术。 [0002] The organic light emitting diode (Organic Light Emitting Diode, 0LED) display is very promising next-generation display technology. 扫描驱动器,扫描每一行像素,保证显示器每帧数据更新。 A scan driver scans each row of pixels, to ensure that the display data of each frame update. 对于有源有机发光二极管显示器来说,每个像素电路需要外围扫描信号控制灰阶数据写入和更新,并实现显示功能,是有源显示不可缺少的一部分,扫描驱动器技术指标主要有:速度,功耗以及驱动能力等。 For an active organic light emitting diode display, each pixel circuit requires a peripheral scan signal controlling the gray scale data written and updated, and to realize the display function, is an integral part of the active display, the scan driver Specifications are: speed, power consumption and driving ability.

[0003] 传统的扫描驱动器采用CMOS工艺,制作成芯片,然后通过COG机器将芯片压在显示器外围的接触键。 [0003] The conventional scan driver using CMOS technology, made into chips, the chip is then pressed by COG machine in the periphery of the display touch keys. 由于芯片成本高,芯片面积和阵列引线消耗面积大,需要特定的COG机器压芯片,造成整个过程非常大的成本消耗,并且不利于实现窄边框,不符合人眼审美观。 Due to the high cost of chip, chip area and a large area array lead consumption, requires a specific machine pressure COG chip, causing the whole process consumes a very large cost, and not conducive to a narrow frame, does not meet the aesthetic eye.

[0004] 随着显示技术的发展,对扫描驱动器的要求越来越高,不仅在功能上要符合驱动的需求,还要消耗面积越来越少,实现可弯曲或者折叠。 [0004] With the development of display technologies, a requirement for increasing the scan driver, not only in function to meet the needs of the drive, but also consumes less area, may be bent or folded to achieve. 在有源有机发光二级管显示器玻璃基板上集成扫描驱动器成为最近研究的热点,在玻璃基板上集成扫描驱动器,不仅降低成本,减少基板面积消耗,减少工艺步骤,还可以把扫描驱动器制作在柔性基板上,实现柔性显示。 On the active organic light emitting diode display glass substrate integrated scan driver become the focus of recent studies, the integrated scan driver on a glass substrate, not only reduce the cost and board area consumption, reduced processing steps, but also can scan driver fabricated flexible on the substrate to realize a flexible display. 但是随之而来的不得不解决的问题,玻璃基板上制作的薄膜晶体管,迁移率低,传输类型单一,全N型或者是全P型管,长时间加电压会出现阈值电压漂移等问题,会使扫描驱动器功能失常,功耗突变,输出摆幅变小等一些毁灭性的结果,因此在设计扫描驱动器时,也是一个非常大的挑战。 But the attendant problems have to be solved, the thin film transistors on a glass substrate, low mobility, a single transmission type, N-type or full full P-tube, problems occur protracted voltage threshold voltage drift, It will scan driver dysfunction, sudden change in output swing is small and some devastating results, so in the design of the scan driver, is also a very big challenge.

发明内容 SUMMARY

[0005] 为了克服现有技术的上述缺点与不足,本发明的目的在于提供一种有源有机电致发光显示器的扫描驱动器,只需一种传输类型的薄膜晶体管的有源有机电致发光显示器的扫描驱动器。 [0005] In order to overcome the above disadvantages and deficiencies of the prior art, an object of the present invention to provide an active scanning drive the organic electroluminescent display, a thin film transistor active-only type of transmission of an organic electroluminescent display the scan driver.

[0006] 本发明的另一目的在于提供上述源有机电致发光显示器的驱动方法。 [0006] Another object of the present invention is to provide a driving source of the above-described organic electroluminescent display.

[0007] 本发明的目的通过以下技术方案实现: [0007] The object of the present invention is achieved by the following technical solution:

[0008] 有源有机电致发光显示器的扫描驱动器,包括N级单元扫描驱动器;每个单元扫描驱动器包括一个输入端IN, —个时钟信号输入端CLK, 一个复位端RESET,第一输出端COUT和第二输出端OUT ;第一级单兀扫描驱动器的输入端IN接收开始输入信号;第NI级单兀扫描驱动器的第一输出端COUT的输出信号作为下一级单兀扫描输入端IN的输入信号;第2、级单兀扫描驱动器的第一输出端COUT的输出信号作为上一级单兀扫描驱动器复位端RESET的启动信号; [0008] The active organic electroluminescent scan driver light emitting display, comprising N-stage unit scan driver; each unit of the scan driver includes an input terminal IN, - a clock signal input of the CLK, a reset terminal the RESET, a first output terminal COUT and a second output terminal OUT; Wu single input of the first stage of the scan driver start terminal iN receives an input signal; a first output signal of the output of the single stage NI Wu scan driver Wu COUT as a single scan input terminal iN of the next stage an input signal; a first output terminal an output signal of a second, single-stage scan driver Wu COUT as on a single scan driver Wu reset terminal rESET of the start signal;

[0009] 每个单元扫描驱动器包括: [0009] The scan driver unit each comprises:

[0010] 输入采样模块,包括第一、第二、第三和第四晶体管;其中第一、第二晶体管在时钟高电位时导通,控制第三、第四晶体管导通情况,从而对输入信号采样; [0010] The input sampling module comprising a first, second, third and fourth transistors; wherein the first, the second transistor is turned on when the clock a high potential, controlling the third, the fourth transistor is turned on, the input thereby signal samples;

[0011] 信号耦合模块包括第五晶体管和一个电容Cp,采样信号控制第五晶体管的导通状态,电容Cp根据时钟信号耦合采样信号,控制输出信号; [0011] The signal coupling module comprises a fifth transistor and a capacitor Cp, the sampling signal controls the conduction state of the fifth transistor, the capacitance Cp sampling signal coupled to the clock signal, the control output signal;

[0012] 电路的输出级包括第六、第七、第八、第九、第十、第十一晶体管;其中第六,第七晶体管构成非门,为采样信号的反相;第八、第九、第十、第十一晶体管构成两个输出端,第八、第十晶体管接正电源,提供高电平输出;第九、第十一晶体管分别接两个负电平,提供负电平的输出; [0012] The output stage circuit comprises a sixth, seventh, eighth, ninth, tenth, eleventh transistor; wherein the sixth, seventh transistors constituting the NAND gate, is inverted sampled signal; eighth, nine, tenth, eleventh transistor two output terminals, eighth, tenth transistor connected to the positive power supply, a high-level output; the ninth, eleventh transistors respectively connected to two negative level, providing a negative output level ;

[0013] 电路电荷泄放模块包括第十二、第十三、第十四、第十五晶体管;第十二、第十三、第十四、第十五晶体管构成对采样信号的保持和泄放回路,第十三晶体管受输入信号控制,确保输入信号高电平时,输出级为低电平;第十二、第十四、第十五晶体管受下一级单元扫描驱动器的输出信号控制,当下一级扫描驱动器的输出信号为高时,第十二、第十四、第十五晶体管导通,泄放电荷。 [0013] bleed circuit module comprises a charge twelfth, thirteenth, fourteenth, fifteenth transistor; the twelfth, thirteenth, fourteenth, fifteenth transistor constituting the signal sampled and held vent back when the road, the thirteenth transistor controlled by the input signal, the input signal to ensure a high level, the output level is low; the twelfth, fourteenth, fifteenth transistor controlled by the output signal of a scan driver unit, an output signal of the lower scan driver is high, twelfth, fourteenth, fifteenth transistor is turned on, a charge bleed.

[0014] 对于第I、级单元扫描驱动器:第一晶体管的源极接第二晶体管的漏极和第三晶体管的栅极,第一晶体管的栅极接时钟控制线,第一晶体管漏极接该级单元扫描驱动器的输入信号线;第二晶体管的栅极接时钟控制线,第二晶体管的源极接第四晶体管的栅极和第十二晶体管的漏极;第三晶体管的漏极接正电源线,第三晶体管的源极接第四晶体管漏极;第四晶体管的源极接第十三、第十四晶体管的漏极,以及第五、第七、第八、第十晶体管的栅极和电容Cp的一端; [0014] For Group I, a scan driver stage unit: the source of the first transistor to the gate of the second transistor and the drain of the third transistor, a gate connected to the clock control line of the first transistor, the first transistor drain connected the stage unit of the scan driver input signal line; clock source control line connected to a gate of the second transistor, the second transistor to the drain of the fourth transistor and the gate of the twelfth transistor; drain of the third transistor is coupled positive power source line, a source of the third transistor being connected the drain of the fourth transistor; the fourth source of the thirteenth transistor being connected, the drain of the fourteenth transistor, and a fifth, seventh, eighth, tenth transistor end of the gate and capacitor Cp;

[0015] 第五晶体管的漏极接时钟信号,第五晶体管的源极接第十五晶体管的漏极,以及电容Cp的另一端; A drain connected to the source and drain of the clock signal [0015] of the fifth transistor, the fifth transistor is connected to a fifteenth transistor, and the other end of the capacitor Cp;

[0016] 第六晶体管的漏极和栅极接正电源VDD,第六晶体管的源极接第七晶体管的漏极以及第九、第十一晶体管的栅极;第七晶体管的源极接第一负电源VSSL ;第八晶体管的漏极接正电源VDD ;第九晶体管的源极接第一负电源VSSL,第十晶体管的漏极接正电源VDD,第十一晶体管的源极接第二负电源VSS ; [0016] The drain and gate of the sixth transistor is connected to the positive supply the VDD, a source connected to the drain of the sixth transistor and a gate of the seventh transistor, ninth, eleventh transistor; a source of the seventh transistor being connected a negative power source VSSL; drain of the eighth transistor is connected to the positive supply the VDD; source of the ninth transistor is connected to a first negative power source VSSL, the drain of the tenth transistor is connected to the positive power supply VDD, a source connected to a second electrode of the eleventh transistor the VSS negative power supply;

[0017] 第十二晶体管的栅极接下一级单元扫描驱动器输出的RESET信号,第十二晶体管的源极接第二负电源VSS;第十三晶体管栅极接该级扫描驱动器的输入信号线,源极接第一负电源VSSL ;第十四晶体管的源极接第一负电源VSSL,第十五晶体管的源极接第二负电源VSS ; A gate [0017] Continued twelfth transistor unit scans a driver output RESET signal, a source connected to the second electrode of the twelfth transistor the VSS negative supply; a thirteenth transistor connected to the gate scan driver stage input signal line, a source connected to a first negative power source VSSL; source of the fourteenth transistor being connected VSSL first negative power supply, a source connected to the second electrode of the fifteenth transistor the VSS negative power supply;

[0018] 对第I级单元扫描驱动器:第八晶体管的源极接第九晶体管的漏极,以及下一级单元扫描驱动器的输入端;第十晶体管的源极接第十一晶体管的漏极以及像素阵列;第十四晶体管的栅极接下一级单元扫描驱动器输出的RESET信号; [0018] Level I of a scan driver unit: a source electrode connected to the drain of the eighth transistor, the ninth transistor, and an input terminal of the scan drive unit; a source electrode connected to the drain of the tenth transistor, the eleventh transistor and a pixel array; a gate of the fourteenth transistor means took a RESET signal output from the scan driver;

[0019] 对于第N级单元扫描驱动器:第八晶体管的源极接第九晶体管的漏极,以及上一级单元扫描驱动器的RESET端;第十晶体管的源极接第十一晶体管的漏极; [0019] For the N th scan drive unit: a source electrode connected to the drain of the eighth transistor, the ninth transistor, and a RESET terminal unit scans the driver; source of the tenth transistor being connected to the drain of the eleventh transistor ;

[0020] 对于第2〜NI级单元扫描驱动器;第八晶体管的源极接第九晶体管的漏极,以及上一级单元扫描驱动器的RESET端,下一级单元扫描驱动器的输入端;第十晶体管的源极接第十一晶体管的漏极以及像素阵列;第十四晶体管的栅极接下一级单元扫描驱动器输出的RESET信号;第十五晶体管的栅极接下一级单兀扫描驱动器输出的RESET信号。 [0020] For the first stage unit 2~NI scan driver; an eighth transistor source connected to the drain of the ninth transistor, and the drive unit scans a RESET terminal, the input terminal of one unit of the scan driver; X a source electrode connected to the drain of the transistor and a pixel array of the eleventh transistor; the gate of the fourteenth transistor means took a RESET signal output from the scan driver; a gate of the fifteenth transistor took a single scan driver Wu RESET signal output.

[0021] 所述单元扫描驱动器中的第一〜十五晶体管为N型晶体管。 The [0021] The scan driver unit of the first through fifth transistor and N-type transistors.

[0022] 所述的有源有机电致发光显示器的扫描驱动器的驱动方法,包括以下步骤:[0023] 时钟信号的前半周期为低电平,下半周期为高电平;VIN信号的脉冲宽度为一个周期的时钟信号; The active [0022] The driving method of an organic electroluminescent light emitting display scan driver, comprising the steps of: [0023] the first half cycle of the clock signal is low, half period is high; pulse width signal VIN a cycle of the clock signal;

[0024] 在时钟信号的第n周期,在时钟信号跳变高电平时,第n级单元扫描驱动器接收输入信号,开始进行输入采样阶段; [0024] In the n-th cycle of the clock signal, when the clock signal transitions high, the n-th scan driver stage unit receives an input signal, the input sampling stage is started;

[0025] 在时钟信号进入第n+1周期时,第n级单元扫描驱动器结束输入采样阶段,进行信号率禹合输出;同时,第n+1级单兀扫描驱动器以第n级单兀扫描驱动器的第一输出端COUT的输出信号为输入信号,在时钟信号进入第n+1周期的下半周期时开始进行输入采样阶段; [0025] When the clock signal entering the n + 1 cycle, the n-th stage unit scan driver ended input sampling stage, the signal rate and Yu output; the same time, the n + 1st single Wu scan driver to n-th single Wu scan a first output terminal of the output signal COUT to the driver input signal sampling stage is started when the clock input signal into the first n + 1 of the next half cycle;

[0026] 在时钟信号的第n+2周期,第n+1级单元扫描驱动器结束输入采样阶段,进行信号耦合输出阶段;同时,第n级单元扫描驱动器以第n+1级单元扫描驱动器的第一输出端COUT的输出信号作为复位端RESET的启动信号,第n级单元扫描驱动器的第一输出端COUT和第二输出端OUT的输出信号均被置位到负电位,开始进行信号泄放阶段;其中n=l-N_l。 [0026] In the n + 2 cycle of the clock signal, the n + 1 level means the scan driver ended input sampling stage, the signal coupling-out stage; the same time, the n-th stage unit scan driver in the + first-stage n 1 means the scan driver a first output terminal COUT output signal as an enabling signal to the reset terminal rESET, a first n-th stage output terminal COUT scan driver unit and the output signal a second output terminal OUT are set to a negative potential, the start signal bleed stage; where n = l-N_l.

[0027] 与现有技术相比,本发明具有以下优点和有益效果: [0027] Compared with the prior art, the present invention has the following advantages and benefits:

[0028] I、本发明的有源有机电致发光显示器的扫描驱动器,只需一种传输类型的薄膜晶体管,可以满足显示器的驱动需求,在阈值电压漂移的范围内,正常工作,并且具有较少的漏电通路,可以降低额外功耗。 [0028] I, the present invention, the active organic electroluminescent light emitting display scan driver, only one kind of transmission type thin film transistor, the drive to meet the needs of display, in the range of the threshold voltage shift, normal operation, and having relatively small leakage path, excess power consumption can be reduced.

[0029] 2、本发明的有源有机电致发光显示器的扫描驱动器的单元扫描驱动器,只需外围一个输入,一个时钟控制线,一正电源线,二条负电源线,大大减低驱动难度,并且输出端接入直流电源,避免了时钟跳变对输出级晶体管寄生电容所产生的耦合效应,和电容充放电所产生的功耗。 [0029] 2, the active of the present invention has a unit scan driver electroluminescent scan driver light emitting display, only the periphery of an input, a clock control line, a positive power source line, two negative power source line, greatly reducing the driving difficulty, and access to the output DC power, to avoid clock transition generated by the coupling effect of the parasitic capacitance of the output stage transistor is generated, and the capacitor charge and discharge power.

附图说明 BRIEF DESCRIPTION

[0030] 图I为本发明有源有机电致发光显示器的扫描驱动器的整体示意原理图。 [0030] Figure I of the present invention have an overall schematic diagram of the active actuator scan driver organic light emitting display.

[0031] 图2为本发明有源有机电致发光显示器的扫描驱动器的时序图。 [0031] There are a timing chart of FIG. 2 the active organic light emitting display scan driver actuator of the present invention.

[0032] 图3为本发明有源有机电致发光显示器的单元扫描驱动器的原理图。 [0032] FIG. 3 schematics active drive unit scans the organic electroluminescent display of the present invention.

[0033] 图4为本发明有源有机电致发光显示器的单元扫描驱动器的时序图。 [0033] FIG 4 the active unit has a timing chart of the scan driver of the organic electroluminescent display of the present invention.

具体实施方式 Detailed ways

[0034] 下面结合实施例及附图,对本发明作进一步地详细说明,但本发明的实施方式不限于此。 [0034] The following examples and the accompanying drawings in conjunction with embodiments of the present invention will be further described in detail, but the embodiment of the present invention is not limited thereto.

[0035] 实施例 [0035] Example

[0036] 如图I所示,有源有机电致发光显示器的扫描驱动器,包括N级单元扫描驱动器(图中示出第I级单元扫描驱动器11、第2级单元扫描驱动器12 ;第3级单元扫描驱动器13 ;第4级单元扫描驱动器14 ;第5级单元扫描驱动器15 ;第6级单元扫描驱动器16);每个单兀扫描驱动器包括一个输入端IN,—个时钟信号输入端CLK, 一个复位端RESET,第一输出端COUT和第二输出端OUT ;第一级单兀扫描驱动器的输入端IN接收开始输入信号;第I^NI级单兀扫描驱动器的第一输出端COUT的输出信号作为下一级单兀扫描驱动器输入端IN的输入信号;第2、级单元扫描驱动器的第一输出端COUT的输出信号作为上一级单元扫描驱动器复位端RESET的启动信号;rN-l级单元扫描驱动器的第二输出端OUT (I)〜OUT (NI)分别连接扫描线SCAN(ir(Nl)。 [0036] FIG I, the active scanning driver organic electroluminescence display, comprising N-stage unit scan driver (shown in stage I, means a scan driver 11, the second-stage unit scan driver 12; Level 3 unit scan driver 13; the fourth stage unit scan driver 14; level 5 unit scan driver 15; level 6 unit scan driver 16); each of the single Wu scan driver includes an input terminal IN, - a clock signal input terminal CLK, a reset terminal rESET, a first and a second output terminal COUT output terminal OUT; Wu single stage input terminal of the first scan driver receives a start input signal iN; I ^ a first output terminal COUT to output a first stage single NI Wu scan driver signal as the a single Wu scan driver input signal iN is input; a second output signal a first output terminal COUT of the stage unit scan driver as the one unit scan driver reset terminal rESET of the enable signal; rN-l grade a second scan driver unit output terminal OUT (I) ~OUT (NI) are connected to the scan line sCAN (ir (Nl).

[0037] 如图2所示,每个单元扫描驱动器包括: [0037] As shown, each scan drive unit 2 comprises:

[0038] 输入采样模块01,包括第一晶体管Tl、第二晶体管T2、第三晶体管T3和第四晶体管T4 ;中第一、第二晶体管在时钟高电位时导通,控制第三、第四晶体管导通情况,从而对输入信号米样; [0038] The input sampling module 01, includes a first transistor Tl, a second transistor T2, third transistor T3 and a fourth transistor T4; the first, the second transistor is turned on when the clock a high potential, controlling the third, fourth transistor is turned on, the rice so that an input signal sample;

[0039] 信号耦合模块02,包括第五晶体管T5和一个电容Cp,采样信号控制第五晶体管的导通状态,电容Cp根据时钟信号耦合采样信号,控制输出信号; [0039] The signal coupling module 02, includes a fifth transistor T5 and a capacitor Cp, the sampling signal controls the conduction state of the fifth transistor, the capacitance Cp sampling signal coupled to the clock signal, the control output signal;

[0040] 电路的输出级03,包括第六晶体管T6、第七晶体管17、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管Tll ;其中第六,第七晶体管构成非门,为采样信号的反相;第八、第九、第十、第十一晶体管构成两个输出端,第八、第十晶体管接正电源,提供高电平输出;第九、第十一晶体管分别接两个负电平,提供负电平的输出; The output stage 03 [0040] The circuit includes a sixth transistor T6, a seventh transistor 17, the eighth transistor T8, T9 ninth transistor, a tenth transistor T10, an eleventh transistor Tll; wherein the sixth, seventh transistor constituting a non- door, is inverted sampled signal; eighth, ninth, tenth, eleventh transistor two output terminals, eighth, tenth transistor connected to the positive power supply, a high-level output; the ninth, eleventh transistors are respectively connected to two negative level, providing an output negative level;

[0041] 电路电荷泄放模块04,包括第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15 ;第十二、第十三、第十四、第十五晶体管构成对采样信号的保持和泄放回路,第十三晶体管受输入信号控制,确保输入信号高电平时,输出级为低电平;第十二、第十四、第十五晶体管受下一级单元扫描驱动器的输出信号控制,当下一级扫描驱动器的输出信号为高时,第十二、第十四、第十五晶体管导通,泄放电荷。 [0041] bleed charge circuit block 04, includes a twelfth transistor T12, T13 thirteenth transistor, a fourteenth transistor T14, a fifteenth transistor T15; the twelfth, thirteenth, fourteenth, fifteenth when transistor circuit for holding the sampled signal and bleed, thirteenth transistor controlled by the input signal, the input signal to ensure a high level, the output level is low; the twelfth, fourteenth, fifteenth transistor receiving the next an output signal of the control stage of a scan driver unit, a current output signal of the scan driver is high, twelfth, fourteenth, fifteenth transistor is turned on, a charge bleed.

[0042] 对于第I、级单元扫描驱动器:第一晶体管的源极接第二晶体管的漏极和第三晶体管的栅极,第一晶体管的栅极接时钟控制线,第一晶体管漏极接该级单元扫描驱动器的输入信号线;第二晶体管的栅极接时钟控制线,第二晶体管的源极接第四晶体管的栅极和第十二晶体管的漏极;第三晶体管的漏极接正电源线,第三晶体管的源极接第四晶体管漏极;第四晶体管的源极接第十三、第十四晶体管的漏极,以及第五、第七、第八、第十晶体管的栅极和电容Cp的一端C端; [0042] For Group I, a scan driver stage unit: the source of the first transistor to the gate of the second transistor and the drain of the third transistor, a gate connected to the clock control line of the first transistor, the first transistor drain connected the stage unit of the scan driver input signal line; clock source control line connected to a gate of the second transistor, the second transistor to the drain of the fourth transistor and the gate of the twelfth transistor; drain of the third transistor is coupled positive power source line, a source of the third transistor being connected the drain of the fourth transistor; the fourth source of the thirteenth transistor being connected, the drain of the fourteenth transistor, and a fifth, seventh, eighth, tenth transistor and the C-terminal end of the gate capacitor Cp;

[0043] 第五晶体管的漏极接时钟信号,第五晶体管的源极接第十五晶体管的漏极,以及电容Cp的另一端D端; A drain connected to the source and drain of the clock signal [0043] of the fifth transistor, the fifth transistor is connected to a fifteenth transistor, and the other end of the D terminal of the capacitor Cp;

[0044] 第六晶体管的漏极和栅极接正电源VDD,第六晶体管的源极接第七晶体管的漏极以及第九、第十一晶体管的栅极;第七晶体管的源极接第一负电源VSSL ;第八晶体管的漏极接正电源VDD ;第九晶体管的源极接第一负电源VSSL,第十晶体管的漏极接正电源VDD,第十一晶体管的源极接第二负电源VSS ; [0044] The drain and gate of the sixth transistor is connected to the positive supply the VDD, a source connected to the drain of the sixth transistor and a gate of the seventh transistor, ninth, eleventh transistor; a source of the seventh transistor being connected a negative power source VSSL; drain of the eighth transistor is connected to the positive supply the VDD; source of the ninth transistor is connected to a first negative power source VSSL, the drain of the tenth transistor is connected to the positive power supply VDD, a source connected to a second electrode of the eleventh transistor the VSS negative power supply;

[0045] 第十二晶体管的栅极接下一级单元扫描驱动器输出的RESET信号,第十二晶体管的源极接第二负电源VSS;第十三晶体管栅极接该级扫描驱动器的输入信号线,源极接第一负电源VSSL ;第十四晶体管的源极接第一负电源VSSL,第十五晶体管的源极接第二负电源VSS ; A gate [0045] The twelfth transistor means took a scan driver output RESET signal, a source connected to the second electrode of the twelfth transistor the VSS negative supply; a thirteenth transistor connected to the gate scan driver stage input signal line, a source connected to a first negative power source VSSL; source of the fourteenth transistor being connected VSSL first negative power supply, a source connected to the second electrode of the fifteenth transistor the VSS negative power supply;

[0046] 对第I级单元扫描驱动器:第八晶体管的源极接第九晶体管的漏极,以及下一级单元扫描驱动器的输入端;第十晶体管的源极接第十一晶体管的漏极以及像素阵列;第十四晶体管的栅极接下一级单元扫描驱动器输出的RESET信号; [0046] Level I of a scan driver unit: a source electrode connected to the drain of the eighth transistor, the ninth transistor, and an input terminal of the scan drive unit; a source electrode connected to the drain of the tenth transistor, the eleventh transistor and a pixel array; a gate of the fourteenth transistor means took a RESET signal output from the scan driver;

[0047] 对于第N级单元扫描驱动器:第八晶体管的源极接第九晶体管的漏极,以及上一级单元扫描驱动器的RESET端;第十晶体管的源极接第十一晶体管的漏极; [0047] For the N th scan drive unit: a source electrode connected to the drain of the eighth transistor, the ninth transistor, and a RESET terminal unit scans the driver; source of the tenth transistor being connected to the drain of the eleventh transistor ;

[0048] 对于第2〜NI级单元扫描驱动器;第八晶体管的源极接第九晶体管的漏极,以及上一级单元扫描驱动器的RESET端,下一级单元扫描驱动器的输入端;第十晶体管的源极接第十一晶体管的漏极以及像素阵列;第十四晶体管的栅极接下一级单元扫描驱动器输出的RESET信号;第十五晶体管的栅极接下一级单兀扫描驱动器输出的RESET信号。 [0048] For the first stage unit 2~NI scan driver; an eighth transistor source connected to the drain of the ninth transistor, and the drive unit scans a RESET terminal, the input terminal of one unit of the scan driver; X a source electrode connected to the drain of the transistor and a pixel array of the eleventh transistor; the gate of the fourteenth transistor means took a RESET signal output from the scan driver; a gate of the fifteenth transistor took a single scan driver Wu RESET signal output.

[0049] 上述单元扫描驱动器中的第一〜十五晶体管为N型晶体管。 [0049] The scan driver unit of the first through fifth transistor and N-type transistors.

[0050] 如图3所示,本实施例的有源有机电致发光显示器的扫描驱动器的驱动方法,包括以下步骤: [0050] As shown in FIG 3, the present embodiment has the active driving method of an organic electroluminescent light emitting display scan driver, comprising the steps of:

[0051] 时钟信号的前半周期为低电平,下半周期为高电平;VIN信号的脉冲宽度为一个周期的时钟信号;在时钟信号的第n周期,在时钟信号跳变高电平时,第n级单元扫描驱动器接收输入信号,开始进行输入采样阶段;在时钟信号进入第n+1周期时,第n级单元扫描驱动器结束输入采样阶段,进行信号耦合输出;同时,第n+1级单元扫描驱动器以第n级单兀扫描驱动器的第一输出端COUT (n)的输出信号为输入信号,在时钟信号进入第n+1周期的下半周期时开始进行输入采样阶段;在时钟信号的第n+2周期,第n+1级单元扫描驱动器结束输入采样阶段,进行信号耦合输出阶段;同时,第n级单元扫描驱动器以第n+1级单元扫描驱动器的第一输出端COUT(n+1)的输出信号作为复位端RESET的启动信号,第n级单兀扫描驱动器的第一输出端COUT (n)和第二输出端OUT (n)的输出信号均被置位到负 First half cycle [0051] The clock signal is low, half period is high; VIN signal is a pulse width of one cycle of the clock signal; n-th cycle of the clock signal, the clock signal goes high jump, n-th stage unit scan driver receives an input signal, it starts an input sample phase; when the clock signal into the first n + 1 cycle, the n-th stage unit scan driver ended input sampling stage, the signal coupling-out; the same time, + first-stage n 1 unit scan driver to output the signal of the n-stage single Wu scan driver to a first output terminal COUT (n) is the input signal to start input sampling stage when the clock signal enters the n + half period one cycle; the clock signal the n + 2 th cycle, the n + 1 level means the scan driver ended input sampling stage, the signal coupling-out stage; simultaneously, a first output terminal COUT n-th unit scan driver in the + first-stage n 1 unit of the scan driver ( n + 1) as the output signal of the enable signal reset terminal rESET, a single n-th stage of the first scan driver Wu output terminal COUT (n) and a second output terminal OUT (n) are an output signal is set to a negative 位,开始进行信号泄放阶段;其中n=l…N-1。 Bits, start bleed phase signal; wherein n = l ... N-1.

[0052] 如图4所示,输入采样阶段具体为:时钟控制线控制第一和第二晶体管的开关状态,时钟信号由高电平变低电平,输入信号由低电平变高电平,此时第一、第二晶体管关断,A、B两点保持低电平维持第三、第四晶体管关断状态,第十三晶体管导通,C点电位被拉低到第一负电源VSSL,使得第五、第七、第八和第十晶体管关闭,E经过第六晶体管被充电到正电源VDD,使得第九和第十一晶体管导通,输出信号为低电平;输入信号继续保持高电平,时钟信号由低电平变高电平,第一、第二晶体管同时导通,A、B两点采集输入信号,使得第三和第四晶体管同时导通,由于第十三晶体管被输入信号打开,C点电位维持第一负电源VSSL的电平,输出信号保持低电平状态。 [0052] As shown in FIG 4, the input sampling stage is specifically: a clock control line and a second switching state of the first transistor, the clock signal goes low from high, the input signal goes high from low In this case the first, the second transistor is turned off, A, B two o'clock held low to maintain the third and the fourth transistor off-state, a thirteenth transistor, C point potential is pulled down to a first negative supply VSSL, so that the fifth, seventh, eighth and tenth transistors are turned off, E through the sixth transistor is charged to the VDD positive power source, so that the ninth and the eleventh transistor is turned on, the output signal is low; the input signal continues to remains high, the clock signal goes high from low, first and second transistors are simultaneously turned on, A, B two o'clock capture input signal, such that the third and fourth transistors are simultaneously turned on, since the thirteenth an input signal transistor is opened, C point potential maintained level, the output signal of the first negative power source VSSL remains low.

[0053] 如图4所示,信号耦合输出阶段:当输入信号由高电平变低电平,时钟信号也由高电平变低电平,因此第一、第二、第十三晶体管均关断,A、B两点维持高电平,第三和第四晶体管保持导通状态,正电源VDD对C点充电到正电源电平,同时将第五晶体管打开,电容Cp保持着C点电位,此时第八晶体管和第十晶体管导通,第七晶体管导通,E点电位拉低到第一负电源VSSL电平,使得第九和第十一晶体管关闭,正电源VDD通过第八和第十晶体管给输出端充电,输出高电平;当输入信号保持低电平,时钟信号也由低变高,第五晶体管继续保持导通,第九和第十一晶体管保持关闭,时钟信号给电容Cp的D端充电,C点随之跳变为更高的电平,使得第八晶体管和第十晶体管有更好的导通状态,使得输出端COUT和OUT的电平等于正电源电平。 [0053] 4, the output signal is coupled stages: a high level when the input signal goes low, the clock signal becomes low level from high level, the first, second, thirteenth transistor are oFF, A, B two o'clock maintains the high level, the third and fourth transistor remains conductive state, the positive power source VDD is charged to the positive power supply point C level while the fifth transistor is turned on, the capacitor Cp maintains the point C potential, when the eighth transistor and the tenth transistor, the seventh transistor is turned on, E point potential is pulled down to the negative power source VSSL a first level, such that the ninth and the eleventh transistor is turned off, the positive power source VDD through the eighth and tenth transistor to charge an output terminal, outputs a high level; when the input signal is held low, the clock signal is also from low to high, to maintain the fifth transistor is turned on, the ninth and eleventh transistors remain off, the clock signal D terminal of the capacitor Cp is charged, C point will jump into a higher level, so that the eighth transistor and the tenth transistor have better conduction state, so that the electrical output terminal OUT and COUT is equal to the positive power source level.

[0054] 如图4所示,信号泄放阶段:输入信号继续保持低电平,下一级单元扫描驱动器的输出RESET信号反馈回这一级单元扫描驱动器的信号泄放模块,打开第十二、第十四、第十五晶体管,将B点,C点,D点上的电荷泄放至第一负电压VSSL,和第二负电压VSS,同时E点电位升高,将第九和第i^一晶体管打开,输出端COUT电位被拉低到第一负电压VSSLjPOUT被拉低到第二负电压VSS。 [0054] 4, the relief phase signal: the input signal held low, the RESET signal at an output unit of the scan driver that feeds back a signal of the scan driver unit deflation module, a twelfth open , fourteenth, fifteenth transistor, the charge on the B point, C point, D point to the first negative voltage VSSL bleed, and the second negative voltage VSS, and the potential of the point E rises, the ninth and i ^ a transistor is turned on, the potential of the output terminal COUT is pulled down to a first negative voltage VSSLjPOUT is pulled down to a second negative voltage VSS.

[0055] 上述实施例为本发明较佳的实施方式,但本发明的实施方式并不受所述实施例的限制,其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化,均应为等效的置换方式,都包含在本发明的保护范围之内。 [0055] The preferred embodiment of the present invention embodiment, but the embodiment of the present invention is not limited by the embodiments, changes made to any other without departing from the spirit and principle of the present invention, a modified, Alternatively, combinations, simplification of the replacement pattern of equivalent effect, are included within the scope of the present invention.

Claims (4)

1.有源有机电致发光显示器的扫描驱动器,其特征在于,包括N级单元扫描驱动器;每个单兀扫描驱动器包括一个输入端IN,—个时钟信号输入端CLK, 一个复位端RESET,第一输出端COUT和第二输出端OUT ;第一级单兀扫描驱动器的输入端IN接收开始输入信号;第I^NI级单兀扫描驱动器的第一输出端COUT的输出信号作为下一级单兀扫描驱动器的输入端IN的输入信号;第2、级单元扫描驱动器的第一输出端COUT的输出信号作为上一级单元扫描驱动器复位端RESET的启动信号; 每个单元扫描驱动器包括: 输入采样模块,包括第一、第二、第三和第四晶体管;其中第一、第二晶体管在时钟高电位时导通,控制第三、第四晶体管导通情况,从而对输入信号采样; 信号耦合模块,包括第五晶体管和一个电容Cp,采样信号控制第五晶体管的导通状态,电容Cp根据时钟信号耦合采样信号 1. The active organic electroluminescent scan driver light emitting display, characterized in that it comprises N-level cell scan driver; each single-Wu scan driver includes an input terminal IN, - a clock signal input of the CLK, a reset terminal the RESET, a first a second output terminal COUT and the output terminal OUT; Wu single stage input terminal of the first scan driver receives a start input signal iN; I ^ a first output signal a first output terminal COUT of the single-stage NI Wu scan driver as the one single input Wu scan driver's iN input signal; a second output signal a first output terminal COUT of the stage unit scan driver as the one unit scan driver reset terminal rESET of the activation signal; each unit scan driver comprising: an input sampling module, comprising a first, second, third and fourth transistors; wherein the first, the second transistor is turned on when the clock a high potential, controlling the third, the fourth transistor is turned on, the input signal samples thereby; signal coupling module, including a fifth transistor and a capacitor Cp, the sampling signal controls the conduction state of the fifth transistor, the capacitance Cp sampling signal coupled to the clock signal ,控制输出信号; 电路的输出级,包括第六、第七、第八、第九、第十、第十一晶体管;其中第六,第七晶体管构成非门,为采样信号的反相;第八、第九、第十、第十一晶体管构成两个输出端,第八、第十晶体管接正电源,提供高电平输出;第九、第十一晶体管分别接两个负电平,提供负电平的输出; 电路电荷泄放模块,包括第十二、第十三、第十四、第十五晶体管;第十二、第十三、第十四、第十五晶体管构成对采样信号的保持和泄放回路,第十三晶体管受输入信号控制,确保输入信号高电平时,输出级为低电平;第十二、第十四、第十五晶体管受下一级单元扫描驱动器的输出信号控制,当下一级扫描驱动器的输出信号为高时,第十二、第十四、第十五晶体管导通,泄放电荷。 The control output signal; an output stage circuit comprises a sixth, seventh, eighth, ninth, tenth, eleventh transistor; wherein the sixth, seventh transistors constituting the NAND gate, the inverted sampling signal; first eight, ninth, tenth, eleventh transistor two output terminals, eighth, tenth transistor connected to the positive power supply, a high-level output; the ninth, eleventh transistors respectively connected to two negative level, providing a negative electrical level output; charge dissipation circuit module comprising a twelfth, thirteenth, fourteenth, fifteenth transistor; the twelfth, thirteenth, fourteenth, fifteenth transistor holding the sampled signal when the bleeder circuit, a thirteenth transistor controlled by the input signal, the input signal to ensure a high level, the output level is low; the twelfth, fourteenth, a fifteenth transistor means receiving the output signal of the scanning driver control, an output signal of the lower scan driver is high, twelfth, fourteenth, fifteenth transistor is turned on, a charge bleed.
2.根据权利要求I所述的有源有机电致发光显示器的扫描驱动器,其特征在于, 对于第rN级单元扫描驱动器:第一晶体管的源极接第二晶体管的漏极和第三晶体管的栅极,第一晶体管的栅极接时钟控制线,第一晶体管漏极接该级单元扫描驱动器的输入信号线;第二晶体管的栅极接时钟控制线,第二晶体管的源极接第四晶体管的栅极和第十二晶体管的漏极;第三晶体管的漏极接正电源线,第三晶体管的源极接第四晶体管漏极;第四晶体管的源极接第十三、第十四晶体管的漏极,以及第五、第七、第八、第十晶体管的栅极和电容Cp的一端; 第五晶体管的漏极接时钟信号,第五晶体管的源极接第十五晶体管的漏极,以及电容Cp的另一端; 第六晶体管的漏极和栅极接正电源VDD,第六晶体管的源极接第七晶体管的漏极以及第九、第十一晶体管的栅极;第七晶体 The active I of the organic electroluminescent light emitting display, a scan driver as claimed in claim, characterized in that, for the first scan driver unit rN stage: a first transistor connected to a source drain of the second transistor and the third transistor the gate, the gate to the clock control line of the first transistor, the first transistor drain connected to the driver stage unit scans an input signal line; clock source control line connected to a gate of the second transistor, the second transistor is connected to a fourth the drain of the transistor and the gate of the twelfth transistor; drain of the third transistor is connected to the positive power source line, a source of the third transistor being connected the drain of the fourth transistor; source of the fourth transistor being connected XIII, X four drain of the transistor, and the fifth, seventh, eighth, tenth transistor and the gate capacitance Cp end; clock signal source connected to the drain of the fifth transistor, the fifth transistor being connected fifteenth transistor drain electrode, and the other end of the capacitor Cp; source drain and gate connected to the positive power supply VDD, a sixth transistor, a sixth transistor and a gate connected to the drain of the seventh transistor of the ninth, eleventh transistor; the first seven crystal 的源极接第一负电源VSSL ;第八晶体管的漏极接正电源VDD ;第九晶体管的源极接第一负电源VSSL,第十晶体管的漏极接正电源VDD,第十一晶体管的源极接第二负电源VSS ; 第十二晶体管的栅极接下一级单元扫描驱动器输出的RESET信号,第十二晶体管的源极接第二负电源VSS;第十三晶体管栅极接该级扫描驱动器的输入信号线,源极接第一负电源VSSL ;第十四晶体管的源极接第一负电源VSSL,第十五晶体管的源极接第二负电源VSS ; 对第I级单元扫描驱动器:第八晶体管的源极接第九晶体管的漏极,以及下一级单元扫描驱动器的输入端;第十晶体管的源极接第十一晶体管的漏极以及像素阵列;第十四晶体管的栅极接下一级单元扫描驱动器输出的RESET信号; 对于第N级单元扫描驱动器:第八晶体管的源极接第九晶体管的漏极,以及上一级单元扫描驱动器的RESET端;第 A first source electrode connected to the negative power source VSSL; positive power supply VDD connected to the drain of the eighth transistor; the ninth transistor is connected to a first negative power source VSSL, a drain connected to the positive power supply VDD of the tenth transistor, an eleventh transistor a second source electrode connected to the VSS negative supply; twelfth transistor gate took a RESET signal output from the scan driver unit, source of the twelfth transistor being connected the second negative power supply the VSS; a thirteenth transistor connected to the gate input signal drive level scan line, a source connected to a first negative power source VSSL; source of the fourteenth transistor being connected VSSL first negative power supply, a source connected to the second electrode of the fifteenth transistor the VSS negative supply; means for level I the scan driver: a source electrode connected to the drain of the eighth transistor, and an input terminal of the ninth transistor is a unit of the scan driver; a source electrode connected to the drain of the tenth transistor and the eleventh transistor pixel array; fourteenth transistor gate means took a RESET signal output from the scan driver; N-th-stage unit for scanning driver: a source electrode connected to the drain of the eighth transistor, the ninth transistor, and a unit on the RESET terminal of the scan driver; of 晶体管的源极接第十一晶体管的漏极; 对于第2〜NI级单元扫描驱动器;第八晶体管的源极接第九晶体管的漏极,以及上一级单元扫描驱动器的RESET端,下一级单元扫描驱动器的输入端;第十晶体管的源极接第十一晶体管的漏极以及像素阵列;第十四晶体管的栅极接下一级单元扫描驱动器输出的RESET信号;第十五晶体管的栅极接下一级单兀扫描驱动器输出的RESET信号。 Source of the transistor to the drain of the eleventh transistor; 2~NI stage unit for the first scan driver; an eighth transistor source connected to the drain of the ninth transistor, and a unit on the RESET terminal of the scan driver, the next stage unit scan driver input terminal; a source electrode connected to the drain of the tenth transistor and the eleventh transistor pixel array; the gate of the fourteenth transistor means took a RESET signal output from the scan driver; a fifteenth transistor a single gate took RESET signal output from the scan driver Wu.
3.根据权利要求I所述的有源有机电致发光显示器的扫描驱动器,其特征在于,所述单元扫描驱动器中的第一〜十五晶体管为N型晶体管。 3. The active I as claimed in claim organic electroluminescent light emitting display scan driver, wherein said drive unit scans the first through fifth transistor and N-type transistors.
4.如权利要求I所述的有源有机电致发光显示器的扫描驱动器的驱动方法,其特征在于,包括以下步骤: 时钟信号的前半周期为低电平,下半周期为高电平;VIN信号的脉冲宽度为一个周期的时钟信号; 在时钟信号的第n周期,在时钟信号跳变高电平时,第n级单元扫描驱动器接收输入信号,开始进行输入采样阶段; 在时钟信号进入第n+1周期时,第n级单元扫描驱动器结束输入采样阶段,进行信号耦合输出;同时,第n+1级单兀扫描驱动器以第n级单兀扫描驱动器的第一输出端COUT的输出信号为输入信号,在时钟信号进入第n+1周期的下半周期时开始进行输入采样阶段; 在时钟信号的第n+2周期,第n+1级单元扫描驱动器结束输入采样阶段,进行信号耦合输出阶段;同时,第n级单元扫描驱动器以第n+1级单元扫描驱动器的第一输出端COUT的输出信号作为复位端RESET的启 4. I claim the active driving method for an organic electroluminescence light emitting scan driver display, characterized by comprising the steps of: a first half cycle of the clock signal is low, half period is high; the VIN pulse width signal is a clock signal period; at n-th cycle of the clock signal, when the clock signal transitions high, the n-th stage unit scan driver receives an input signal, it starts an input sample phase; into the n-th clock signal +1 cycle, the n-th stage unit scan driver ended input sampling stage, the signal coupling-out; the same time, the n + 1st single Wu scan driver the n-th stage output signal a first output terminal COUT single Wu scan driver is start input sampling stage input signal into the next half period of the n + 1 cycle of the clock signal; the n + 2 th cycle of the clock signal, + first-stage n 1 means the scan driver ended input sampling stage, the signal outcoupling stage; the same time, the n-th scan driver stage unit to the output signal of the first output terminal of stage n + 1 of the driver unit scans as COUT start of the reset terminal rESET 动信号,第n级单兀扫描驱动器的第一输出端COUT和第二输出端OUT的输出信号均被置位到负电位,开始进行信号泄放阶段;其中n=l-N_l。 Activation signal, the n-th scan driver stage single Wu first output terminal COUT and the output signal a second output terminal OUT are set to the negative potential, start bleed phase signal; wherein n = l-N_l.
CN201210505333.0A 2012-11-30 2012-11-30 Scanning driver for active organic electroluminescent display and driving method thereof CN102968956B (en)

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