CN102967791A - Inspection method for judging contact of digital circuit board test pen and test pen - Google Patents
Inspection method for judging contact of digital circuit board test pen and test pen Download PDFInfo
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- CN102967791A CN102967791A CN2012104575901A CN201210457590A CN102967791A CN 102967791 A CN102967791 A CN 102967791A CN 2012104575901 A CN2012104575901 A CN 2012104575901A CN 201210457590 A CN201210457590 A CN 201210457590A CN 102967791 A CN102967791 A CN 102967791A
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Abstract
The invention discloses an inspection method for judging contact of a digital circuit board test pen and a digital circuit board test pen with a contact inspection function, which are applied to the field of testing of the digital circuit boards. According to the inspection method disclosed by the invention, a method for comparing preset voltage with voltage is utilized to judge and display whether the test pen contacts well with a test point on the circuit board or not on the condition of not affecting a digital signal collected or received by the test pen, thereby avoiding misjudgment of the test result due to poor contact of the test pen.
Description
Technical field
The present invention relates to the digital circuit board field tests, be specifically related to a kind of inspection method of the contact for judging digital circuit board test probe pen and realize the test probe pen that described probe pen contact checks.
Background technology
In today of informationized society high speed development; digital circuit has been widely used in the every field such as computing machine, network, digital entertainment and Industry Control; in the process of development, production, test and the use of these electronic equipments; all exist the on-line testing demand of a series of digital circuit board; usually can use the equipment such as logic analyser; when these equipment of use, the probe pen of equipment need to be accessed in the digital circuit board well.
Patented claim " point calibration method under a kind of test probe pen pin " (applying date 2012.04.24, application number is 201210121618.4) a kind of camera that utilizes is disclosed to the method for point calibration under the pin of test probe pen and accurate location, behind point calibration under the pin, as long as watch tracking cross to aim at the measured target point at computer screen, and needn't the drop test probe pen make probe contact circuit plate, can judge that the test probe pen reaches the measured target point, thereby can make the test probe pen accurately fall the measured target point.But present most of circuit board surface has all covered one deck insullac, when even probe touches on the circuit board during detection, because insullac is sometimes thicker, probe is the insulation-piercing enamelled coating not necessarily, at this moment probe seems with circuit and contacts, but reality is good contact not, and the signal that collect by probe this moment can not truly reflect actual signal, thereby cause the erroneous judgement to circuit signal.
Summary of the invention
The object of the invention is to, a kind of inspection method and test probe pen of judging the contact of digital circuit board test probe pen is provided, to realize judging that probe pen is whether in the digital circuit of good access circuit-under-test plate, and in the situation that does not affect signal on the circuit board the accurate signal of collecting circuit board test point, thereby circuit board is carried out fault diagnosis.
For reaching above-mentioned purpose, the inspection method of the contact of judgement digital circuit board test probe pen provided by the invention comprises:
The logic state that presets probe pen under the contact condition not is the third logic state outside the digital circuit logic state;
Judge the circuit logic state at probe pen and digital circuit board contact point place;
Judge according to the logic state of probe pen contact whether good contact is in digital circuit board in the contact.
Digital circuit board test probe pen with contact audit function provided by the invention is characterized in that comprising that contact point voltage initializing circuit, logical one lower voltage limit arrange circuit, the logical zero upper voltage limit arranges circuit, contact point voltage comparator circuit, decision circuitry and indicating circuit:
Contact point voltage initializing circuit: be used for the voltage of probe pen contact is initialized to preset voltage, this preset voltage is the intermediate value voltage of logical one lower voltage limit value and logical zero upper voltage limit value, when probe pen does not contact with circuit board, the voltage of probe pen contact is this preset voltage just, in case probe pen contacts with circuit board, then the voltage of probe pen contact will become the voltage at institute contact circuit plate place;
The logical one lower voltage limit arranges circuit: for generation of the logical one lower voltage limit, as the discrimination standard of logical one voltage on the circuit board;
The logical zero upper voltage limit arranges circuit: for generation of the logical zero upper voltage limit, as the discrimination standard of logical zero voltage on the circuit board;
Contact point voltage comparator circuit: the voltage of contact point is compared and export respectively comparative result with logical one lower voltage limit, logical zero upper voltage limit respectively;
Decision circuitry: two comparative results of contact point voltage comparator circuit output are carried out logical combination, judge whether contact point accesses in the digital circuit;
Indicating circuit: be used to indicate judged result.
Utilize the present invention, during test point on using probe pen (such as circuit fault diagnosis system probe pen, logic analyser probe pen) contact digital circuit board, can guarantee that the contact of probe pen can not affect the original signal amount of test point, simultaneously can show clearly whether probe pen contacts well with the measured number circuit board, thereby avoid reading wrong data because the probe pen loose contact causes.
Description of drawings
Fig. 1 is the schematic diagram that the test probe pen detects at digital circuit board;
Fig. 2 is the probe pen contact check circuit schematic diagram that the specific embodiment of the invention realizes.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in further detail.
Be illustrated in figure 1 as the schematic diagram that the test probe pen detects at digital circuit board.In test process, with digital signal acquiring equipment 1(such as logic analyser, circuit fault diagnosis system etc.) probe pen 2 access circuit-under-test plates 3 in, under the state of circuit working, the signal of test point is gathered.
As shown in Figure 2, take the digital circuit board of Transistor-Transistor Logic level as example, circuit adopts direct supply 4(such as button cell) power supply.Resistance 5 and resistance 6 consist of the logical zero upper voltage limit circuit are set, and dividing potential drop produces logical zero upper voltage limit standard value (being 0.8V).Resistance 7 and resistance 8 consist of the logical one lower voltage limit circuit are set, and dividing potential drop produces logical one lower voltage limit standard value (being 2.4V).Resistance 9 and resistance 10 consist of contact point voltage initializing circuit, preset voltage when dividing potential drop produces probe pen unsettled (namely not contact circuit plate), the logic state that presets probe pen under the contact condition not is the third logic state outside the digital circuit logic state, this preset voltage is neither in the logical one voltage range, also not in the logical zero voltage range, be the intermediate value voltage (being 1.6V) of logical zero upper voltage limit standard value and logical one lower voltage limit standard value.The first comparer 11 and the second comparer 12 consist of the contact point voltage comparator circuit, are used for judging the circuit logic state at probe pen and digital circuit board contact point place.The logical one lower voltage limit is accessed the end of oppisite phase of the first comparer 11, and the logical zero upper voltage limit accesses the in-phase end of the second comparer 12.At this moment, the end of oppisite phase voltage of the first comparer 11 is 2.4V, and the in-phase end voltage of the second comparer 12 is 0.8V.The output terminal of the first comparer 11 and the second comparer 12 is connected respectively to or the input end of door 13.Or door 13 consists of decision circuitry, be used for judging according to the circuit logic state of probe pen contact whether good contact is to digital circuit board in the contact, or the output terminal of door 13 is connected with LED lamp 15 through current-limiting resistance 14, the lighting and extinguish of control LED lamp 15, thus the indication probe pen whether with the circuit board test point good contact.
When probe pen 2 was unsettled, the in-phase end voltage of the first comparer 11 was 1.6V, less than end of oppisite phase voltage, so the first comparer 11 is output as 0; At this moment, the end of oppisite phase voltage of the second comparer 12 is 1.6V, greater than in-phase end voltage, so the second comparer 12 is output as 0; Through or door be output as 0, LED lamp 15 after 13 and be in and extinguish state.
After probe pen 3 touches test point on the circuit board, and this moment, circuit board was in running order, and the voltage on this moment probe pen contact is the voltage of test point, only had logical one state and logical zero state for the semaphore of circuit on the digital circuit board.If test point is the logical one state, this moment, test point voltage was greater than 2V, then the in-phase end voltage of the first comparer 11 is greater than end of oppisite phase voltage, be output as " 1 " (near 5V), the in-phase end voltage of the second comparer 12 is output as " 0 " less than end of oppisite phase voltage, so behind process or the door 13, be output as " 1 ", LED lamp 15 is lighted.
In like manner, when probe pen touches test point, test point is the logical zero state, and when this moment, test point voltage was less than 1V, the in-phase end voltage of the first comparer 11 was output as " 0 " less than end of oppisite phase voltage; The in-phase end voltage of the second comparer 12 is output as " 1 " greater than end of oppisite phase voltage; Being output as 1, LED lamp 15 behind process or the door 13 also lights.
Can find out by the state of LED lamp whether probe pen is linked in the circuit, if namely LED lamp 15 light the expression probe pen be linked in the circuit, if LED lamp 15 extinguish the expression probe pen do not contact with circuit.
As shown in Figure 2, when the signal of circuit board test point is connected to contact check circuit, also be connected to simultaneously digital signal acquiring equipment 1, therefore can be implemented in the contact situation of ray examination probe pen.
Although described the present invention by embodiment, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, wishes that appended claim comprises these distortion and variation.
Claims (8)
1. inspection method of judging the contact of digital circuit board test probe pen is characterized in that comprising:
The logic state that presets probe pen under the contact condition not is the third logic state outside the digital circuit logic state;
Judge the circuit logic state at probe pen and digital circuit board contact point place;
Judge according to the circuit logic state of probe pen contact whether good contact is in digital circuit board in the contact.
2. the inspection method of the contact of judgement digital circuit board test probe pen as claimed in claim 1 is characterized in that judging that the step of the circuit logic state at probe pen and digital circuit board contact point place is:
Logical one lower voltage limit in probe pen contact voltage and the measured number circuit board is compared, judge whether the contact logic state is 1;
Logical zero upper voltage limit in probe pen contact voltage and the measured number circuit board is compared, judge whether the contact logic state is 0.
3. the inspection method of the contact of judgement digital circuit board test probe pen as claimed in claim 1 is characterized in that the preset voltage of probe pen under the contact condition not is neither in the logical one voltage range, also not in the logical zero voltage range.
4. the inspection method of the contact of judgement digital circuit board test probe pen as claimed in claim 1, it is characterized in that judging according to the circuit logic state of probe pen contact whether good contact to the method in the digital circuit board is in the contact: according to the logic state judged result of probe pen contact, if the logic state of contact is " 1 " or " 0 ", show that then the probe pen contact well accesses in the measured number circuit board; If the voltage of contact, shows then that the probe pen contact contacts with the measured number circuit board neither logical one voltage neither logical zero voltage.
5. one kind has the digital circuit board test probe pen that contacts audit function, it is characterized in that comprising that contact point voltage initializing circuit, logical one lower voltage limit arrange circuit, the logical zero upper voltage limit arranges circuit, contact point voltage comparator circuit, decision circuitry and indicating circuit:
Contact point voltage initializing circuit: be used for the voltage of probe pen contact is initialized to preset voltage, this preset voltage is the intermediate value voltage of logical one lower voltage limit value and logical zero upper voltage limit value, when probe pen does not contact with circuit board, the voltage of probe pen contact is this preset voltage just, in case probe pen contacts with circuit board, then the voltage of probe pen contact will become the voltage at institute contact circuit plate place;
The logical one lower voltage limit arranges circuit: for generation of the logical one lower voltage limit, as the discrimination standard of logical one voltage on the circuit board;
The logical zero upper voltage limit arranges circuit: for generation of the logical zero upper voltage limit, as the discrimination standard of logical zero voltage on the circuit board;
Contact point voltage comparator circuit: the voltage of contact point is compared and export respectively comparative result with logical one lower voltage limit, logical zero upper voltage limit respectively;
Decision circuitry: two comparative results of contact point voltage comparator circuit output are carried out logical combination, judge whether contact point accesses in the digital circuit;
Indicating circuit: be used to indicate judged result.
6. test probe pen as claimed in claim 5 is characterized in that described contact point voltage comparator circuit comprises the first comparer and the second comparer:
The first comparer is used for the lower voltage limit of contact point voltage and logical one is compared;
The second comparer is used for the upper voltage limit of contact point voltage and logical zero is compared.
7. test probe pen as claimed in claim 5, it is characterized in that described decision circuitry comprises one or door: be used for two comparative results of contact point voltage comparator circuit output are got or, described get or after the result be used for judging whether contact point accesses in the digital circuit.
8. test probe pen as claimed in claim 5 is characterized in that the result that described circuit adopts the indication of LED lamp to check.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210457590.1A CN102967791B (en) | 2012-11-15 | 2012-11-15 | Inspection method for judging contact of digital circuit board test pen and test pen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210457590.1A CN102967791B (en) | 2012-11-15 | 2012-11-15 | Inspection method for judging contact of digital circuit board test pen and test pen |
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| Publication Number | Publication Date |
|---|---|
| CN102967791A true CN102967791A (en) | 2013-03-13 |
| CN102967791B CN102967791B (en) | 2015-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210457590.1A Expired - Fee Related CN102967791B (en) | 2012-11-15 | 2012-11-15 | Inspection method for judging contact of digital circuit board test pen and test pen |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104316864A (en) * | 2014-10-30 | 2015-01-28 | 南通富士通微电子股份有限公司 | Semiconductor testing fixture |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2147548Y (en) * | 1992-09-15 | 1993-11-24 | 四川大学 | Digital IC testing instrument and testing probe |
| CN2438273Y (en) * | 2000-06-12 | 2001-07-04 | 麦肯积体电路股份有限公司 | Circuit for testing mains voltage across points |
| JP2001194407A (en) * | 2000-01-17 | 2001-07-19 | Nec Ibaraki Ltd | Method and apparatus of electrical inspection for pattern wiring board |
| CN2874512Y (en) * | 2006-01-14 | 2007-02-28 | 比亚迪股份有限公司 | High voltage detection warning instrument for battery |
| CN102621482A (en) * | 2012-04-24 | 2012-08-01 | 河南正泰信创新基地有限公司 | Testing pen needle lower point correcting method |
-
2012
- 2012-11-15 CN CN201210457590.1A patent/CN102967791B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2147548Y (en) * | 1992-09-15 | 1993-11-24 | 四川大学 | Digital IC testing instrument and testing probe |
| JP2001194407A (en) * | 2000-01-17 | 2001-07-19 | Nec Ibaraki Ltd | Method and apparatus of electrical inspection for pattern wiring board |
| CN2438273Y (en) * | 2000-06-12 | 2001-07-04 | 麦肯积体电路股份有限公司 | Circuit for testing mains voltage across points |
| CN2874512Y (en) * | 2006-01-14 | 2007-02-28 | 比亚迪股份有限公司 | High voltage detection warning instrument for battery |
| CN102621482A (en) * | 2012-04-24 | 2012-08-01 | 河南正泰信创新基地有限公司 | Testing pen needle lower point correcting method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104316864A (en) * | 2014-10-30 | 2015-01-28 | 南通富士通微电子股份有限公司 | Semiconductor testing fixture |
| CN104316864B (en) * | 2014-10-30 | 2018-06-22 | 通富微电子股份有限公司 | Semiconductor test jig |
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| Publication number | Publication date |
|---|---|
| CN102967791B (en) | 2015-03-11 |
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Granted publication date: 20150311 Termination date: 20161115 |