CN102956485A - Semiconductor device structure and manufacturing method for same - Google Patents
Semiconductor device structure and manufacturing method for same Download PDFInfo
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- CN102956485A CN102956485A CN2011102421482A CN201110242148A CN102956485A CN 102956485 A CN102956485 A CN 102956485A CN 2011102421482 A CN2011102421482 A CN 2011102421482A CN 201110242148 A CN201110242148 A CN 201110242148A CN 102956485 A CN102956485 A CN 102956485A
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Abstract
The invention discloses a manufacturing method for a semiconductor device structure. The manufacturing method includes providing a semiconductor substrate; forming a covering layer with first openings on the semiconductor substrate; doping fluorine in a first region and a second region of the semiconductor substrate; removing a part of the covering layer in a channel center region to form a second opening; and forming a gate oxide layer on the semiconductor substrate and inside the second opening. The first region and the second region of the semiconductor substrate are exposed by the first openings, the first region is an overlap region of a gate electrode to be formed and a source electrode to be formed, the second region is an overlap region of the gate electrode to be formed and a drain electrode to be formed, and the channel center region is positioned between the first region and the second region. Thicknesses of parts of the gate oxide layer in the first region A and the second region B and the thickness of a part of the gate oxide layer on the channel center region C are controlled respectively, so that GIDL (gate-induced drain leakage) current can be prevented from being generated at overlap positions of the gate electrode and the source electrode/drain electrode, and the performance of the channel center region is guaranteed.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of semiconductor device structure and preparation method thereof.
Background technology
Owing between the grid of metal oxide semiconductor field effect tube (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) and the drain electrode very large overlapping region is arranged.As shown in Figure 1, the represented zone of regional A is the overlapping region between grid 101 and the drain electrode 103.Take NMOSFET as example, after grid 101 applies voltage, drain electrode 103 electromotive forces among the NMOSFET than grid 101 electromotive forces corrigendums to, then the effect owing to grid 101 voltages can produce the hole in regional A, the hole that forms will be passed depletion region and move in substrate 100, and the formation substrate current, this electric current is commonly called grid induction drain leakage (Gate-induced drain leakage, GIDL) electric current.Otherwise, after grid applies voltage, grid potential among the PMOSFET than drain potentials corrigendum to, then in overlapping between grid 101 and drain electrode 103 because the effect of grid 101 voltages can produce electronics, electronics will pass depletion region and move and formation GIDL electric current in substrate.
When semiconductor technology enters sub-micro after the epoch, owing to device size dwindles day by day, numerous integrity problems that the GIDL electric current causes become further serious.For example, the GIDL electric current may affect reliability and the power consumption of undersized MOSFET, the GIDL electric current also has material impact to the erasable operation of the memory devices such as electricallyerasable ROM (EEROM) (Electrically Erasable Programmable Read-Only Memory, EEPROM) simultaneously.
Produce the GIDL electric current for fear of the overlapping between grid and source/drain, can increase the thickness of the gate oxide layers of grid 101, the electric field that drains between 103 to reduce grid 101 and source electrode 102/, and then reduce the GIDL electric current.Yet, although it is favourable to avoiding producing the GIDL electric current to increase the thickness of gate oxide layers, but damaged the MOS performance of devices.
Therefore, need a kind of manufacture method of semiconductor device, can avoid the adverse effect brought by the GIDL electric current among the MOSFET, can keep again the original performance of MOS device.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The invention discloses a kind of manufacture method of semiconductor device structure, comprising: Semiconductor substrate a) is provided; B) form the cover layer with first opening in described Semiconductor substrate, described the first opening exposes first area and the second area of described Semiconductor substrate, described first area is the overlay region of grid to be formed and source electrode to be formed, described second area is the overlay region of described grid to be formed and drain electrode to be formed, and is the raceway groove central area between described first area and the described second area; C) doped with fluorine in the described first area of described Semiconductor substrate and described second area; D) cover layer on the described raceway groove of the removal central area is to form the second opening; And e) the described Semiconductor substrate in described the second opening forms gate oxide layers.
Preferably, described b) tectal formation method described in the step, comprise: on described Semiconductor substrate, be formed with successively the first oxide skin(coating) and the first nitride layer, be formed with the patterns of openings that exposes described Semiconductor substrate in described the first oxide skin(coating) and described the first nitride layer, wherein, the corresponding described first area of described patterns of openings, described raceway groove central area and described second area; Sidewall in described patterns of openings inboard forms side wall, and the material of described side wall is oxide; Form the second oxide skin(coating) with described the first nitride layer in described patterns of openings, wherein, the thickness of described the second oxide skin(coating) is less than the thickness of described the first oxide skin(coating); In described patterns of openings, form the nitride packed layer; And remove described the second oxide skin(coating) on described side wall and described nitride packed layer both sides and described the first nitride layer, have the described cover layer of described the first opening with formation.
Preferably, the formation method of described nitride packed layer comprises: form layer of nitride material at described the second oxide skin(coating), described layer of nitride material is filled up described patterns of openings at least; Remove the described layer of nitride material of described patterns of openings outside, to form described nitride packed layer.
Preferably, described d) removes tectal method on the described raceway groove central area in the step, comprising: described nitride packed layer is carried out etching; Remaining described the second oxide skin(coating) is carried out etching.
Preferably, adopt injection technology doped with fluorine in the described first area of described Semiconductor substrate and described second area.
Preferably, the employed gas of described injection technology is fluorine gas.
The dosage of the described fluorine that preferably, injects in the described injection technology is 1 * 10
13-5 * 10
15/ square centimeter.
Preferably, the Implantation Energy of described injection technology is 1-100KeV.
Preferably, the formation method of described gate oxide layers is thermal oxidation method.
Preferably, described method is at described e) also comprise after the step: the step that f) forms grid at described gate oxide layers.
Preferably, described f) step comprises: at described e) device that obtains of step forms gate material layers, and described gate material layers is filled up described the second opening at least; Remove the described gate material layers of described the second opening outside; Remove remaining cover layer, with in described first area, described raceway groove central area and described second area form described grid.
Preferably, described method is at described f) also comprise after the step: g) in the described Semiconductor substrate of described grid both sides, form the first shallow doped region and source electrode and the second shallow doped region and drain electrode.
Preferably, described g) step comprises: form the first clearance wall in the both sides of described grid; Carry out shallow doping injection technology, in the described Semiconductor substrate of described grid both sides, to form the described first shallow doped region and the described second shallow doped region; The outside at described first clearance wall of described grid both sides forms the second clearance wall; Execution source/drain electrode injection technology is to form described source electrode and described drain electrode in the described Semiconductor substrate of described grid both sides.
Preferably, the material of described the first clearance wall is oxide, and the material of described the second clearance wall is nitride.
Preferably, described gate oxide layers is at the thickness of described first area and the described second area thickness greater than described raceway groove central area.
The present invention also provides a kind of semiconductor device structure, comprising: Semiconductor substrate; The grid that forms in described Semiconductor substrate, and the source electrode and the drain electrode that are arranged in the described Semiconductor substrate of described grid both sides, described grid comprises gate oxide layers, and the thickness of the described gate oxide layers of the overlapping region of described grid and described source electrode and described drain electrode is greater than the thickness of the described gate oxide layers of described channel region.
Preferably, be doped with fluorine in the described Semiconductor substrate of the overlapping region of described grid and described source electrode and described drain electrode.
The present invention is by the formation technique of doping special properties of fluorine in control first area and the second area and combination gate oxide layers subsequently, control respectively the thickness of the gate oxide layers on first area A and the second area B and the thickness of the gate oxide layers on the C of raceway groove central area, and then can reduce even avoid the overlapping between grid and source/drain to produce in the GIDL electric current, guarantee the performance of raceway groove central area, and then reach the purpose that the MOS performance of devices is not exerted an influence.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the schematic diagram that forms the principle of GIDL electric current;
Fig. 2 is the process chart of making semiconductor device structure according to one embodiment of the present invention;
The cutaway view of the device that Fig. 3 A-3E obtains for each step in the technological process of making semiconductor device according to one embodiment of the present invention;
Fig. 4 A-4G for according to the present invention another execution mode make the cutaway view of the device that each step obtains in the technological process of semiconductor device;
Fig. 5 is according to the tectal process chart shown in an embodiment of the invention construction drawing 3B; With
Fig. 6 A-6F is the cutaway view of the device that obtains according to each step in the tectal technological process shown in one embodiment of the present invention construction drawing 3B.
Embodiment
Next, in connection with accompanying drawing the present invention is described more intactly, shown in the drawings of embodiments of the invention.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, it is thorough and complete to provide these embodiment to expose, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, size and the relative size in floor and district may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, perhaps can have between two parties element or layer.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, then do not have between two parties element or layer.
Fig. 2 is the process chart of making semiconductor device structure according to one embodiment of the present invention, the cutaway view of the device that Fig. 3 A-3E obtains for each step in the technological process of making semiconductor device according to one embodiment of the present invention.Describe method of the present invention in detail below in conjunction with Fig. 2 and Fig. 3 A-3E.
At first, execution in step 201 provides Semiconductor substrate.
As shown in Figure 3A, provide Semiconductor substrate 300.Semiconductor substrate 300 can be at least a in the following material of mentioning: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), the insulator on silicon, silicon-on-insulator (SOI), the insulator.Can be defined active area on the Semiconductor substrate 300.In addition, can be formed with the isolation structure (not shown) in Semiconductor substrate 300, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure etc.In order to simplify, only represent Semiconductor substrate 300 with a blank herein.
Then, execution in step 202, form the cover layer with first opening in Semiconductor substrate, first area and the second area of this first opening exposing semiconductor substrate, wherein, this first area is the overlay region of grid to be formed and source electrode to be formed, and this second area is the overlay region of grid to be formed and drain electrode to be formed, and is the raceway groove central area between this first area and this second area.
Shown in Fig. 3 B, be formed with first area A and the second area B of cover layer 310, the first openings 320 exposing semiconductor substrates 300 with first opening 320 in Semiconductor substrate 300.Cover layer 310 can be to be made by this area any materials commonly used, and cover layer 310 can be single layer structure, also can be sandwich construction, as long as it can form the first opening 320 of exposing semiconductor substrate 300 within it, and in subsequent technique, can independently the removal of the part between the first opening 320 be got final product.In addition, although the section shape of the first opening 320 shown in Fig. 3 B is up-narrow and down-wide trapezoidal, the present invention is not all right in this, and the section shape of the first opening 320 can also be trapezoidal, rectangle wide at the top and narrow at the bottom or other shape.First area A is the overlay region of grid (not shown) to be formed and source electrode (not shown) to be formed, second area B is the overlay region of grid to be formed and drain electrode (not shown) to be formed, and is raceway groove central area C between first area A and the second area B.Need to prove, because cover layer 310 will be as the mask of subsequent technique doped with fluorine in Semiconductor substrate 300, for doped with fluorine and do not affect other zone in first area A and second area B only, therefore, the size of first area A and second area B is corresponding with the minimum dimension of the first opening 320 on section.Below, in connection with Fig. 4 and Fig. 5 A-5H the formation method of cover layer 310 is described in detail.
Then, execution in step 203, doped with fluorine in the first area of Semiconductor substrate and second area.
According to one embodiment of the present invention, shown in Fig. 3 C, adopt injection technology doped with fluorine in the first area of Semiconductor substrate 300 A and second area B.Doped with fluorine in first area A and second area B can improve subsequently the growth rate of the gate oxide layers of growth thereon, and then so that the gate oxide layers of under equal conditions growing has different thickness in zones of different.Because the growth rate of gate oxide layers on first area A and second area B is greater than the growth rate at raceway groove central area C, therefore, can so that the thickness that is positioned at the gate oxide layers on first area A and the second area B greater than the thickness that is positioned at the gate oxide layers on the C of raceway groove central area.Like this by doping special properties of fluorine in control first area and the second area and in conjunction with the formation technique of subsequently gate oxide layers, can control respectively the thickness of the gate oxide layers on first area A and the second area B and the thickness of the gate oxide layers on the C of raceway groove central area, and then can reduce even avoid the overlapping between grid and source/drain to produce in the GIDL electric current, guarantee the performance of raceway groove central area, and then reach the purpose that the MOS performance of devices is not exerted an influence.
Preferably, the employed gas of injection technology is fluorine gas.Preferably.The dosage of the fluorine that injects in the injection technology is 1 * 10
13-5 * 10
15/ square centimeter.Preferably, the Implantation Energy of injection technology is 1-100KeV.
Then, execution in step 204 is removed the cover layer on the raceway groove central area, to form the second opening.
Shown in Fig. 3 D, the cover layer 310 that covers the raceway groove central area C of Semiconductor substrate 300 is removed, to form the second opening 330.The second opening 330 comprises first area A and second area B and the raceway groove central area C between the two on the Semiconductor substrate 300.Because this step is relevant with the structure and material of cover layer 310, therefore, the cover layer 310 that those skilled in the art can will be positioned at selectively according to the structure and material of its cover layer that adopts 310 on the C of raceway groove central area is removed.Should be noted that cover layer 310 removals that will be positioned at selectively on the C of raceway groove central area and do not mean that and to produce any impact to the cover layer 310 of the second opening 320 both sides.Hereinafter the structure and material in connection with cover layer 310 provided by the invention is described in detail for this removal step.
At last, execution in step 205, the Semiconductor substrate in the second opening forms gate oxide layers.
Shown in Fig. 3 E, the Semiconductor substrate 300 in the second opening 330 forms gate oxide layers 340.As example, the formation method of gate oxide layers 340 is thermal oxidation method.Because doped with fluorine in the first area of Semiconductor substrate 300 A and second area B, cause the growth rate of gate oxide layers on first area A and second area B greater than the growth rate at raceway groove central area C, therefore, be positioned at the thickness of the gate oxide layers on first area A and the second area B greater than the thickness that is positioned at the gate oxide layers on the C of raceway groove central area.
Fig. 4 A-4G for according to the present invention another execution mode make the cutaway view of the device that each step obtains in the technological process of semiconductor device.Another execution mode according to the present invention, manufacture method of the present invention also are included in the step that gate oxide layers forms grid after step 205.Another execution mode according to the present invention, manufacture method of the present invention also are included in the step that forms the first shallow doped region and source electrode and the second shallow doped region and drain electrode in the Semiconductor substrate of grid both sides.
As example, the step that forms grid at gate oxide layers may further comprise the steps.
Shown in Fig. 4 A, the device that obtains in step 205 forms gate material layers 350, and gate material layers 350 is filled up the second opening at least.As example, the material of described gate material layers 350 is polysilicon.
Shown in Fig. 4 B, remove the gate material layers 350 of the second opening 330 outsides.As example, the removal method of gate material layers 350 can be cmp (CMP).Particularly, adopt cmp to remove the gate material layers 350 of cover layer more than 310.
Shown in Fig. 4 C, remove remaining cover layer 310(namely, be positioned at the cover layer 310 of the second opening 330 both sides), to form grid at first area A, raceway groove central area C and second area B.This grid comprises gate oxide layers 340 and gate material layers 350.
As example, the step that forms the first shallow doped region and source electrode and the second shallow doped region and drain electrode in the Semiconductor substrate of grid both sides may further comprise the steps.
Shown in Fig. 4 D, form the first clearance wall 360 in the both sides of grid.The formation method of the first clearance wall 360 can adopt this area method commonly used, for example, forms the first spacer material layer at grid and Semiconductor substrate 300, then this first spacer material layer is carried out dry etching, to form the first clearance wall 360.
Shown in Fig. 4 E, carry out shallow doping injection technology, in the Semiconductor substrate 300 of grid both sides, to form the first shallow doped region 370A and the second shallow doped region 370B.For nmos device, the N-type of the dopant type that this shallow doping injection technology is injected; For the PMOS device, the P type of the dopant type that this shallow doping injection technology is injected.
Shown in Fig. 4 F, form the second clearance wall 380 in the outside of the first clearance wall 360 of grid both sides.Similarly, the formation method of the second clearance wall 380 can adopt this area method commonly used, for example, forms the second spacer material layer in grid, the first clearance wall 360 and Semiconductor substrate 300, then this second spacer material layer is carried out dry etching, to form the second clearance wall 380.
Shown in Fig. 4 G, execution source/drain electrode injection technology is to form source electrode 390A and drain electrode 390B in the Semiconductor substrate 300 of grid both sides.For nmos device, the N-type of the dopant type that this source/drain electrode injection technology is injected; For the PMOS device, the P type of the dopant type that this source/drain electrode injection technology is injected.
As example, the material of the first clearance wall 360 is oxide, and the material of the second clearance wall 380 is nitride.
Fig. 5 is the process chart according to the cover layer 310 shown in an embodiment of the invention construction drawing 3B, and Fig. 6 A-6F is the cutaway view of the device that obtains according to each step in the technological process of the cover layer 310 shown in one embodiment of the present invention construction drawing 3B.Describe the method for making cover layer 310 according to one embodiment of the present invention in detail below in conjunction with Fig. 5 and Fig. 6 A-6F.
At first, execution in step 202A is formed with the first oxide skin(coating) and the first nitride layer successively on Semiconductor substrate, be formed with the patterns of openings of exposing semiconductor substrate in the first oxide skin(coating) and the first nitride layer, wherein, the corresponding first area of patterns of openings, raceway groove central area and second area.
As shown in Figure 6A, on Semiconductor substrate 300, be formed with successively the first oxide skin(coating) 301 and the first nitride layer 302, and be formed with the patterns of openings 303 of exposing semiconductor substrate 300 in the first oxide skin(coating) 301 and the first nitride layer 302.The formation method of the first oxide skin(coating) 301 and the first nitride layer 302 can adopt this area method commonly used, for example, the figuratum photoresist layer of deposited oxide layer, nitride layer and tool on Semiconductor substrate successively, take photoresist layer as mask nitride layer and oxide skin(coating) are carried out etching, form patterns of openings 303.Patterns of openings 303 is used to form grid, and therefore, it is corresponding with first area A, raceway groove central area C and second area B.
Then, execution in step 202B, the sidewall in the patterns of openings inboard forms side wall, and the material of side wall is oxide.
Shown in Fig. 6 B, the sidewall in patterns of openings 303 inboards forms side wall 304.Similarly, the formation method of side wall 304 can adopt this area method commonly used, for example, reaches Semiconductor substrate 300 and form the spacer material layers in patterns of openings 303, then this spacer material layer is carried out dry etching, to form side wall 304.The material of side wall 304 is oxide.
Then, execution in step 202C forms the second oxide skin(coating) with the first nitride layer in patterns of openings, and wherein, the thickness of the second oxide skin(coating) is less than the thickness of the first oxide skin(coating).
Shown in Fig. 6 C, in patterns of openings 303, form the thickness of the second oxide skin(coating) 305, the second oxide skin(coating)s 305 less than the thickness 301 of the first oxide skin(coating) with the first nitride layer 302.
Then, execution in step 202D forms the nitride packed layer in patterns of openings.
As example, the formation method of nitride packed layer comprises: form layer of nitride material 306 at the second oxide skin(coating) 305, layer of nitride material 306 is filled up patterns of openings 303(at least shown in Fig. 6 D); And the layer of nitride material 306 of removing patterns of openings 303 outsides, to form nitride packed layer 307(shown in Fig. 6 E).Wherein, the method for the layer of nitride material 306 of removal patterns of openings 303 outsides for example is cmp.
At last, execution in step 202E removes the second oxide skin(coating) on side wall and nitride packed layer both sides and the first nitride layer, has the cover layer of the first opening with formation.
Shown in Fig. 6 F, the second oxide skin(coating) 305 on side wall 304 and nitride packed layer 307 both sides and the first nitride layer 302 is removed.Because the material of side wall 304 and the second oxide skin(coating) 305 is oxide, therefore, adopt dry etching it together can be removed.
In the above-described embodiment, cover layer on the C of raceway groove central area (comprising 305 and 307) from bottom to top comprises oxide skin(coating) and nitride layer successively, and the cover layer (comprising 301 and 302) that is positioned at the first opening both sides lower and on comprise successively oxide skin(coating) and nitride layer, therefore, at first adopt the etching gas of nitride that nitride packed layer 307 and the first nitride layer 302 are removed, then adopt the etching gas of oxide that remaining institute the second oxide skin(coating) 305 is removed.Because the thickness of the second oxide skin(coating) 305 is less than the thickness of the first oxide skin(coating) 301, therefore, remove after remaining the second oxide skin(coating) 305, still can form the second opening (shown in Fig. 3 B) on corresponding first area A, raceway groove central area C and the second area B.
The present invention is by the formation technique of doping special properties of fluorine in control first area and the second area and combination gate oxide layers subsequently, control respectively the thickness of the gate oxide layers on first area A and the second area B and the thickness of the gate oxide layers on the C of raceway groove central area, and then can reduce even avoid the overlapping between grid and source/drain to produce in the GIDL electric current, guarantee the performance of raceway groove central area, and then reach the purpose that the MOS performance of devices is not exerted an influence.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (17)
1. the manufacture method of a semiconductor device structure is characterized in that, comprising:
A) provide Semiconductor substrate;
B) form the cover layer with first opening in described Semiconductor substrate, described the first opening exposes first area and the second area of described Semiconductor substrate, described first area is the overlay region of grid to be formed and source electrode to be formed, described second area is the overlay region of described grid to be formed and drain electrode to be formed, and is the raceway groove central area between described first area and the described second area;
C) doped with fluorine in the described first area of described Semiconductor substrate and described second area;
D) cover layer on the described raceway groove of the removal central area is to form the second opening; And
E) the described Semiconductor substrate in described the second opening forms gate oxide layers.
2. manufacture method as claimed in claim 1 is characterized in that, described b) tectal formation method described in the step, comprising:
On described Semiconductor substrate, be formed with successively the first oxide skin(coating) and the first nitride layer, be formed with the patterns of openings that exposes described Semiconductor substrate in described the first oxide skin(coating) and described the first nitride layer, wherein, the corresponding described first area of described patterns of openings, described raceway groove central area and described second area;
Sidewall in described patterns of openings inboard forms side wall, and the material of described side wall is oxide;
Form the second oxide skin(coating) with described the first nitride layer in described patterns of openings, wherein, the thickness of described the second oxide skin(coating) is less than the thickness of described the first oxide skin(coating);
In described patterns of openings, form the nitride packed layer; And
Remove described the second oxide skin(coating) on described side wall and described nitride packed layer both sides and described the first nitride layer, have the described cover layer of described the first opening with formation.
3. manufacture method as claimed in claim 2 is characterized in that, the formation method of described nitride packed layer comprises:
Form layer of nitride material at described the second oxide skin(coating), described layer of nitride material is filled up described patterns of openings at least;
Remove the described layer of nitride material of described patterns of openings outside, to form described nitride packed layer.
4. manufacture method as claimed in claim 2 is characterized in that, described d) remove the tectal method on the described raceway groove central area in the step, comprising:
Described nitride packed layer is carried out etching;
Remaining described the second oxide skin(coating) is carried out etching.
5. the method for claim 1 is characterized in that, adopts injection technology doped with fluorine in the described first area of described Semiconductor substrate and described second area.
6. method as claimed in claim 5 is characterized in that, the employed gas of described injection technology is fluorine gas.
7. method as claimed in claim 5 is characterized in that, the dosage of the described fluorine that injects in the described injection technology is 1 * 10
13-5 * 10
15/ square centimeter.
8. method as claimed in claim 5 is characterized in that, the Implantation Energy of described injection technology is 1-100KeV.
9. manufacture method as claimed in claim 1 is characterized in that, the formation method of described gate oxide layers is thermal oxidation method.
10. manufacture method as claimed in claim 1 is characterized in that, described method is at described e) also comprise after the step:
F) form the step of grid at described gate oxide layers.
11. manufacture method as claimed in claim 10 is characterized in that, described f) step comprises:
At described e) device that obtains of step forms gate material layers, and described gate material layers is filled up described the second opening at least;
Remove the described gate material layers of described the second opening outside;
Remove remaining cover layer, with in described first area, described raceway groove central area and described second area form described grid.
12. manufacture method as claimed in claim 11 is characterized in that, described method is at described f) also comprise after the step:
G) in the described Semiconductor substrate of described grid both sides, form the first shallow doped region and source electrode and the second shallow doped region and drain electrode.
13. manufacture method as claimed in claim 12 is characterized in that, described g) step comprises:
Form the first clearance wall in the both sides of described grid;
Carry out shallow doping injection technology, in the described Semiconductor substrate of described grid both sides, to form the described first shallow doped region and the described second shallow doped region;
The outside at described first clearance wall of described grid both sides forms the second clearance wall;
Execution source/drain electrode injection technology is to form described source electrode and described drain electrode in the described Semiconductor substrate of described grid both sides.
14. manufacture method as claimed in claim 13 is characterized in that, the material of described the first clearance wall is oxide, and the material of described the second clearance wall is nitride.
15. manufacture method as claimed in claim 1 is characterized in that, described gate oxide layers is at the thickness of described first area and the described second area thickness greater than described raceway groove central area.
16. a semiconductor device structure is characterized in that, comprising:
Semiconductor substrate;
The grid that forms in described Semiconductor substrate, and the source electrode and the drain electrode that are arranged in the described Semiconductor substrate of described grid both sides, described grid comprises gate oxide layers, and the thickness of the described gate oxide layers of the overlapping region of described grid and described source electrode and described drain electrode is greater than the thickness of the described gate oxide layers of described channel region.
17. semiconductor device structure as claimed in claim 16 is characterized in that, is doped with fluorine in the described Semiconductor substrate of the overlapping region of described grid and described source electrode and described drain electrode.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956458A (en) * | 2011-08-23 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method for same |
| CN106328595A (en) * | 2015-07-01 | 2017-01-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
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| US20110024829A1 (en) * | 2009-07-30 | 2011-02-03 | Hynix Semiconductor Inc. | Semiconductor device having voids along buried gates and method for manufacturing the same |
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| US20030082861A1 (en) * | 2001-10-29 | 2003-05-01 | Nec Corporation | Method for fabricating a MOSFET |
| US20110024829A1 (en) * | 2009-07-30 | 2011-02-03 | Hynix Semiconductor Inc. | Semiconductor device having voids along buried gates and method for manufacturing the same |
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| CN102956458A (en) * | 2011-08-23 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method for same |
| CN102956458B (en) * | 2011-08-23 | 2015-05-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method for same |
| CN106328595A (en) * | 2015-07-01 | 2017-01-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
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| CN102956485B (en) | 2015-12-02 |
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