CN102955308B - Array substrate for display device and method of fabricating the same - Google Patents
Array substrate for display device and method of fabricating the same Download PDFInfo
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- CN102955308B CN102955308B CN201210287676.4A CN201210287676A CN102955308B CN 102955308 B CN102955308 B CN 102955308B CN 201210287676 A CN201210287676 A CN 201210287676A CN 102955308 B CN102955308 B CN 102955308B
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Abstract
The invention discloses an array substrate for a display device and a method of fabricating the same. The device comprises a substrate, a grid line formed on the substrate along a first direction; a data line formed above the substrate along a second direction, wherein the data line and the grid line are intersected with each other to limit a pixel region; a film transistor formed in the pixel region and having a drain, a grid connected with the grid line and a source connected with the data line; a pixel electrode formed in the pixel region and connected with the drain; a first auxiliary grid pattern formed above the grid line and contacted with the grid line; and a first auxiliary data pattern formed above the data line a nd contacted with the data line.
Description
This application claims No. 10-2011-0082808th, the korean patent application enjoying in and submit on August 19th, 2011 and the right of priority of No. 10-2012-0067842nd, korean patent application submitted on June 25th, 2012, in order to all objects, described patented claim is incorporated to herein by quoting, as described patented claim is all set forth at this.
Technical field
Present disclosure relates to a kind of array base palte for display device, particularly relates to a kind of array base palte of the display device for comprising thin film transistor (TFT), and the manufacture method of this array base palte.
Background technology
Along with the fast development of infotech, need the various display device for showing image.Flat pannel display (FPD) device of such as liquid crystal display (LCD) device, plasma display (PDP) device and Organic Light Emitting Diode (OLED) device and so on has been proposed.
In described FPD device, LCD device because size is little, lightweight, slim body and advantage low in energy consumption be used widely.
Comprise the pixel of arranging in the matrix form and be used widely for the active matrix type display of the open/close on-off element controlling each pixel.Active matrix type display comprises array base palte, and described array base palte is formed grid line, data line, on-off element and pixel electrode.Hereinafter with reference to accompanying drawing, array base palte is described.
Fig. 1 is the planimetric map of the array base palte for display device represented according to prior art.
In FIG, grid line 22 and data line 52 intersected with each other to limit pixel region P.Thin film transistor (TFT) T is connected with grid line 22 and data line 52.
Thin film transistor (TFT) T comprises grid 24, active layer 42, source electrode 54 and drain electrode 56.Grid 24 is connected with grid line 22, and source electrode 54 is connected with data line 52, and drains and 56 to separate with source electrode 54.Active layer 42 is exposed between source electrode 54 and drain electrode 56, and the expose portion of active layer 42 becomes the raceway groove of thin film transistor (TFT) T.
Pixel electrode 72 to be formed in pixel region P and to be connected with the drain electrode 56 of thin film transistor (TFT) T by drain contact hole 62.
With reference to Fig. 2, the cross section structure according to the array base palte for display device of prior art is described.
Fig. 2 is the sectional view of the array base palte for display device represented according to prior art, and the cross section that Fig. 2 intercepts corresponding to the II-II line along Fig. 1.
In Fig. 2, the grid 24 being formed with grid line 22 on the substrate 10 and being connected with grid line 22, and gate insulation layer 30 is formed on grid line 22 and grid 24.
Gate insulation layer 30 is formed with the active layer 42 of intrinsic silicon above grid 24, and on active layer 42, is formed with the ohmic contact layer 44 of doped silicon.
Ohmic contact layer 44 is formed data line 52, source electrode 54 and drain electrode 56.Data line 52, source electrode 54 and drain electrode 56 are formed with passivation layer 60.Passivation layer 60 comprises the drain contact hole 62 exposing drain electrode 56.
Passivation layer 60 is formed with pixel electrode 72, and pixel electrode 72 is connected with drain electrode 56 by drain contact hole 62.
Recently, because display device is required to have large scale and high definition, so such as the length of the signal wire of grid line 22 and data line 52 and so on becomes longer.So the resistance of signal wire increases, and causes signal delay.In addition, because actuating speed improves, so be applied to the load rise of signal wire.For addressing these problems, people have carried out various trial.
Such as, the width by widening signal wire can reduce the resistance of signal wire.In this case, because the area of pixel region reduces, make aperture than reducing and brightness reduction.Here, brightness improves by the amount increasing the light supplied.But this makes power consumption raise, and luminescence efficiency reduces.
Alternately, the thickness by thickening signal wire can reduce the resistance of signal wire.But, signal wire by deposit metallic material to form metal level and optionally composition (pattern) described metal level and being formed.So, in order to thicken the thickness of signal wire, the thickness of described metal level should be thickeied, and then also increase for the amount of the metal material deposited.In addition, the amount for the etching agent of metal level described in composition also increases.Therefore, the manufacturing cost of array base palte improves.
Meanwhile, some metal material with substrate contacts in there is bad performance, and when these metal materials are formed thick, may to rupture or peel off from substrate.Therefore, the increase of signal wire thickness has limit.
Summary of the invention
Therefore, the present invention relates to the manufacture method of a kind of array base palte for display device and described array base palte, described array base palte and manufacture method substantially eliminate due to the limitation of prior art and defect and the one or more problems caused.
An advantage of the present invention there are provided and a kind ofly can reduce the array base palte for display device of signal wire resistance and the manufacture method of described array base palte.
Another advantage of the present invention there are provided a kind of can improve aperture than and the array base palte for display device of brightness and the manufacture method of described array base palte.
Other feature of the present invention and advantage will be illustrated in the following description, and a part is wherein apparent from instructions, maybe can by learning enforcement of the present invention.These and other advantages of the present invention can be realized by the structure specifically noted in instructions, claims and accompanying drawing and be obtained.
For realizing these and other advantages, object according to the embodiment of the present invention, as described in and summary concrete at this, a kind of array base palte for display device comprises: substrate; Grid line, described grid line is formed on the substrate along first direction; Data line, described data line is formed in the top of described substrate along second direction, wherein said data line and described grid line intersected with each other to limit pixel region; Thin film transistor (TFT), described thin film transistor (TFT) is formed in described pixel region, and the source electrode that there is drain electrode, the grid be connected with described grid line and be connected with described data line; Pixel electrode, described pixel electrode is formed in described pixel region, and is connected with described drain electrode; First auxiliary grid pattern, described first auxiliary grid pattern is formed in the top of described grid line and contacts with described grid line; And the first auxiliary data pattern, described first auxiliary data pattern be formed in described data line top and with described data line contact.
In addition, the above array base palte for display device can comprise further: gate insulation layer, and described gate insulation layer covers described grid line and described grid, and in the below of described data line; Passivation layer, described passivation layer is formed on described data line and described gate insulation layer; First contact hole, described first contact hole is formed in described passivation layer and described gate insulation layer, and exposes described grid line along described first direction; And second contact hole, described second contact hole is formed in described passivation layer, and exposes described data line along described second direction, and wherein said first auxiliary grid pattern can be formed in described first contact hole; And described first auxiliary data pattern can be formed in described second contact hole.
In addition, array base palte above for display device can comprise further: drain contact pattern, wherein said passivation layer can be formed in further in described drain electrode and to comprise drain contact hole, described drain contact pattern can be formed in described drain contact hole and to contact described drain electrode, and described pixel electrode can cover and contact described drain contact pattern.
In addition, the above array base palte for display device can comprise further: the second auxiliary grid pattern, and described second auxiliary grid pattern is formed on described first auxiliary grid pattern, to cover, to contact and to protect described first auxiliary grid pattern; And the second auxiliary data pattern, described second auxiliary data pattern is formed on described first auxiliary data pattern, to cover, to contact and to protect described first auxiliary data pattern.
In addition, above in the array base palte of display device, described second auxiliary grid pattern can be formed by the material identical with the material of described pixel electrode with described second auxiliary data pattern.
In addition, above in the array base palte of display device, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method (plating).
In addition, above in the array base palte of display device, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.
In addition, above in the array base palte of display device, described first auxiliary grid pattern and described first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, above in the array base palte of display device, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, above in the array base palte of display device, described first auxiliary data pattern can be integrally formed along described data line.
In addition, the above array base palte for display device can comprise further: concentric line, and described concentric line is formed between adjacent grid line, and parallel with described grid line, and wherein said gate insulation layer can cover described concentric line further; Capacitance electrode, described capacitance electrode is formed in the top of described concentric line, and the described capacitance electrode overlapped each other and described concentric line form holding capacitor together with the described gate insulation layer between described capacitance electrode and described concentric line; And capacitance contact pattern, wherein said passivation layer can be formed on described capacitance electrode further, and described passivation layer comprises capacitance contact hole, described capacitance contact pattern can be formed in described capacitance contact hole and to contact described capacitance electrode, and described pixel electrode can cover and contact described capacitance contact pattern.
In addition, above in the array base palte of display device, described drain contact pattern, described first auxiliary grid pattern, described first auxiliary data pattern and described capacitance contact pattern are formed by plating method.
In addition, above in the array base palte of display device, described drain contact pattern, described first auxiliary grid pattern, described first auxiliary data pattern and described capacitance contact pattern can be formed by copper, chromium or nickel.
In addition, above in the array base palte of display device, described first auxiliary grid pattern and described first auxiliary data pattern each can comprise the first plating layer of being formed by copper and the second plating layer formed by nickel on described first plating layer, and described second plating layer is thinner than described first plating layer.
On the other hand, a kind of method manufactured for the array base palte of display device comprises the following steps: on substrate, form grid line along first direction, and form grid on the substrate, wherein said grid extends from described grid line; Form the gate insulation layer covering described grid line and described grid; Described gate insulation layer is formed with active layer above described grid, described active layer forms ohmic contact layer; Described gate insulation layer forms data line along second direction, and on described ohmic contact layer, form source electrode and drain electrode, wherein said data line and described grid line intersected with each other to limit pixel region, described source electrode extends from described data line, and described drain electrode and described source electrode are separated above described grid; Form the first auxiliary grid pattern to contact described grid line, and form the first auxiliary data pattern to contact described data line; And pixel electrode is formed in described pixel region, described pixel electrode is connected with described drain electrode.
In addition, above method can be further comprising the steps: in described data line, described source electrode and described drain electrode, form passivation layer; And in described passivation layer and described gate insulation layer, form the first contact hole to expose described grid line, and in described passivation layer, form the second contact hole to expose described data line, wherein said first auxiliary grid pattern can be formed in described first contact hole, and described first auxiliary data pattern can be formed in described second contact hole.
In addition, above method can be further comprising the steps: in described passivation layer, form drain contact hole, to expose described drain electrode; And in described drain contact hole, form drain contact pattern, to contact described drain electrode.
In addition, in the step forming pixel electrode, the second auxiliary grid pattern can be formed on described first auxiliary grid pattern, to cover and to contact described first auxiliary grid pattern, and the second auxiliary data pattern can be formed on the first auxiliary data pattern, to cover and to contact described first auxiliary data pattern.
In addition, in above method, described second auxiliary grid pattern can be formed by the material identical with the material of described pixel electrode with described second auxiliary data pattern.
In addition, in the step forming grid line, between adjacent grid line, concentric line can be formed abreast with described grid line; In the step forming gate insulation layer, described gate insulation layer can cover described concentric line further; In the step being formed with active layer, capacitance electrode can be formed above described concentric line, and the described capacitance electrode overlapped each other and described concentric line can form holding capacitor together with the described gate insulation layer between described capacitance electrode and described concentric line; In the step forming drain contact hole, capacitance contact hole can be formed in described passivation layer, to expose described capacitance electrode; In the step of formation first auxiliary grid pattern, capacitance contact pattern can be formed in described capacitance contact hole, to contact described capacitance electrode; And in the step forming pixel electrode, described pixel electrode can cover further and contact described capacitance contact pattern.
In addition, in above method, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.
In addition, in above method, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.
In addition, in above method, described capacitance contact pattern, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.
In addition, in above method, described first auxiliary grid pattern and described first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, in above method, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, in above method, described capacitance contact pattern, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, in above method, described first auxiliary data pattern can be integrally formed along described data line.
In addition, in above method, form described first auxiliary grid pattern and described first auxiliary data pattern can comprise the first plating layer of being formed and being formed by copper and on described first plating layer, form the second plating layer formed by nickel, and wherein said second plating layer is thinner than described first plating layer.
It should be understood that summary description is above all exemplary and explanatory with detailed description below, be intended to further illustrate claimed the invention provides.
Accompanying drawing explanation
Included accompanying drawing is used to provide a further understanding of the present invention, and accompanying drawing to be incorporated in present specification and to form a part for present specification.Accompanying drawing shows embodiments of the present invention, and is used from instructions one and explains principle of the present invention.
In the accompanying drawings:
Fig. 1 is the planimetric map of the array base palte for display device represented according to prior art;
Fig. 2 is the sectional view of the array base palte for display device represented according to prior art, and the cross section that Fig. 2 intercepts corresponding to the II-II line along Fig. 1;
Fig. 3 is the planimetric map of the array base palte for display device represented according to exemplary embodiment of the invention;
Fig. 4 is the sectional view intercepted along the IV-IV line of Fig. 3;
Fig. 5 A to Fig. 5 D represents the planimetric map according to the array base palte in each step of the method for exemplary embodiment of the invention manufacturing array substrate;
Fig. 6 A to Fig. 6 F represents the sectional view according to the array base palte in each step of the method for exemplary embodiment of the invention manufacturing array substrate, and the cross section that Fig. 6 A to Fig. 6 F intercepts corresponding to the VI-VI line along Fig. 5 A to Fig. 5 D;
Fig. 7 represents according to the process flow diagram without electric plating (electroless plating) method technique of the present invention;
Fig. 8 represents another sectional view for the array base palte of display device according to exemplary embodiment of the invention;
Fig. 9 is the planimetric map of the array base palte for display device represented according to another embodiment of the present invention; And
Figure 10 is the sectional view intercepted along the IX-IX line of Fig. 9.
Embodiment
Be described with detailed reference to embodiments of the present invention now, some examples are wherein shown in the drawings.
Fig. 3 is the planimetric map of the array base palte for display device represented according to exemplary embodiment of the invention.Fig. 4 is the sectional view intercepted along the IV-IV line of Fig. 3.
In figs. 3 and 4, transparent insulation substrate 110 is formed with grid line 122 and the grid 124 of conductive material.Grid line 122 is formed along first direction, and grid 124 extends from grid line 122.Between adjacent grid line 122, be formed with concentric line 126, and concentric line 126 is parallel with grid line 122.
Grid line 122, grid 124 and concentric line 126 are formed with the gate insulation layer 130 of silicon nitride or monox, and gate insulation layer 130 covers grid line 122, grid 124 and concentric line 126.
Gate insulation layer 130 is formed with the active layer 142 of intrinsic amorphous silicon above grid 124.Active layer 142 is formed the ohmic contact layer 144 of doped amorphous silicon.
Ohmic contact layer 144 is formed the data line 152 of the conductive material of such as metal and so on, source electrode 154 and drain electrode 156.Data line 152 is formed along the second direction vertical with first direction, and data line 152 intersects with grid line 122 and concentric line 126.Data line 152 limits pixel region P together with grid line 122.Source electrode 154 extends from data line 152, and drain 156 and source electrode 154 separate above grid 124.Gate insulation layer 130 is formed with capacitance electrode 158 above concentric line 126, and capacitance electrode 158 by with data line 152, source electrode 154 and drain 156 the identical material of material formed.Here, intrinsic silicon pattern and doped silicon pattern is formed with at data line 152 and capacitance electrode 158 below each.
Source electrode 154 and drain electrode 156, active layer 142 and grid 124 define thin film transistor (TFT) T, and the active layer 142 be exposed between source electrode 154 and drain electrode 156 becomes the raceway groove of thin film transistor (TFT) T.The capacitance electrode 158 overlapped each other and concentric line 126 together form holding capacitor with the dielectric gate insulation layer 130 of conduct between which.
Data line 152, source electrode 154 and drain electrode 156 and capacitance electrode 158 are formed with passivation layer 160.Passivation layer 160 is formed by the inorganic insulating material of such as silicon nitride and monox and so on or the organic insulation of such as acryl resin and so on.Passivation layer 160 comprises the drain contact hole 162 exposing drain electrode 156 and the capacitance contact hole 164 exposing capacitance electrode 158.Passivation layer 160 comprises the first contact hole 166 exposing grid line 122 along first direction further together with gate insulation layer 130, and passivation layer 160 comprises the second contact hole 168 exposing data line 152 along second direction further.
In drain contact hole 162, be formed with drain contact pattern 172, and this drain contact pattern 172 contacts drain electrode 156.Capacitance contact pattern 174 is formed in capacitance contact hole 164, and this capacitance contact pattern 174 hand capacity electrode 158.In the first contact hole 166, be formed with the first auxiliary grid pattern 176, and this first auxiliary grid pattern 176 contacts grid line 122.In the second contact hole 168, be formed with the first auxiliary data pattern 178, and this first auxiliary data pattern 178 contacts data line 152.
Drain contact pattern 172, capacitance contact pattern 174, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 are formed by plating method, and difference filling contact hole 162,164,166 and 168.Drain contact pattern 172, capacitance contact pattern 174, first auxiliary grid pattern 176 can have the height identical with passivation layer 160 with the first auxiliary data pattern 178, or can exceed passivation layer 160.Drain contact pattern 172, capacitance contact pattern 174, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can have identical thickness, and therefore drain contact pattern 172, capacitance contact pattern 174 and the comparable first auxiliary grid pattern 176 of the first auxiliary data pattern 178 more exceed passivation layer 160.
Passivation layer 160 in pixel region P is formed with the pixel electrode 182 of transparent conductive material.Pixel electrode 182 covers and contacts drain contact pattern 172 and capacitance contact pattern 174, and pixel electrode 182 is electrically connected with drain electrode 156 and capacitance electrode 158.In addition, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 are formed with the second auxiliary grid pattern 184 respectively and the second auxiliary data pattern 186, second auxiliary grid pattern 184 is formed by the material identical with pixel electrode 182 with the second auxiliary data pattern 186.Second auxiliary grid pattern 184 covers respectively with the second auxiliary data pattern 186, contact and protect the first auxiliary grid pattern 176 and the first auxiliary data pattern 178.
In embodiments of the present invention, when forming drain contact hole 162 and capacitance contact hole 164, formed expose respectively grid line 122 and data line 152 the first contact hole 166 and the second contact hole 168, and form the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 respectively in this first contact hole 166 and the second contact hole 168.Thus, the resistance of grid line 122 and data line 152 can be reduced.Therefore, can signal delay be prevented, and can load be reduced.In addition, the width of grid line 122 and data line 152 can be reduced, and aperture ratio and brightness can be improved.
The method of manufacturing array substrate is described in detail with reference to Fig. 5 A to Fig. 5 D, Fig. 6 A to Fig. 6 F, Fig. 3 and Fig. 4.Fig. 5 A to Fig. 5 D represents the planimetric map according to the array base palte in each step of the method for exemplary embodiment of the invention manufacturing array substrate.Fig. 6 A to Fig. 6 F represents the sectional view according to the array base palte in each step of the method for exemplary embodiment of the invention manufacturing array substrate, and the cross section that Fig. 6 A to Fig. 6 F intercepts corresponding to the VI-VI line along Fig. 5 A to Fig. 5 D.
In Fig. 5 A and Fig. 6 A, by utilizing sputtering method to deposit the conductive material of such as metal and so on, and carry out conductive material described in composition by the photoetching process that make use of photomask, in the transparent insulation substrate 110 of such as glass or plastics and so on, form grid line 122, grid 124 and concentric line 126 thus.Grid line 122 is formed along first direction, and concentric line 126 is arranged between adjacent grid line 122 and parallel with grid line 122.Grid 124 extends from grid line 122.
Grid line 122, grid 124 and concentric line can be formed by aluminium, molybdenum, nickel, chromium, copper or their alloy.Here, because copper has relatively low resistivity, so use copper more effectively to reduce the resistance of line and to prevent signal delay.When copper is being used, cushion can be formed below layers of copper, to improve the surface nature with substrate 110.Cushion 110 can be formed by molybdenum, titanium, tantalum or their alloy.
In Fig. 5 B and Fig. 6 B to Fig. 6 D, grid line 122, grid 124 and concentric line 126 form gate insulation layer 130, and the photoetching process then by make use of photomask is formed with active layer 142, ohmic contact layer 144, data line 152, source electrode 154, drain electrode 156 and capacitance electrode 158 on gate insulation layer 130.
This will describe in more detail in following content.
In fig. 6b, grid line 122, grid 124 and concentric line 126 sequentially form gate insulation layer 130, intrinsic silicon layer 140, doped silicon layer 141 and metal level 150.Here, gate insulation layer 130, intrinsic silicon layer 140 and doped silicon layer 141 are formed by chemical vapor deposition (CVD) method.Metal level 150 is formed by the physical vapor deposition (PVD) method of such as sputtering and so on.Gate insulation layer 130 can by silicon nitride (SiNx) or monox (SiO
2) formed.Intrinsic silicon layer 140 can be formed by intrinsic amorphous silicon, and doped silicon layer 141 can be formed by boron-doping or phosphorus-doped amorphous silicon.Metal level 150 can be formed by aluminium, molybdenum, nickel, chromium, copper or their alloy.Here, because copper has relatively low resistivity, so use copper more effectively to reduce the resistance of line and to prevent signal delay.When copper is being used, cushion can be formed below layers of copper, to improve the surface nature with substrate 110.Cushion 110 can be formed by molybdenum, titanium, tantalum or their alloy.
Metal level 150 is formed photoresist layer (not shown), and mask M is set above this photoresist layer.Mask M comprises the shading light part BA for shading light, the transmitted light part TA for transmitted light and the half transmitting light part HTA for partly transmitted light.Half transmitting light part HTA can comprise semitransparent layer or multiple slit.
Next, the light of such as ultraviolet and so on is by mask M photolithography glue-line, and photoresist layer is exposed.By the photoresist layer development after exposure, thus form the first photoetching agent pattern 192 and the second photoetching agent pattern 194.First photoetching agent pattern 192 is corresponding with the shading light part BA of mask M, and has the first thickness.Second photoetching agent pattern 194 is corresponding with half transmitting light part HTA, and has second thickness thinner than the first thickness.Second photoetching agent pattern 194 is arranged on the top of grid 124, and the first photoetching agent pattern is arranged on the both sides of the second photoetching agent pattern 194 and the top of concentric line 126.
In figure 6 c, sequentially etch the intrinsic silicon layer 140 of the metal level 150 of Fig. 6 B, the doped silicon layer 141 of Fig. 6 B and Fig. 6 B by the first photoetching agent pattern 192 and the second photoetching agent pattern 194 that utilize Fig. 6 B as etching mask, thus form data line 152, source drain pattern 150a, doped semiconductor pattern 141a, active layer 142 and capacitance electrode 158.Here, carry out wet etching by the metal level 150 of mordant to Fig. 6 B, carry out dry etching by the intrinsic silicon layer 140 of etching gas to the doped silicon layer 141 of Fig. 6 B and Fig. 6 B.
Data line 152 is formed along the second direction vertical with first direction, and intersects with grid line 122 and concentric line 126.Data line 152 and grid line 122 limit pixel region P.Source drain pattern 150a is connected with data line 152.Active layer 142, doped semiconductor pattern 141a and source drain pattern 150a are sequentially arranged on the top of grid.Capacitance electrode 158 is arranged on the top of concentric line 126 and overlapping with concentric line 126.Here, intrinsic silicon pattern and doped silicon pattern are formed in data line 152 and capacitance electrode 158 below each.
Then, removed second photoetching agent pattern 194 of Fig. 6 B by ashing (ashing) technique, thus expose the source drain pattern 150a above grid 124.Now, the first photoetching agent pattern 192 is partially removed, and the thickness of this first photoetching agent pattern 192 reduces.
In figure 6d, the source drain pattern 150a of Fig. 6 C and the doped semiconductor pattern 141a of Fig. 6 C is etched as etching mask by using first photoetching agent pattern 192 of Fig. 6 C, thus form source electrode 154 and drain 156 and ohmic contact layer 144, and expose active layer 142.Source electrode 154 is connected with data line 152, and drains 156 in the face of source electrode 154 separating with source electrode 154 relative to grid 124.
Next, the first photoetching agent pattern 192 is removed.
Here, by with form data line 152, source electrode 154 and drain 156 the identical photoetching process of photoetching process be formed with active layer 142.Also by from form data line 152, source electrode 154 and drain 156 the different photoetching process of photoetching process be formed with active layer 142.
Then, in Fig. 5 C and Fig. 6 E, passivation layer 160 is formed by the inorganic insulating material depositing such as silicon nitride or monox and so on, and carry out patterned passivation layer 160 by the photoetching process that make use of photomask, thus form drain contact hole 162, capacitance contact hole 164, first contact hole 166 and the second contact hole 168.Now, corresponding with the first contact hole 166 gate insulation layer 130 is also optionally removed.Drain contact hole 162 exposes drain electrode 156, and capacitance contact hole 164 exposes capacitance electrode 158.First contact hole 166 exposes the grid line 122 between adjacent data line 152, and the second contact hole 168 exposes the data line 152 between adjacent grid line 122.
Meanwhile, passivation layer 160 can be formed by the organic insulation of such as acryl resin and so on, and in this case, passivation layer 160 has flat top surface.
In Fig. 5 D and Fig. 6 F, in drain contact hole 162, capacitance contact hole 164, first contact hole 166 and the second contact hole 168, form drain contact pattern 172, capacitance contact pattern 174, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 by plating method respectively.Here, drain contact pattern 172, capacitance contact pattern 174, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can have the thickness of about 0.2 micron to about 5 microns.Valuably, drain contact pattern 172, capacitance contact pattern 174, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can have the thickness of about 2 microns to about 3 microns, with the orientation problem of the resistance the liquid crystal molecule preventing the step due to pattern from causing that reduce line.Drain contact pattern 172, capacitance contact pattern 174, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can fill drain contact hole 162, capacitance contact hole 164, first contact hole 166 and the second contact hole 168 respectively, and can exceed passivation layer 160.
Drain contact pattern 172, capacitance contact pattern 174, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can be formed by the conductive material of such as copper, chromium or nickel and so on.Valuably, drain contact pattern 172, capacitance contact pattern 174, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can be formed by copper, to reduce the resistance of line further.
In this embodiment of the present invention, the second contact hole 168 can be formed in the top of the data line 152 between adjacent grid line 122.This second contact hole 168 can be formed in the top of the data line 152 intersected with grid line 122, and may extend to next pixel region P.The second adjacent contact hole 168 can be connected to each other.Therefore, the first auxiliary data pattern 178 in the second contact hole 168 can be integrally formed along data line 152, to reduce the resistance of line further.In other words, whole first auxiliary data pattern can be formed continuously along data line.
Drain contact hole 172, capacitance contact pattern 174, first auxiliary grid pattern 176 and the first auxiliary data pattern 178 are by being formed without electric plating method, and this will describe subsequently.
Next, in figs. 3 and 4, deposit transparent conductive material, and carry out transparent conductive material described in composition by the photoetching process that make use of photomask, thus form pixel electrode 182, second auxiliary grid pattern 184 and the second auxiliary data pattern 186.Pixel electrode 182 is arranged on the passivation layer 160 in pixel region P.Pixel electrode 182 contacts and covers drain contact pattern 172 and capacitance contact pattern 174, and pixel electrode 182 is electrically connected with drain electrode 156 and capacitance electrode 158.Second auxiliary grid pattern 184 contacts and covers the first auxiliary grid pattern 176, and the second auxiliary data pattern 186 contacts and cover the first auxiliary data pattern 178.Described transparent conductive material can be tin indium oxide or indium zinc oxide.
Second auxiliary grid pattern 184 and the second auxiliary data pattern 186 prevent the oxidation of the first auxiliary grid pattern 176 and the first auxiliary data pattern 178, and protect this first auxiliary grid pattern 176 and the first auxiliary data pattern 178.
Describe according to of the present invention without electric plating method with reference to Fig. 7.Fig. 7 represents according to the process flow diagram without electric plating method technique of the present invention.Will explain as an example to cover copper coating.
In the figure 7, at first step ST1, for increasing the adhesion between basalis (base layer) and plating layer, performing cleaning procedure, removing particle or organic substance, thus the surface of clear base bottom.Now, the substrate including basalis above can be exposed to organic solution about 30 seconds, and described basalis can comprise copper.
Then, at second step ST2, perform adjusting process (conditioning process), remove the oxide film on basalis.The surface of basalis has polarity, and described polarity is such as just (+) polarity.Now, the substrate including basalis above can be exposed to and comprise sulfuric acid (H
2sO
4) solution about 30 seconds.Here, second step ST2 can be omitted.
Next, at third step ST3, perform activating process (activating process), palladium (Pd) is adsorbed onto the surface of basalis.Palladium plays catalyzer.The substrate including basalis above can be exposed to the acid solution about 60 seconds being wherein dissolved with palladium ion.The copper of basalis loses electronics due to the catalytic performance of displaced type (substitution-type) palladium ion, becomes ion.Palladium ion reduces and is adsorbed to the surface of basalis.Here, acid solution can be sulfuric acid (H
2sO
4) based sols.
At the 4th step ST4, perform without electric plating technique, form copper plate on the base layer.Now, copper plating solution is used.Copper plating solution comprises slaine, reductive agent, complexing agent (complexant), stabilizing agent and promoter (exaltant) (in other words rate accelerating material (accelerator)), and copper plating solution is alkalescence (alkali).
Reductive agent is supplied to copper ion electronics.The electromotive force (potential) of reductive agent can lower than the equilibrium potential of copper ion (equilibrium potential).Reductive agent can comprise formaldehyde, one of dimethylamino monoborane (dimethylamineborane, DMAD) and sodium hypophosphite.Such as, when using formaldehyde as reductive agent, the reduction process due to formaldehyde can generate hydrogen ion (H+) and hydroxide ion (OH-), and can change the pH value of plating solution.
Complexing agent is combined with copper ion, prevents copper ion and reductive agent from reacting and precipitating.Complexing agent can comprise sodium-potassium tartrate (sodium potassium tartrate), ethylenediamine tetraacetic acid (ethylenediaminetetraacetic acid, EDTA), one of glycollic acid (glycolic acid) and triethanolamine (triethanol amine), described sodium-potassium tartrate can be called as Rochelle (Rochelle) salt.
Stabilizing agent is adsorbed onto on dust (dust) or copper particle, prevents copper ion from contacting with reductive agent.Stabilizing agent can comprise oxygen, thiocarbamide, 2-mercaptobenzothiazole (2-mercaptobenzothiazole), one of DECTC (diethyldithiocarbamate) and vanadium pentoxide (vanadium pentoxide).
Promoter (or rate accelerating material) is for improving plating speed.Promoter can comprise prussiate, one of propionitrile (proprionitrile) and phenanthrolene (O-phenanthroline).
Therefore, when the exposure of substrates comprising the basalis being adsorbed with palladium is to copper plating solution, generate electronics due to the reduction process of reductive agent, copper ion and electronics are tied to be incorporated on palladium catalyst and are separated out (educe), thus form copper plate.In addition, the copper of plating plays autocatalysis, and forms copper plate further.
Here, the thickness of copper plate changed according to the composition of copper plating solution, component ratio and open-assembly time.Such as, when basalis is exposed to the copper plating solution about 1200 seconds comprising formaldehyde, Rochelle salt and 2-mercaptobenzothiazole, the copper plate of about 1.5 microns can be formed.
In this embodiment of the present invention, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 are by being formed without electric plating method.First auxiliary grid pattern 176 and the first auxiliary data pattern 178 are also formed by plating (electro plating) method.More particularly, for avoiding electrostatic during manufacturing array substrate and for check electric condition after manufacturing array substrate, defining the short-circuiting bar (shorting bar) connecting grid line and data line.First auxiliary grid pattern 176 and the first auxiliary data pattern 178 are formed by the electrochemical plating that make use of short-circuiting bar.
In this embodiment of the present invention, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 are respectively formed on grid line 122 and data line 152 by plating method.Reduce the resistance of grid line 122 and data line 152, and prevent signal delay.The load of line can be reduced.Now, because the width of grid line 122 and data line 152 can be reduced, and pixel region P can be extended, so can improve aperture ratio and brightness.Size and the resolution of display device are depended in the raising of aperture ratio.Compared with prior art, aperture ratio can improve about 10% to about 50%, and uprises along with the resolution of display device, can further improve aperture ratio.
Due to when formed drain contact hole 162 and capacitance contact hole 164 time and exposure grid line 122 and data line 152 after, auxiliary patterns 176 and 178 is formed by plating method simultaneously, therefore with separate the situation of plating grid line 122 with data line 152 and compare, can Simplified flowsheet, reduction manufacturing cost and the time of shortening.
In addition, if grid line 122 and data line 152 are separated plating, then grid line 122 and data line 152 are coated to plating twice in their cross part branch, and this will have relatively high step in cross part office.So due to the cause of step, the layer that cross section is formed may disconnect.But in the present invention, the not coating plating in cross part office due to grid line 122, so the layer that can avoid the formation of on cross section disconnects.In addition, if grid line 122 and data line 152 are separated plating, then the electrode of thin film transistor (TFT) T may by plating, and this just has the problem of the deterioration of such as thin film transistor (TFT) T and so on.But in the present invention, the electrode of thin film transistor (TFT) T not by plating, then avoids this problem.
Meanwhile, if the side of contact hole 162,164,166 and 168 is back taper when being formed contact hole 162,164,166 and 168 by patterned passivation layer 160, then due to the cause of back taper step, the layer formed below may disconnect.But in the present invention, metal pattern is formed in contact hole 162,164,166 and 168 by plating method.So, even if the side of contact hole 162,164,166 and 168 is back taper, the disconnection of the layer formed also can be prevented below.
In superincumbent embodiment, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 have single layer structure.First auxiliary grid pattern 176 and the first auxiliary data pattern 178 also have sandwich construction by the different material of plating.Especially, when the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 comprise copper, copper plate can form nickel coating further so that anti-oxidation also reduces the contact resistance with succeeding layer.
This describes with reference to Fig. 8.Fig. 8 represents another sectional view for the array base palte of display device according to exemplary embodiment of the invention.Identical Reference numeral will be used to refer to for the parts identical with above embodiment, and will omit the explanation to same parts.
In fig. 8, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 each comprise the first plating layer 176a or 178a and the second plating layer 176b or 178b.Second plating layer 176b or 178b has the thickness of the thickness being less than the first plating layer 176a or 178a.Here, drain contact pattern 172 and capacitance contact pattern 174 also have the double-decker of the first plating layer 172a or 174a and the second plating layer 172b or 174b.
Such as, first plating layer 172a, 174a, 176a and 178a is formed by plating copper, and second plating layer 172b, 174b, 176b and 178b is formed by plating nickel.Second plating layer 172b, 174b, 176b and 178b prevents first plating layer 172a, 174a, 176a and 178a oxidized, and is reduced in the contact resistance between one of pixel electrode 182, second auxiliary grid pattern 184 and second auxiliary data pattern 186 and first plating layer 172a, 174a, 176a or 178a.
First plating layer 172a, 174a, 176a and 178a can have and be more than or equal to about 0.2 micron and the thickness being less than or equal to about 5 microns, valuably, can have and be more than or equal to about 2 microns and the thickness being less than or equal to about 3 microns.Second plating layer 172b, 174b, 176b and 178b can have and be more than or equal to about 0.02 micron and the thickness being less than or equal to about 0.1 micron.
In above embodiment of the present invention, the concentric line overlapped each other and capacitance electrode constitute holding capacitor.Alternately, the structure of holding capacitor can change, and this describes with reference to Fig. 9 and Figure 10.
Fig. 9 is the planimetric map of the array base palte for display device represented according to another embodiment of the present invention.Figure 10 is the sectional view intercepted along the IX-IX line of Fig. 9.
In figure 9 and in figure 10, transparent insulation substrate 210 is formed with grid line 222 and the grid 224 of conductive material.Grid line 222 is formed along first direction, and grid 224 extends from grid line 222.
Grid line 222 and grid 224 are formed with the gate insulation layer 230 of silicon nitride or monox, and gate insulation layer 230 covers grid line 222 and grid 224.
Gate insulation layer 230 is formed with the active layer 242 of intrinsic amorphous silicon above grid 224.Active layer 242 is formed the ohmic contact layer 244 of doped amorphous silicon.
Ohmic contact layer 244 is formed the data line 252 of the conductive material of such as metal and so on, source electrode 254 and drain electrode 256.Data line 252 is formed along the second direction vertical with first direction, and data line 252 and grid line 222 intersect to limit pixel region P.Source electrode 254 extends from data line 252, and source electrode 254 faced by drain electrode 256 is also separated above grid 224 with source electrode 254.On gate insulation layer 230 and be formed with capacitance electrode 258 above the Part I of grid line 222, and capacitance electrode 258 is formed by with data line 252, source electrode 254 and the 256 identical materials that drain.Here, intrinsic silicon pattern and doped silicon pattern is formed with at data line 252 and capacitance electrode 258 below each.
Source electrode 254 and drain electrode 256, active layer 242 and grid 224 define thin film transistor (TFT) T, and the active layer 242 be exposed between source electrode 254 and drain electrode 256 becomes the raceway groove of thin film transistor (TFT) T.The capacitance electrode 258 overlapped each other and grid line 222 define holding capacitor with the dielectric gate insulation layer 230 of conduct between which.
Data line 252, source electrode 254 and drain electrode 256 and capacitance electrode 258 are formed with passivation layer 260.Passivation layer 260 is formed by the inorganic insulating material of such as silicon nitride and monox and so on or the organic insulation of such as acryl resin and so on.Passivation layer 260 comprises the drain contact hole 262 exposing drain electrode 256 and the capacitance contact hole 264 exposing capacitance electrode 258.Passivation layer 260 comprises the first contact hole 266 of the Part II exposing grid line 222 further together with gate insulation layer 230, and passivation layer 260 comprises the second contact hole 268 exposing data line 252 further.
In drain contact hole 262, be formed with drain contact pattern 272, and this drain contact pattern 272 contacts drain electrode 256.Capacitance contact pattern 274 is formed in capacitance contact hole 264, and this capacitance contact pattern 274 hand capacity electrode 258.In the first contact hole 266, be formed with the first auxiliary grid pattern 276, and this first auxiliary grid pattern 276 contacts grid line 222.In the second contact hole 268, be formed with the first auxiliary data pattern 278, and this first auxiliary data pattern 278 contacts data line 252.
Drain contact pattern 272, capacitance contact pattern 274, first auxiliary grid pattern 276 and the first auxiliary data pattern 278 are formed by plating method, and difference filling contact hole 262,264,266 and 268.Drain contact pattern 272, capacitance contact pattern 274, first auxiliary grid pattern 276 can have the height identical with the height of passivation layer 260 with the first auxiliary data pattern 278, or can exceed passivation layer 260.Drain contact pattern 272, capacitance contact pattern 274, first auxiliary grid pattern 276 and the first auxiliary data pattern 278 can have identical thickness, and therefore drain contact pattern 272, capacitance contact pattern 274 and the comparable first auxiliary grid pattern 276 of the first auxiliary data pattern 278 more exceed passivation layer 260.
Passivation layer 260 in pixel region P is formed with the pixel electrode 282 of transparent conductive material.Pixel electrode 282 covers and contacts drain contact pattern 272 and capacitance contact pattern 274, and pixel electrode 282 is electrically connected with drain electrode 256 and capacitance electrode 258.In addition, first auxiliary grid pattern 276 and the first auxiliary data pattern 278 are formed with the second auxiliary grid pattern 284 respectively and the second auxiliary data pattern 286, second auxiliary grid pattern 284 is formed by the material identical with pixel electrode 282 with the second auxiliary data pattern 286.Second auxiliary grid pattern 284 covers respectively with the second auxiliary data pattern 286, contact and protect the first auxiliary grid pattern 276 and the first auxiliary data pattern 278.
Meanwhile, capacitance electrode 258 can be omitted, in this case, pixel electrode 282 can overlapping grid line 222 to form holding capacitor.
Manufacture according to the array base palte of another embodiment of the present invention technique by Fig. 5 A to Fig. 5 D, Fig. 6 A to Fig. 6 F, Fig. 3 and Fig. 4.
In the manufacture method of array base palte according to the present invention and this array base palte, grid line and data line are formed with auxiliary patterns.In it is possible to the resistance reducing line, and signal delay can be prevented.The load of line can be reduced.In addition, the width of line can be reduced, and improve aperture ratio and brightness.Now, littlely on grid line and data line, form auxiliary patterns by plating technique simultaneously, simplify technique.Reduce manufacturing cost and shorten the time.
Meanwhile, grid line is not in the cross part office of grid line and data line by plating, and the layer that can avoid the formation of above cross section disconnects.In addition, the electrode of thin film transistor (TFT) is not by plating.In it is possible to avoid thin film transistor (TFT) deterioration.
Can make various modifications and variations when not departing from the spirit or scope of the present invention to the present invention, this will be readily apparent to persons skilled in the art.Therefore, the present invention is intended to contain the various modifications and variations of the present invention in the scope being included into appended claims and its equivalent.
Claims (26)
1., for an array base palte for display device, the described array base palte for display device comprises:
Substrate;
Grid line, described grid line is formed on the substrate along first direction;
Data line, described data line is formed in the top of described substrate along second direction, wherein said data line and described grid line intersected with each other to limit pixel region;
Thin film transistor (TFT), described thin film transistor (TFT) is formed in described pixel region, and the source electrode that there is drain electrode, the grid be connected with described grid line and be connected with described data line;
Passivation layer, described passivation layer is in described drain electrode and comprise drain contact hole;
Drain contact pattern, described drain contact pattern to be formed in described drain contact hole and to contact described drain electrode, and the outermost border of wherein said drain contact pattern is arranged in the outermost border of described drain electrode; Pixel electrode, described pixel electrode is formed in described pixel region, and is connected with described drain electrode, and wherein said pixel electrode covers and contacts described drain contact pattern, makes described drain contact pattern setting between described drain electrode and described pixel electrode;
First auxiliary grid pattern, described first auxiliary grid pattern is formed in the top of described grid line and contacts with described grid line; And
First auxiliary data pattern, described first auxiliary data pattern be formed in described data line top and with described data line contact.
2. the array base palte for display device according to claim 1, comprises further:
Gate insulation layer, described gate insulation layer covers described grid line and described grid, and in the below of described data line;
Described passivation layer, described passivation layer is formed on described data line and described gate insulation layer;
First contact hole, described first contact hole is formed in described passivation layer and described gate insulation layer, and exposes described grid line along described first direction; And
Second contact hole, described second contact hole is formed in described passivation layer, and exposes described data line along described second direction,
Wherein said first auxiliary grid pattern is formed in described first contact hole; And described first auxiliary data pattern is formed in described second contact hole.
3. the array base palte for display device according to claim 1, comprises further:
Second auxiliary grid pattern, described second auxiliary grid pattern is formed on described first auxiliary grid pattern, to cover, to contact and to protect described first auxiliary grid pattern; And
Second auxiliary data pattern, described second auxiliary data pattern is formed on described first auxiliary data pattern, to cover, to contact and to protect described first auxiliary data pattern.
4. the array base palte for display device according to claim 3, wherein said second auxiliary grid pattern is formed by the material identical with described pixel electrode with described second auxiliary data pattern.
5. the array base palte for display device according to claim 1 and 2, wherein said first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.
6. the array base palte for display device according to claim 2, wherein said drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.
7. the array base palte for display device according to claim 1 and 2, wherein said first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.
8. the array base palte for display device according to claim 2, wherein said drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.
9. the array base palte for display device according to claim 1 and 2, wherein said first
Auxiliary data pattern is integrally formed along described data line.
10. the array base palte for display device according to claim 2, comprises further:
Concentric line, described concentric line is formed between adjacent grid line, and parallel with described grid line, and wherein said gate insulation layer covers described concentric line further;
Capacitance electrode, described capacitance electrode is formed in the top of described concentric line, and the described capacitance electrode wherein overlapped each other and described concentric line form holding capacitor together with the described gate insulation layer between described capacitance electrode and described concentric line; And
Capacitance contact pattern,
Wherein said passivation layer is formed on described capacitance electrode further, and described passivation layer comprises capacitance contact hole, described capacitance contact pattern to be formed in described capacitance contact hole and to contact described capacitance electrode, and described pixel electrode covers and contacts described capacitance contact pattern.
11. array base paltes for display device according to claim 10, wherein said drain contact pattern, described first auxiliary grid pattern, described first auxiliary data pattern and described capacitance contact pattern are formed by plating method.
12. array base paltes for display device according to claim 10, wherein said drain contact pattern, described first auxiliary grid pattern, described first auxiliary data pattern and described capacitance contact pattern are formed by copper, chromium or nickel.
13. array base paltes for display device according to claim 1, wherein said first auxiliary grid pattern and described first auxiliary data pattern each comprise the first plating layer of being formed by copper and the second plating layer formed by nickel on described first plating layer, and described second plating layer is thinner than described first plating layer.
14. 1 kinds of manufactures are used for the method for the array base palte of display device, said method comprising the steps of:
Substrate forms grid line along first direction, and forms grid on the substrate, wherein said grid extends from described grid line;
Form the gate insulation layer covering described grid line and described grid;
Described gate insulation layer is formed with active layer above described grid, described active layer forms ohmic contact layer;
Described gate insulation layer forms data line along second direction, and on described ohmic contact layer, form source electrode and drain electrode, wherein said data line and described grid line intersected with each other to limit pixel region, described source electrode extends from described data line, and described drain electrode and described source electrode are separated above described grid;
Described drain electrode forms passivation layer, and described passivation layer comprises drain contact hole;
In described drain contact hole, form drain contact pattern, and drain described in described drain contact pattern contacts, the outermost border of wherein said drain contact pattern is arranged in the outermost border of described drain electrode;
Form the first auxiliary grid pattern to contact described grid line, and form the first auxiliary data pattern to contact described data line; And
In described pixel region, form pixel electrode, described pixel electrode is connected with described drain electrode, and wherein said pixel electrode covers and contacts described drain contact pattern, makes described drain contact pattern setting between described drain electrode and described pixel electrode.
15. methods according to claim 14, further comprising the steps:
Described data line and described source electrode form described passivation layer; And
In described passivation layer and described gate insulation layer, form the first contact hole, to expose described grid line, and form the second contact hole in described passivation layer, to expose described data line,
Wherein said first auxiliary grid pattern is formed in described first contact hole, and described first auxiliary data pattern is formed in described second contact hole.
16. methods according to claim 14, wherein in the step forming pixel electrode, described first auxiliary grid pattern forms the second auxiliary grid pattern, to cover and to contact described first auxiliary grid pattern, and on described first auxiliary data pattern, form the second auxiliary data pattern, to cover and to contact described first auxiliary data pattern.
17. methods according to claim 16, wherein said second auxiliary grid pattern is formed by the material identical with described pixel electrode with described second auxiliary data pattern.
18. methods according to claim 16, wherein:
In the step forming grid line, between adjacent grid line, form concentric line abreast with described grid line;
In the step forming gate insulation layer, described gate insulation layer covers described concentric line further;
In the step being formed with active layer, above described concentric line, form capacitance electrode, and the described capacitance electrode overlapped each other and described concentric line and the described gate insulation layer between described capacitance electrode and described concentric line together form holding capacitor;
In the step forming drain contact hole, in described passivation layer, form capacitance contact hole, to expose described capacitance electrode;
In the step of formation first auxiliary grid pattern, in described capacitance contact hole, form capacitance contact pattern, to contact described capacitance electrode; And
In the step forming pixel electrode, described pixel electrode covers further and contacts described capacitance contact pattern.
19. methods according to claim 14, wherein said first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.
20. methods according to claim 15, wherein said drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.
21. methods according to claim 18, wherein said capacitance contact pattern, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.
22. methods according to claim 14, wherein said first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.
23. methods according to claim 15, wherein said drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.
24. methods according to claim 18, wherein said capacitance contact pattern, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.
25. methods according to claim 14, wherein said first auxiliary data pattern is integrally formed along described data line.
26. methods according to claim 14, wherein form described first auxiliary grid pattern and described first auxiliary data pattern comprise the first plating layer of being formed and being formed by copper and on described first plating layer, form the second plating layer formed by nickel, and wherein said second plating layer is thinner than described first plating layer.
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| KR1020120067842A KR101976057B1 (en) | 2011-08-19 | 2012-06-25 | Array substrate for display device and method of fabricating the same |
| KR10-2012-0067842 | 2012-06-25 |
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| CN103558722B (en) * | 2013-11-18 | 2017-01-25 | 京东方科技集团股份有限公司 | Array substrate, production method of array substrate and display device |
| CN103680327B (en) * | 2013-12-27 | 2016-03-16 | 京东方科技集团股份有限公司 | Array base palte and display device |
| CN103744242A (en) * | 2013-12-30 | 2014-04-23 | 深圳市华星光电技术有限公司 | Thin film transistor liquid crystal display device and signal line thereof |
| CN104091818B (en) | 2014-06-23 | 2017-09-29 | 上海天马有机发光显示技术有限公司 | A kind of organic electroluminescence display panel, device and its manufacture method |
| KR102238756B1 (en) * | 2014-11-07 | 2021-04-12 | 삼성디스플레이 주식회사 | Display apparatus and manufacturing method thereof |
| KR102523911B1 (en) * | 2016-02-05 | 2023-04-20 | 삼성디스플레이 주식회사 | Display device |
| KR102716398B1 (en) * | 2016-06-17 | 2024-10-11 | 삼성디스플레이 주식회사 | Organic light emitting diode display and method for manufacturing organic light emitting diode display |
| CN107180837A (en) * | 2017-05-17 | 2017-09-19 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN109148381B (en) * | 2018-08-24 | 2020-11-20 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
| CN110673414B (en) * | 2019-09-25 | 2021-09-03 | Tcl华星光电技术有限公司 | Array substrate and preparation method thereof |
| CN111474790A (en) * | 2020-05-14 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| WO2022266925A1 (en) * | 2021-06-24 | 2022-12-29 | 京东方科技集团股份有限公司 | Array substrate, preparation method therefor and display panel |
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