CN102938400A - Inductor structure - Google Patents
Inductor structure Download PDFInfo
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- CN102938400A CN102938400A CN201210477011XA CN201210477011A CN102938400A CN 102938400 A CN102938400 A CN 102938400A CN 201210477011X A CN201210477011X A CN 201210477011XA CN 201210477011 A CN201210477011 A CN 201210477011A CN 102938400 A CN102938400 A CN 102938400A
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- mos transistor
- screen unit
- chip inductor
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- induction structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
The invention discloses an inductor structure which comprises an on-chip inductor and a shielding layer positioned below the on-chip inductor, wherein the shielding layer comprises multiple shielding units; the shielding units are orthogonal to the direction of eddy current generated by the on-chip inductor; the shielding units are composed of MOS (metal oxide semiconductor) transistors or metal wires or polysilicon; at least one among the shielding units is composed of MOS transistors; and source electrodes and drain electrodes of the MOS transistors are grounded. According to the inductor structure, the area below the on-chip inductor is fully utilized to realize the function of a voltage stabilizing transistor.
Description
Technical field
The present invention relates to integrated circuit fields, particularly a kind of inductance for circuit chip structure.
Background technology
Inductance is the important passive device in the radio frequency transceiver front end, and the radio-frequency front-end transceiver module need to be used mainly containing of integrated inductor: induction structure, power amplifier, oscillator, up-conversion mixer etc.Inductance has all been played the part of important effect in these modules.
Take induction structure as example, induction structure is one of important module in the radio frequency transceiver, is mainly used in will being received from the communication system signal amplification of antenna, and the receiver circuit of being convenient to rear class is processed.Be positioned at the at first one-level of whole receiver next-door neighbour antenna just because of noise amplifier, its characteristic directly affects the quality that whole receiver receives signal.For induction structure, the performance of inductance has directly determined gain, noise, impedance matching of induction structure etc.
As a rule, the Q value is one of important indicator of an inductance performance, and the energy storage loss that higher Q value means inductance still less that is to say that the isolation between inductance and the substrate is better.In addition, to the assessment of an inductance except the traditional performance indexs such as inductance value, Q value, also comprise inductance to the impact of other circuit in radio system, if inductance itself is better with the isolation of peripheral circuits, inductance will not affect the work of other circuit at work so.Because the area of integrated silicon inductor is usually larger, how when guaranteeing inductance performance, strengthen the isolation of inductance and substrate, inductance and other circuit, for the module that is applied to radio-frequency front-end, have great significance.
Figure 1 shows that the schematic diagram of induction structure in the prior art, its structure by the passive masking layer of substrate realizes the isolation of inductance and substrate.As a rule, for the integrated circuit (IC) chip of 8 layers of metal level, top-level metallic and time top-level metallic are commonly used to make integrated inductor 1, first layer metal then is used for making the passive separator 2 of sheltering that is positioned at inductance 1 below as shown in Figure 1, passive shelter separator 2 by many independences and itself be 90 the degree rectangular shaped the first layer metal lines consist of.The vortex flow perpendicular direction that these first layer metal lines and integrated inductor 1 produce cuts off the inductance galvanomagnetic effect to the impact of substrate thereby reach the passive separator 2 of sheltering.It should be noted that because the area of inductance usually large (such as 300 microns * 300 microns) is thereunder made the effect that passive masking layer no doubt can play electromagnetic isolation, but but effectively do not utilized the area of inductance below.
Summary of the invention
Main purpose of the present invention is to overcome the defective of prior art, takes full advantage of the area of induction areas below, makes screen have the effect of isolation and voltage-stable transistor concurrently.
For reaching above-mentioned purpose, the invention provides a kind of induction structure, the screen that comprises on-chip inductor and be positioned at described on-chip inductor below, described screen comprises a plurality of screen units, described a plurality of screen unit forms at least one shielding area, the vortex flow direction quadrature that described screen unit and described on-chip inductor produce, described screen unit is comprised of MOS transistor or metal wire or polysilicon, and at least one screen unit is comprised of MOS transistor in described a plurality of screen unit, the source electrode of described MOS transistor and grounded drain.
Further, the grid of described MOS transistor connects power supply, and its source electrode and drain electrode are drawn ground connection by contact hole by metal connecting line; The grid of described MOS transistor is polysilicon gate.
Further, each described screen unit forms by a MOS transistor.
Further, each described screen unit forms by a plurality of MOS transistor of adjacent common-source and drain electrode.
Further, described on-chip inductor is the square spiral circle, the number of described screen unit is 4N, and a described 4N screen unit forms 4 described shielding areas with the Central Symmetry distribution of described on-chip inductor, the N of each described shielding area described screen unit is square and outwards disperses arrangement with a determining deviation with equidirectional, and wherein N is the integer more than or equal to 1.
Further, the channel width of described MOS transistor is identical with source leakage width.
Further, has the interval between the described shielding area.
The invention has the advantages that, with the screen of active transistor as induction structure, can play on-chip inductor and substrate, the buffer action between on-chip inductor and other circuit.Further, screen more can form mos capacitance and be connected in and play pressure stabilization function between the VDD-to-VSS, thereby take full advantage of the larger area of on-chip inductor below, compared to prior art, effectively saved the area that conventional power source voltage voltage stabilizing MOS transistor takies at chip.
Description of drawings
Fig. 1 is the schematic diagram of induction structure in the prior art.
Fig. 2 is the schematic diagram of embodiment of the invention induction structure.
Fig. 3 is the schematic diagram of another embodiment of the present invention induction structure.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Induction structure of the present invention comprises on-chip inductor and is positioned at the screen of on-chip inductor below.Wherein, on-chip inductor is made by top-level metallic and time top-level metallic, and screen comprises a plurality of screen units, and these screen units form at least one shielding area.The passive arrangement mode of first layer metal of sheltering in the separator is identical in the arrangement mode of these screen units and the prior art, that is to say the vortex flow direction quadrature that produces with on-chip inductor, thereby can cut off the inductance galvanomagnetic effect to the impact of substrate.On-chip inductor can be the square spiral circle, the rectangular shape of screen unit.On-chip inductor also can be the round screw thread coil, and screen unit then can be rectilinear form and outwards disperses from the on-chip inductor center.Screen unit can be by MOS transistor, or metal wire, or polysilicon forms, but has at least a screen unit to be comprised of MOS transistor in these screen units.MOS transistor is formed by the manufacturing of standard integrated circuit technology, includes the source region, source electrode, drain and gate.Grid for example is polysilicon gate, and source electrode and drain electrode are drawn by metal connecting line by contact hole.It should be noted that, wherein source electrode and drain electrode are to lead to ground connection by contact hole by metal connecting line, therefore many grounded metal lines with vortex flow direction quadrature have been equivalent to below on-chip inductor, form, thereby can be well at on-chip inductor magnetic field and substrate, and realize between on-chip inductor magnetic field and other circuit cutting off, so that substrate loss reduces, also reduced the signal cross-talk to other circuit devcies simultaneously.Better, the grid of MOS transistor connects supply voltage.Because source electrode and the grounded drain of MOS transistor, the grid of MOS transistor then is equivalent to connect a mos capacitance after connecing supply voltage between supply voltage and ground, thereby MOS transistor can be used as the supply voltage voltage-stabiliser tube simultaneously, plays the pressure stabilization function of supply voltage.
Figure 2 shows that the schematic diagram of the induction structure of first embodiment of the invention.Please refer to Fig. 2, on-chip inductor 1 is the square spiral circle, is made by top-level metallic and time top-level metallic.Each screen unit of screen forms by a MOS transistor, and MOS transistor includes source region 3, source S, drain D and grid 2.Grid 2 for example is polysilicon gate, and source S and drain D lead to ground connection by contact hole 4 by metal connecting line.In the present embodiment, screen unit that is to say that the number of MOS transistor is 12, and at 4 shielding areas of Central Symmetry distribution formation of on-chip inductor 1, each shielding area has 3 MOS transistor.In other embodiments, the quantity of MOS transistor also can be 4, and 8,16 ..., the Central Symmetry of same on-chip inductor 1 distributes and forms 4 shielding areas, and the present invention is not limited to this.The MOS transistor of same shielding area is square and outwards disperses arrangement with equidirectional, and separately between the MOS transistor also has a square spacing.Form " ten " font interval between 4 shielding areas.Because MOS transistor source electrode and grounded drain, its equivalence is the grounded metal line of square, therefore can shield well the magnetic interference of square spiral circle.In addition, the channel width of MOS transistor is all identical with source leakage width, is beneficial to batch production.
Better, the grid 2 of MOS transistor connects supply voltage.Because source S and the drain D ground connection of MOS transistor, the grid 2 of MOS transistor then is equivalent to connect a mos capacitance after connecing supply voltage between supply voltage and ground, thereby MOS transistor can be used as the supply voltage voltage-stabiliser tube simultaneously, plays the pressure stabilization function of supply voltage.It is worthy of note, for conventional power source voltage voltage stabilizing MOS transistor, in order to guarantee that the mos capacitance value is enough large, usually need very large MOS transistor area and meeting independently occupy quite a few area of integrated circuit (IC) chip, cause the area cost of chip to increase.And induction structure of the present invention is to utilize MOS transistor to form the screen of on-chip inductor below, MOS transistor can equivalence be the supply voltage voltage-stabiliser tube, therefore take full advantage of the larger area of below, on-chip inductor zone, need not additionally to increase again chip area the voltage stabilizing MOS transistor is set, the cost of effectively saving.Better, the screen unit in the present embodiment all is separate MOS transistor, thus the mos capacitance value that forms is also enough large.
Figure 3 shows that the induction structure schematic diagram of second embodiment of the invention, the difference of induction structure is among itself and the first embodiment, each screen unit of screen forms by a plurality of MOS transistor, and common-source S and drain D between the adjacent MOS transistor in these MOS transistor.Specifically, screen has 4 screen units, is respectively the first screen unit, secondary shielding unit, the 3rd screen unit and the 4th screen unit.Each screen unit is comprised of the MOS transistor of 3 adjacent common source drain electrodes.These 4 screen units form 4 shielding areas in the Central Symmetry distribution of on-chip inductor 1, and the screen unit of each shielding area is square and outwards disperses arrangement with equidirectional.In other embodiments, the quantity of screen unit also can be 8,16, Central Symmetry distribution with on-chip inductor 1 forms 4 shielding areas equally, and the screen unit of each shielding area is square and outwards disperses arrangement with a determining deviation with equidirectional, and the present invention is not limited to this.Form " ten " font interval between 4 shielding areas.Because in each screen unit, adjacent MOS transistor common-source S and drain D, and source S and drain D ground connection, MOS transistor grid 2 connects supply voltage, no longer has spacing between the MOS transistor, just can improve thus the area utilization of below, on-chip inductor zone largelyr, so that the MOS electric capacity of voltage regulation of MOS transistor equivalence is larger, thereby realize better the voltage regulation result between supply voltage and the ground.In addition, the MOS transistor channel width is all identical with source leakage width, can be beneficial to batch production.
To sum up, induction structure proposed by the invention, with the screen unit of active transistor as the induction structure screen, not only can play on-chip inductor and substrate, buffer action between on-chip inductor and other circuit more can form the mos capacitance that is connected between the VDD-to-VSS to play pressure stabilization function.Therefore, compared to prior art, the present invention takes full advantage of the larger area of on-chip inductor below, has effectively reduced conventional power source voltage voltage stabilizing MOS transistor at the area that chip takies, and provides cost savings.
Although the present invention discloses as above with preferred embodiment; right described many embodiment only give an example for convenience of explanation; be not to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion so that claims are described.
Claims (7)
1. induction structure, the screen that comprises on-chip inductor and be positioned at described on-chip inductor below, described screen comprises a plurality of screen units, described a plurality of screen unit forms at least one shielding area, the vortex flow direction quadrature that described screen unit and described on-chip inductor produce, it is characterized in that
Described screen unit is comprised of MOS transistor or metal wire or polysilicon, and at least one screen unit is comprised of MOS transistor in described a plurality of screen unit, the source electrode of described MOS transistor and grounded drain.
2. induction structure according to claim 1 is characterized in that, the grid of described MOS transistor connects power supply, and its source electrode and drain electrode are drawn ground connection by contact hole by metal connecting line; The grid of described MOS transistor is polysilicon gate.
3. induction structure according to claim 2 is characterized in that, each described screen unit forms by a MOS transistor.
4. induction structure according to claim 2 is characterized in that, each described screen unit forms by a plurality of MOS transistor of adjacent common-source and drain electrode.
5. according to claim 3 or 4 described induction structures, it is characterized in that, described on-chip inductor is the square spiral circle, the number of described screen unit is 4N, and a described 4N screen unit forms 4 described shielding areas with the Central Symmetry distribution of described on-chip inductor, the N of each described shielding area described screen unit is square and outwards disperses arrangement with a determining deviation with equidirectional, and wherein N is the integer more than or equal to 1.
6. according to claim 3 or 4 described induction structures, it is characterized in that, it is identical that width is leaked in the channel width of described MOS transistor and source.
7. induction structure according to claim 5 is characterized in that, has the interval between the described shielding area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210477011.XA CN102938400B (en) | 2012-11-22 | 2012-11-22 | A kind of induction structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210477011.XA CN102938400B (en) | 2012-11-22 | 2012-11-22 | A kind of induction structure |
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| CN102938400A true CN102938400A (en) | 2013-02-20 |
| CN102938400B CN102938400B (en) | 2017-05-31 |
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| CN201210477011.XA Active CN102938400B (en) | 2012-11-22 | 2012-11-22 | A kind of induction structure |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103312294A (en) * | 2013-06-08 | 2013-09-18 | 上海集成电路研发中心有限公司 | Active inductor |
| CN106783798A (en) * | 2016-12-29 | 2017-05-31 | 上海集成电路研发中心有限公司 | A kind of millimeter wave induction structure |
| CN104637917B (en) * | 2013-11-06 | 2018-01-16 | 领特德国有限公司 | Coil arrangement with metal charge |
| TWI617005B (en) * | 2014-11-21 | 2018-03-01 | 威盛電子股份有限公司 | Integrated circuit device |
| CN108962872A (en) * | 2018-07-21 | 2018-12-07 | 安徽矽磊电子科技有限公司 | A kind of the on piece realization structure and laying method of inductance |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010013626A1 (en) * | 2000-02-14 | 2001-08-16 | Hiroki Fujii | Semiconductor device |
| US20020190349A1 (en) * | 2000-04-19 | 2002-12-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing same |
| JP2004031922A (en) * | 2002-05-10 | 2004-01-29 | Mitsubishi Electric Corp | Semiconductor device |
| CN102214640A (en) * | 2010-04-08 | 2011-10-12 | 联发科技股份有限公司 | Semiconductor device |
-
2012
- 2012-11-22 CN CN201210477011.XA patent/CN102938400B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010013626A1 (en) * | 2000-02-14 | 2001-08-16 | Hiroki Fujii | Semiconductor device |
| US20020190349A1 (en) * | 2000-04-19 | 2002-12-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing same |
| JP2004031922A (en) * | 2002-05-10 | 2004-01-29 | Mitsubishi Electric Corp | Semiconductor device |
| CN102214640A (en) * | 2010-04-08 | 2011-10-12 | 联发科技股份有限公司 | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103312294A (en) * | 2013-06-08 | 2013-09-18 | 上海集成电路研发中心有限公司 | Active inductor |
| CN104637917B (en) * | 2013-11-06 | 2018-01-16 | 领特德国有限公司 | Coil arrangement with metal charge |
| TWI617005B (en) * | 2014-11-21 | 2018-03-01 | 威盛電子股份有限公司 | Integrated circuit device |
| CN106783798A (en) * | 2016-12-29 | 2017-05-31 | 上海集成电路研发中心有限公司 | A kind of millimeter wave induction structure |
| CN108962872A (en) * | 2018-07-21 | 2018-12-07 | 安徽矽磊电子科技有限公司 | A kind of the on piece realization structure and laying method of inductance |
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| Publication number | Publication date |
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| CN102938400B (en) | 2017-05-31 |
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