CN102929815B - Controller for DDR3 storer in network processor - Google Patents
Controller for DDR3 storer in network processor Download PDFInfo
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- CN102929815B CN102929815B CN201210484096.4A CN201210484096A CN102929815B CN 102929815 B CN102929815 B CN 102929815B CN 201210484096 A CN201210484096 A CN 201210484096A CN 102929815 B CN102929815 B CN 102929815B
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Abstract
The invention relates to a controller for a DDR3 (Double Data Rate 3) storer in a network processor and belongs to the technical field of controllers. The controller comprises a parallel bus interface module, a cache module and a DDR3 storer interface module, wherein the parallel bus interface module at least comprises two parallel bus interfaces, each bus interface comprises a bus interface unit and an function operation unit; the cache module comprises primary caches in the same number as the parallel bus interfaces and a secondary cache; the cache module is connected with the DDR3 storer through the DDR3 storer interface module; and the DDR3 storer further conceals the refresh time delay on the basis of realizing bank activation and precharge time delay concealing. According to the controller, the memory access efficiency of the DDR3 storer is greatly improved as a whole, and the requirement of the network processor is met. Besides, the controller provided by the invention has the advantages of simple structure, low cost and wide application range.
Description
Technical field
The present invention relates to the controller technology field in controller technology field, particularly storer, specifically refer to a kind of controller of the DDR3 storer be applied in network processing unit.
Background technology
Network processing unit becomes the core devices of next generation network product because fast, the able to programme performance of its speed is good, along with the development of network, the linear speed of network processing unit requires more and more higher; DDR3 is high speed more common at present, jumbo dual rate synchronous memories, and cheap.So real time data is read in a large number frequently to access with routing table and is all undertaken by DDR3, so the bandwidth sum speed of network processing unit to DDR3 interface is proposed higher requirement in network processing unit; And require that DDR3 controller is also upgraded thereupon along with network linear speed promotes.
Traditional DDR3 controller mainly adopts shortening delay strategy, Chinese patent CN102543195A, (Wang Hongbin, a kind of DDR controller and its implementation and chip) disclose and a kind ofly utilize the mode of anticipation to carry out hiding bank to activate and the mechanism (Fig. 1 is shown) of precharge delay, namely by first order is cached and judge in advance this order be whether with next command in the same row, if in the same row, just continue to perform this queue command, otherwise jump to another queue fill order.The limited efficacy that this mode can only improve, the time delay between the read-write being only hidden in different bank or different rows, the efficiency value before raising is η
before=nt
wL/ (nt
wL+ t
rP+ t
rCD), wherein t
wL, t
rP, t
rCDrepresent an access time respectively, precharge time and activationary time, and their value size is similar; The size of n decides continuous dispensing to the data amount check of same bank with a line by programmer, and the efficiency that when distributing more balanced, this algorithm improves is very limited, is difficult to meet the performance boost requirement of DDR3 controller in network processing unit.
Summary of the invention
The object of the invention is to overcome above-mentioned shortcoming of the prior art, there is provided a kind of and adopt parallel reception and processing unit, two-level cache structure and hiding refreshes time delay, thus increase substantially the memory access efficiency of storer, meet the requirement of network processing unit, and structure is simple, with low cost, range of application is comparatively widely used in the controller of the DDR3 storer in network processing unit.
In order to realize above-mentioned object, the controller of the DDR3 storer be applied in network processing unit of the present invention has following formation:
The controller of this DDR3 storer be applied in network processing unit comprises parallel bus interface module, cache module and DDR3 memory interface module.Described parallel bus interface module comprises the bus interface that at least two-way is parallel, the feature operation unit that each road bus interface includes Bus Interface Unit and is connected with described Bus Interface Unit, described Bus Interface Unit deposits visit order in order to obtain DDR3 storer from bus, described feature operation unit visits order in order to perform described depositing, described each feature operation unit connects described cache module respectively, and described cache module connects DDR3 storer by described DDR3 memory interface module.
This is applied in the controller of the DDR3 storer in network processing unit, and described feature operation unit comprises reading and writing data subelement, atomic operation subelement and queue operation subelement.
This is applied in the controller of the DDR3 storer in network processing unit, and described parallel bus interface module comprises the parallel bus interface in four tunnels.
This is applied in the controller of the DDR3 storer in network processing unit, described cache module comprises the level cache identical with described parallel bus interface quantity and a L2 cache, described each level cache is connected to the interface unit of a road bus interface respectively, and all connect described L2 cache, described level cache in order to store recently write and the packet be not read out and the most frequently used routing table; DDR3 memory interface module described in described L2 cache connects, in order to store conventional routing table.
This is applied in the controller of the DDR3 storer in network processing unit, and described DDR3 memory interface module comprises: six FIFO, two counters, two anticipation logical blocks, a status command converting unit and initialization logic.
In six described FIFO, a FIFO and the 2nd FIFO is the first group command FIFO, the 3rd FIFO and the 4th FIFO is the second group command FIFO, the first described group command FIFO and the second group command FIFO is for depositing described memory access order, the read-write requests demanded storage of even number bank is in a described FIFO and the 3rd FIFO, the read-write requests demanded storage of odd number bank is in the 2nd described FIFO and the 4th FIFO, 5th FIFO is read data FIFO, and the 6th FIFO is for writing data FIFO;
In two counters, the first counter is connected to a FIFO and the 2nd FIFO of the first described group command FIFO, second counter is connected to the 3rd FIFO and the 4th FIFO of the second described group command FIFO, this group command FIFO in order to connect at a counter counts when carrying out read-write process, and when reaching the refresh cycle, jump to another group command FIFO and carry out read-write process, with this hiding refreshes clock period, reach the object of hiding refreshes time delay;
In two anticipation logical blocks, the first anticipation logical block connects a FIFO and the 2nd FIFO of the first described group command FIFO respectively, second anticipation logical block connects the 3rd FIFO and the 4th FIFO of the second described group command FIFO respectively, and described anticipation logical block is in order to hiding activation and Precharge clock cycle;
The first group command FIFO described in status command converting unit connects respectively by the first described anticipation logical block, the second group command FIFO described in being connected by the second described anticipation logical block, and connect described in read data FIFO and write data FIFO, in order to according to control described in each FIFO;
Initialization logic is connected to described status command converting unit, in order to realize the initialization of described status command converting unit.
This is applied in the controller of the DDR3 storer in network processing unit, the width of a described FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 27, and the degree of depth of a FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 32; The 5th described FIFO and the width of the 6th FIFO are 128, and the degree of depth of the 5th FIFO and the 6th FIFO is 128.
Have employed the controller being applied to the DDR3 storer in network processing unit of this invention, it comprises parallel bus interface module, cache module and DDR3 memory interface module.Parallel bus interface module comprises the bus interface that at least two-way is parallel, the feature operation unit that each road bus interface includes Bus Interface Unit and is connected with described Bus Interface Unit, each feature operation unit Connection Cache module respectively; Cache module comprises the level cache identical with described parallel bus interface quantity and a L2 cache, and each level cache is connected to the interface unit of a road bus interface respectively, and all connects described L2 cache; Described cache module connects DDR3 storer by described DDR3 memory interface module, and DDR3 memory interface module, realizing hiding on the basis of bank activation and precharge delay, conceals refreshing time delay further.Thus increased substantially the memory access efficiency of DDR3 storer on the whole, can meet the requirement of network processing unit, and the structure of the controller of the DDR3 storer be applied in network processing unit of the present invention is simple, with low cost, range of application is comparatively extensive.
Accompanying drawing explanation
Fig. 1 is DDR memory controller structural representation of the prior art.
Fig. 2 is the structural representation of the controller of the DDR3 storer be applied in network processing unit of the present invention.
Fig. 3 is the bus interface of controller and the structural representation of feature operation parts of the DDR3 storer be applied in network processing unit of the present invention.
Fig. 4 is the structural representation of the DDR3 interface unit of the controller of the DDR3 storer be applied in network processing unit of the present invention.
Embodiment
In order to more clearly understand technology contents of the present invention, describe in detail especially exemplified by following examples.
Refer to shown in Fig. 2, be applied to the structural representation of the controller of the DDR3 storer in network processing unit for the present invention.
In one embodiment, the controller of this DDR3 storer be applied in network processing unit comprises parallel bus interface module, cache module and DDR3 memory interface module.
Described parallel bus interface module comprises the parallel bus interface in four tunnels, the feature operation unit that each road bus interface includes Bus Interface Unit and is connected with described Bus Interface Unit.Described Bus Interface Unit deposits visit order in order to obtain DDR3 storer from bus.Described feature operation unit comprises reading and writing data subelement, atomic operation subelement and queue operation subelement, and each subelement visits order in order to perform to deposit accordingly.Described each feature operation unit connects described cache module respectively, and described cache module connects DDR3 storer by described DDR3 memory interface module.
In more preferably embodiment, described cache module comprises the level cache identical with described parallel bus interface quantity and a L2 cache, described each level cache is connected to the interface unit of a road bus interface respectively, and all connect described L2 cache, described level cache in order to store recently write and the packet be not read out and the most frequently used routing table; DDR3 memory interface module described in described L2 cache connects, in order to store conventional routing table.
In preferred embodiment, described DDR3 memory interface module comprises: six FIFO, two counters, two anticipation logical blocks, a status command converting unit and initialization logic.
In six described FIFO, a FIFO and the 2nd FIFO is the first group command FIFO, the 3rd FIFO and the 4th FIFO is the second group command FIFO, the first described group command FIFO and the second group command FIFO is for depositing described memory access order, the read-write requests demanded storage of even number bank is in a described FIFO and the 3rd FIFO, the read-write requests demanded storage of odd number bank is in the 2nd described FIFO and the 4th FIFO, 5th FIFO is read data FIFO, and the 6th FIFO is for writing data FIFO; The width of a described FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 27, and the degree of depth of a FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 32; The 5th described FIFO and the width of the 6th FIFO are 128, and the degree of depth of the 5th FIFO and the 6th FIFO is 128;
In two counters, the first counter is connected to a FIFO and the 2nd FIFO of the first described group command FIFO, second counter is connected to the 3rd FIFO and the 4th FIFO of the second described group command FIFO, this group command FIFO in order to connect at a counter counts when carrying out read-write process, and when reaching the refresh cycle, jump to another group command FIFO and carry out read-write process, conceal refreshing time delay;
In two anticipation logical blocks, the first anticipation logical block connects a FIFO and the 2nd FIFO of the first described group command FIFO respectively, second anticipation logical block connects the 3rd FIFO and the 4th FIFO of the second described group command FIFO respectively, and described anticipation logical block is in order to hiding activation and Precharge clock cycle;
The first group command FIFO described in described status command converting unit connects respectively by the first described anticipation logical block, the second group command FIFO described in being connected by the second described anticipation logical block, and connect described in read data FIFO and write data FIFO, in order to according to control described in each FIFO;
Described initialization logic is connected to described status command converting unit, in order to realize the initialization of described status command converting unit.
In actual applications, the DDR3 controller of the technical scheme of controller of the present invention mainly a kind of multistage optimization, it comprises following characteristics:
A. comprise multiple Bus Interface Unit, the parallel order received from bus, improves controller data handling capacity, and can need to improve interface concurrent degree according to network linear speed; Feature operation parts are connect, to process memory access order in time after each interface unit.
B. two-stage cache unit, shortens Memory accessing delay.
C. on the basis of hiding activation and precharge delay, design a kind of can the structure of hiding refreshes time delay further, the utilization factor of DDR3 interface is improved further.
Specifically, the structure of the controller of the DDR3 storer be applied in network processing unit of the present invention comprises following characteristics:
1, the structure of bus interface and feature operation parts as shown in Figure 3.Adopt four bus receiving elements, be connected with four internal buss respectively, can walk abreast to receive and come from the command request of bus in four roads, and order is assigned on different functional parts in time does further process.It comprises bus line command translation interface and feature operation parts, and feature operation parts are divided into according to the dissimilar of order again: date read-write cell, atomic operation unit, queue operation unit.Bus Interface Unit is independent receives order from bus, and order is transformed on the corresponding operating unit of functional part, operating unit is fill order independently, exchanges data is carried out with one-level cache again when need carry out exchanges data, if carry out exchanges data with secondary cache again when one-level cache is miss, if carry out exchanges data with DDR3 again when secondary cache is also miss.When linear speed improves, only need the bus interface, feature operation parts and the one-level cache unit that increase in this structure.
2, the cache unit of stratification adopts two-stage cache unit to carry out data buffer storage.Wherein first order cache mainly stores the packet of just write, and a part is the normal routing table used recently, and the data packet discarding that will have read; Second level cache mainly stores the conventional routing table of a larger part.Reading and writing data speed in DDR3 can be improved by cooperatively interacting of this two-stage cache.First order cache size in two-stage cache structure is 128K, second level cache size is 1M, wherein one-level cache is multiport unit, it can walk abreast the data provided required for above-mentioned several functional part, and can conduct the locking operations to data, in process operation data, namely forbid that other functional parts operate data.Second level cache also can provide multichannel interface, and convenient and DDR3 SDRAM carries out exchanges data.
3, for DDR3 interface unit, primary structure as shown in Figure 4, comprises six FIFO, wherein front four for depositing memory access order, the 5th is read data FIFO, and the 6th is write data FIFO; Two counters; Two anticipation logical blocks; A status command converting unit; An initialization logic.In the process realized, first different FIFO is put in the memory access order of different bank, wherein 0,2bank order puts into first FIFO, and 1,3bank order puts into second FIFO, the rest may be inferred.And first counter counts first and second FIFO simultaneously, once count down to the refresh cycle just jump to third and fourth FIFO carry out read-write process; And the read-write requests of odd even bank separately stores, and activation and Precharge clock cycle can be hidden by anticipation logic.
The size of six FIFO is respectively 32 degree of depth that FIFO1 ~ 4 are 27 bit wides, and FIFO5 ~ 6 are 128 bit wide, 128 FIFO degree of depth, two counters and two anticipation logics, and initialization logic and a status command conversion logic are formed.In the process realized, the FIFO of four described order FIFO(numberings 1,2,3,4) be divided into two groups, first group for store bank0,1,2, the read write command of 3, second group for store bank4,5,6, the read write command of 7, the order in first group is first performed during data manipulation, and carry out refresh operation to second group simultaneously, when also counting down to refresh requests for first group, just fill order unit is switched to second group of execution, come hiding first group with this and refresh time delay, can hiding refreshes time delay when alternately performing.In every Management Information Base FIFO, the read-write requests of odd even bank separately stores, and can hide activation and Precharge clock cycle by anticipation logic.
Adopt above-mentioned practical application structure that the present invention can be made to have following beneficial effect:
1, by adopting parallel bus receiving element and functional part unit to receive order from bus in time in the DDR3 controller of this multistage optimization in the first order, increase the handling capacity of DDR3 interface, make the operational orders such as the read-write of DDR3 can not produce congestion phenomenon, and increasing of functional part can process read write command timely.And can according to the needs of network processes speed, dynamically increase interface and feature operation parts are to adapt to the demand of linear speed lifting.
2, a lot of read amendment owing to can produce in network processing unit and the atomic operation such as to write, adopt the two-stage cache structure in the second level of the present invention to be placed in this DDR3 controller, effectively reduce these and operate the time delay brought.According to the speed-up ratio formula of cache
wherein S
pfor speed-up ratio, H is cache hit probability, T
cfor the access time of cache, about 7 clock period; T
mthe access time of DDR3, about 140 clock period.When hit rate is 90%, speed-up ratio is 6.89.The averaging time of now DDR3 access is about 20 clock period, effectively shortens access time delay.And adding of second level cache can the locality of development data further, store the data of more write recently, to improve cache hit probability.
3, compared to Chinese patent CN102543195A described in the prior art, (Wang Hongbin, a kind of DDR controller and its implementation and chip), activation and precharge delay is not only concealed by the third level of this controller, but also conceal and refresh time delay more and more frequently now, the utilization factor of DDR3 interface is further enhanced.
Have employed the controller being applied to the DDR3 storer in network processing unit of this invention, it comprises parallel bus interface module, cache module and DDR3 memory interface module.Parallel bus interface module comprises the bus interface that at least two-way is parallel, the feature operation unit that each road bus interface includes Bus Interface Unit and is connected with described Bus Interface Unit, each feature operation unit Connection Cache module respectively; Cache module comprises the level cache identical with described parallel bus interface quantity and a L2 cache, and each level cache is connected to the interface unit of a road bus interface respectively, and all connects described L2 cache; Described cache module connects DDR3 storer by described DDR3 memory interface module, and DDR3 memory interface module, realizing hiding on the basis of bank activation and precharge delay, conceals refreshing time delay further.Thus increased substantially the memory access efficiency of DDR3 storer on the whole, can meet the requirement of network processing unit, and the structure of the controller of the DDR3 storer be applied in network processing unit of the present invention is simple, with low cost, range of application is comparatively extensive.
In this description, the present invention is described with reference to its specific embodiment.But, still can make various amendment and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (5)
1. one kind is applied to the controller of the DDR3 storer in network processing unit, it is characterized in that, described controller comprises parallel bus interface module, cache module and DDR3 memory interface module, described parallel bus interface module comprises the bus interface that at least two-way is parallel, the feature operation unit that each road bus interface includes Bus Interface Unit and is connected with described Bus Interface Unit, described Bus Interface Unit is in order to obtain the order relevant to the memory access of DDR3 storer from bus, described feature operation unit is in order to perform the relevant order of described memory access, described each feature operation unit connects described cache module respectively, described cache module connects DDR3 storer by described DDR3 memory interface module, described cache module comprises the level cache identical with described parallel bus interface quantity and a L2 cache, each described level cache is connected to the interface unit of a road bus interface respectively, and all connect described L2 cache, described level cache in order to store recently write and the packet be not read out and the most frequently used routing table, DDR3 memory interface module described in described L2 cache connects, in order to store conventional routing table.
2. the controller of the DDR3 storer be applied in network processing unit according to claim 1, is characterized in that, described feature operation unit comprises reading and writing data subelement, atomic operation subelement and queue operation subelement.
3. the controller of the DDR3 storer be applied in network processing unit according to claim 1, is characterized in that, described parallel bus interface module comprises the parallel bus interface in four tunnels.
4. the controller of the DDR3 storer be applied in network processing unit according to claim 1, is characterized in that, described DDR3 memory interface module comprises:
Six FIFO, wherein a FIFO and the 2nd FIFO is the first group command FIFO, the 3rd FIFO and the 4th FIFO is the second group command FIFO, the first described group command FIFO and the second group command FIFO is for depositing described memory access order, the read-write requests demanded storage of even number bank is in a described FIFO and the 3rd FIFO, the read-write requests demanded storage of odd number bank is in the 2nd described FIFO and the 4th FIFO, 5th FIFO is read data FIFO, and the 6th FIFO is for writing data FIFO;
Two counters, first counter is connected to a FIFO and the 2nd FIFO of the first described group command FIFO, second counter is connected to the 3rd FIFO and the 4th FIFO of the second described group command FIFO, this group command FIFO in order to connect at a counter counts when carrying out read-write process, and when will reach the refresh cycle, jump to another group command FIFO and carry out read-write process, with this hiding refreshes clock period;
Two anticipation logical blocks, first anticipation logical block connects a FIFO and the 2nd FIFO of the first described group command FIFO respectively, second anticipation logical block connects the 3rd FIFO and the 4th FIFO of the second described group command FIFO respectively, and described anticipation logical block is in order to hiding activation and Precharge clock cycle;
A status command converting unit, the first group command FIFO described in connecting respectively by the first described anticipation logical block, the second group command FIFO described in being connected by the second described anticipation logical block, and connect described in read data FIFO and write data FIFO, in order to according to control described in each FIFO;
An initialization logic, is connected to described status command converting unit, in order to realize the initialization of described status command converting unit.
5. the controller of the DDR3 storer be applied in network processing unit according to claim 4, it is characterized in that, the width of a described FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 27, and the degree of depth of a FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 32; The 5th described FIFO and the width of the 6th FIFO are 128, and the degree of depth of the 5th FIFO and the 6th FIFO is 128.
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| CN102543159A (en) * | 2010-12-29 | 2012-07-04 | 炬才微电子（深圳）有限公司 | Double data rate (DDR) controller and realization method thereof, and chip |
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| CN102543159A (en) * | 2010-12-29 | 2012-07-04 | 炬才微电子（深圳）有限公司 | Double data rate (DDR) controller and realization method thereof, and chip |
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| M. Ohmacht et al.Blue Gene/L compute chip: memory and Ethernet subsystem.《IBM Journal of research and development》.2005,第49卷第225-264页. * |
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