CN102929815A - Controller for DDR3 storer in network processor - Google Patents
Controller for DDR3 storer in network processor Download PDFInfo
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- CN102929815A CN102929815A CN2012104840964A CN201210484096A CN102929815A CN 102929815 A CN102929815 A CN 102929815A CN 2012104840964 A CN2012104840964 A CN 2012104840964A CN 201210484096 A CN201210484096 A CN 201210484096A CN 102929815 A CN102929815 A CN 102929815A
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Abstract
The invention relates to a controller for a DDR3 (Double Data Rate 3) storer in a network processor and belongs to the technical field of controllers. The controller comprises a parallel bus interface module, a cache module and a DDR3 storer interface module, wherein the parallel bus interface module at least comprises two parallel bus interfaces, each bus interface comprises a bus interface unit and an function operation unit; the cache module comprises primary caches in the same number as the parallel bus interfaces and a secondary cache; the cache module is connected with the DDR3 storer through the DDR3 storer interface module; and the DDR3 storer further conceals the refresh time delay on the basis of realizing bank activation and precharge time delay concealing. According to the controller, the memory access efficiency of the DDR3 storer is greatly improved as a whole, and the requirement of the network processor is met. Besides, the controller provided by the invention has the advantages of simple structure, low cost and wide application range.
Description
Technical field
The present invention relates to the controller technology field in controller technology field, particularly storer, specifically refer to a kind of controller that is applied to the DDR3 storer in the network processing unit.
Background technology
Network processing unit is owing to the good core devices that becomes the next generation network product of fast, the able to programme performance of its speed, and along with the development of network, the linear speed of network processing unit requires more and more higher; DDR3 is present more common high speed, jumbo dual rate synchronous memories, and cheap.So real time data reads in a large number with routing table frequent access and is all undertaken by DDR3 in the network processing unit, so network processing unit has all proposed higher requirement to bandwidth and the speed of DDR3 interface; And require along with the network linear speed promotes, the DDR3 controller is thereupon upgrading also.
Traditional DDR3 controller mainly adopts the shortening delay strategy, Chinese patent CN102543195A, (Wang Hongbin, a kind of DDR controller and its implementation and chip) disclose a kind of mode of utilizing anticipation and hidden that bank activates and the mechanism (shown in Figure 1) of precharge delay, namely by first order is cached and judge in advance this order whether with next command in delegation, if in delegation, just continue to carry out this queue command, otherwise jump to another formation fill order.The efficient that this mode can only improve is limited, only is hidden in the time-delay between the read-write of different bank or different rows, and the efficiency value before improving is η
Before=nt
WL/ (nt
WL+ t
RP+ t
RCD), t wherein
WL, t
RP, t
RCDRepresent respectively access time one time, precharge time and activationary time, and their value size is similar; The size of n is to decide continuous dispensing to the data amount check of same bank with delegation by the programmer, and the efficient that this algorithm improves when distributing equilibrium is very limited, is difficult to satisfy the performance boost requirement of DDR3 controller in the network processing unit.
Summary of the invention
The objective of the invention is to have overcome above-mentioned shortcoming of the prior art, a kind of employing parallel receive and processing unit, two-level cache structure and hiding refreshes time-delay are provided, thereby increase substantially the memory access efficient of storer, satisfy the requirement of network processing unit, and simple in structure, with low cost, range of application comparatively is widely used in the controller of the DDR3 storer in the network processing unit.
In order to realize above-mentioned purpose, the controling appliance that is applied to the DDR3 storer in the network processing unit of the present invention has following formation:
This controller that is applied to the DDR3 storer in the network processing unit comprises parallel bus interface module, cache module and DDR3 memory interface module.Described parallel bus interface module comprises at least parallel bus interface of two-way, each road bus interface includes Bus Interface Unit and the feature operation unit that links to each other with described Bus Interface Unit, described Bus Interface Unit is deposited the visit order in order to obtain the DDR3 storer from bus, order is visited in order to carry out described depositing in described feature operation unit, described each feature operation unit connects described cache module respectively, and described cache module connects the DDR3 storer by described DDR3 memory interface module.
This is applied in the controller of the DDR3 storer in the network processing unit, and described feature operation unit comprises reading and writing data subelement, atomic operation subelement and queue operation subelement.
This is applied in the controller of the DDR3 storer in the network processing unit, and described parallel bus interface module comprises four tunnel parallel bus interface.
This is applied in the controller of the DDR3 storer in the network processing unit, described cache module comprises level cache and a L2 cache identical with described parallel bus interface quantity, described each level cache is connected in the interface unit of one tunnel bus interface respectively, and all connecting described L2 cache, described level cache is in order to storage packet that write recently and that be not read out and the most frequently used routing table; Described L2 cache connects described DDR3 memory interface module, in order to store routing table commonly used.
This is applied in the controller of the DDR3 storer in the network processing unit, and described DDR3 memory interface module comprises: six FIFO, two counters, two anticipation logical blocks, a status command converting unit and an initialization logic unit.
A FIFO and the 2nd FIFO are that the first group command FIFO, the 3rd FIFO and the 4th FIFO are the second group command FIFO among described six FIFO, described the first group command FIFO and the second group command FIFO are used for depositing described memory access order, the read-write requests demanded storage of even number bank is in a described FIFO and the 3rd FIFO, the read-write requests demanded storage of odd number bank is in described the 2nd FIFO and the 4th FIFO, the 5th FIFO is read data FIFO, and the 6th FIFO is for writing data FIFO;
The first counter is connected to a FIFO and the 2nd FIFO of described the first group command FIFO in two counters, the second counter is connected to the 3rd FIFO and the 4th FIFO of described the second group command FIFO, count when reading and writing processing in order to this group command FIFO that connects at a counter, and when reaching the refresh cycle, jump to another group command FIFO and read and write processing, with this hiding refreshes clock period, reach the purpose of hiding refreshes time delay;
The first anticipation logical block connects respectively a FIFO and the 2nd FIFO of described the first group command FIFO in two anticipation logical blocks, the second anticipation logical block connects respectively the 3rd FIFO and the 4th FIFO of described the second group command FIFO, and described anticipation logical block activates and the precharge clock period in order to hide;
The status command converting unit connects described the first group command FIFO by described the first anticipation logical block respectively, connect described the second group command FIFO by described the second anticipation logical block, and connect described read data FIFO and write data FIFO, in order to according to described each FIFO of control;
The initialization logic unit is connected in described status command converting unit, in order to realize the initialization of described status command converting unit.
This is applied in the controller of the DDR3 storer in the network processing unit, the width of a described FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 27, and the degree of depth of a FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 32; The width of described the 5th FIFO and the 6th FIFO is 128, and the degree of depth of the 5th FIFO and the 6th FIFO is 128.
Adopted the controller that is applied to the DDR3 storer in the network processing unit of this invention, it comprises parallel bus interface module, cache module and DDR3 memory interface module.The parallel bus interface module comprises at least parallel bus interface of two-way, and each road bus interface includes Bus Interface Unit and the feature operation unit that links to each other with described Bus Interface Unit, and each feature operation unit is the Connection Cache module respectively; Cache module comprises level cache and a L2 cache identical with described parallel bus interface quantity, and each level cache is connected in the interface unit of one tunnel bus interface respectively, and all connects described L2 cache; Described cache module connects the DDR3 storer by described DDR3 memory interface module, and the DDR3 memory interface module has further been hidden and refreshed time-delay on the basis of realizing hiding bank activation and precharge delay.Thereby increased substantially on the whole the memory access efficient of DDR3 storer, can satisfy the requirement of network processing unit, and the controller that is applied to the DDR3 storer in the network processing unit of the present invention is simple in structure, with low cost, range of application is comparatively extensive.
Description of drawings
Fig. 1 is DDR memory controller structural representation of the prior art.
Fig. 2 is the structural representation that is applied to the controller of the DDR3 storer in the network processing unit of the present invention.
Fig. 3 is the bus interface of the controller that is applied to the DDR3 storer in the network processing unit of the present invention and the structural representation of feature operation parts.
Fig. 4 is the structural representation of the DDR3 interface unit of the controller that is applied to the DDR3 storer in the network processing unit of the present invention.
Embodiment
In order more clearly to understand technology contents of the present invention, describe in detail especially exemplified by following examples.
See also shown in Figure 2ly, be applied to the structural representation of the controller of the DDR3 storer in the network processing unit for the present invention.
In one embodiment, this controller that is applied to the DDR3 storer in the network processing unit comprises parallel bus interface module, cache module and DDR3 memory interface module.
Described parallel bus interface module comprises four tunnel parallel bus interface, and each road bus interface includes Bus Interface Unit and the feature operation unit that links to each other with described Bus Interface Unit.Described Bus Interface Unit is deposited the visit order in order to obtain the DDR3 storer from bus.Described feature operation unit comprises reading and writing data subelement, atomic operation subelement and queue operation subelement, and each subelement is visited order in order to carry out to deposit accordingly.Described each feature operation unit connects described cache module respectively, and described cache module connects the DDR3 storer by described DDR3 memory interface module.
In embodiment more preferably, described cache module comprises level cache and a L2 cache identical with described parallel bus interface quantity, described each level cache is connected in the interface unit of one tunnel bus interface respectively, and all connecting described L2 cache, described level cache is in order to storage packet that write recently and that be not read out and the most frequently used routing table; Described L2 cache connects described DDR3 memory interface module, in order to store routing table commonly used.
In preferred embodiment, described DDR3 memory interface module comprises: six FIFO, two counters, two anticipation logical blocks, a status command converting unit and an initialization logic unit.
A FIFO and the 2nd FIFO are that the first group command FIFO, the 3rd FIFO and the 4th FIFO are the second group command FIFO among described six FIFO, described the first group command FIFO and the second group command FIFO are used for depositing described memory access order, the read-write requests demanded storage of even number bank is in a described FIFO and the 3rd FIFO, the read-write requests demanded storage of odd number bank is in described the 2nd FIFO and the 4th FIFO, the 5th FIFO is read data FIFO, and the 6th FIFO is for writing data FIFO; The width of a described FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 27, and the degree of depth of a FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 32; The width of described the 5th FIFO and the 6th FIFO is 128, and the degree of depth of the 5th FIFO and the 6th FIFO is 128;
The first counter is connected to a FIFO and the 2nd FIFO of described the first group command FIFO in two counters, the second counter is connected to the 3rd FIFO and the 4th FIFO of described the second group command FIFO, count when reading and writing processing in order to this group command FIFO that connects at a counter, and when reaching the refresh cycle, jump to another group command FIFO and read and write processing, hidden and refreshed time delay;
The first anticipation logical block connects respectively a FIFO and the 2nd FIFO of described the first group command FIFO in two anticipation logical blocks, the second anticipation logical block connects respectively the 3rd FIFO and the 4th FIFO of described the second group command FIFO, and described anticipation logical block activates and the precharge clock period in order to hide;
Described status command converting unit connects described the first group command FIFO by described the first anticipation logical block respectively, connect described the second group command FIFO by described the second anticipation logical block, and connect described read data FIFO and write data FIFO, in order to according to described each FIFO of control;
Described initialization logic unit is connected in described status command converting unit, in order to realize the initialization of described status command converting unit.
In actual applications, the technical scheme of controller of the present invention mainly is a kind of DDR3 controller of multistage optimization, and it comprises following characteristics:
A. comprise a plurality of Bus Interface Units, parallel receive improves the controller data handling capacity from the order of bus, and can improve the interface concurrent degree according to network linear speed needs; Connect feature operation parts behind each interface unit, with timely processing memory access order.
B. two-stage cache unit shortens Memory accessing delay.
C. on the basis that hides activation and precharge delay, design a kind of structure of further hiding refreshes time-delay, the utilization factor of DDR3 interface is further improved.
Particularly, the structure that is applied to the controller of the DDR3 storer in the network processing unit of the present invention comprises following characteristics:
1, the structure of bus interface and feature operation parts as shown in Figure 3.Adopt four bus receiving elements, link to each other with four internal buss respectively, can come from the command request of bus by four road parallel receives, and will order in time to be assigned to and do further processing on the different functional parts.It comprises bus line command translation interface and feature operation parts, and the feature operation parts are again according to dissimilar being divided into of ordering: date read-write cell, atomic operation unit, queue operation unit.Bus Interface Unit is independent to receive order from bus, and order is transformed on the corresponding operating unit of functional part, operating unit is fill order independently, carry out exchanges data with one-level cache again in the time that exchanges data need being carried out, if carry out exchanges data with secondary cache again when one-level cache is miss, if carry out exchanges data with DDR3 again when secondary cache is also miss.When linear speed improved, the bus interface, feature operation parts and the one-level cache unit that only need to increase in this structure got final product.
2, the cache unit of stratification is to adopt two-stage cache unit to carry out data buffer storage.Wherein first order cache mainly stores the packet that has just write, and a part is the normal routing table of using recently, and the data packet discarding that will read; Second level cache stores larger part routing table commonly used.Can improve reading and writing data speed among the DDR3 by cooperatively interacting of this two-stage cache.First order cache size in the two-stage cache structure is 128K, cache size in the second level is 1M, wherein one-level cache is the multiport unit, it can walk abreast provides above-mentioned several functional part needed data, and can conduct the locking operations to data, forbid in process operation data that namely other functional parts operate data.Second level cache also can provide the multichannel interface, and convenient and DDR3 SDRAM carries out exchanges data.
3, for the DDR3 interface unit, primary structure comprises six FIFO as shown in Figure 4, and wherein front four are used for depositing the memory access order, and the 5th is read data FIFO, and the 6th is to write data FIFO; Two counters; Two anticipation logical blocks; A status command converting unit; An initialization logic unit.In the process that realizes, at first different FIFO is put in the memory access order of different bank, wherein 0, the 2bank order puts into first FIFO, and 1, the 3bank order puts into second FIFO, the rest may be inferred.And first counter is counted simultaneously to first and second FIFO, reads and writes processing in case just jump to third and fourth FIFO when counting down to the refresh cycle; And the read-write requests of odd even bank is storage separately, and can hide activation and precharge clock period by the anticipation logic.
The size of six FIFO is respectively 32 degree of depth that FIFO1～4 are 27 bit wides, and FIFO5～6 are 128 FIFO degree of depth of 128 bit wides, two counters and two anticipation logics, and initialization logic and a status command conversion logic consist of.In the process that realizes, the FIFO of described four order FIFO(numberings 1,2,3,4) is divided into two groups, first group is used for storage bank0,1,2,3 read write command, second group is used for storage bank4,5,6,7 read write command, carry out first the order in first group during data manipulation, and carry out refresh operation to second group simultaneously, when also counting down to refresh requests for first group, just the fill order unit is switched to second group of execution, hide first group with this and refresh time-delay, can the hiding refreshes time-delay when alternately carrying out.The read-write requests of odd even bank is separately stored among every Management Information Base FIFO, and can hide activation and precharge clock period by the anticipation logic.
Adopt above-mentioned practical application structure can make the present invention have following beneficial effect:
1, by in the DDR3 of this multistage optimization controller, adopting the in time reception of parallel bus receiving element and functional part unit from the order of bus in the first order, increased the handling capacity of DDR3 interface, make the operational orders such as read-write of DDR3 can not produce congestion phenomenon, and increasing of functional part can be processed read write command timely.And can according to the needs of network processes speed, dynamically increase the demand that interface and feature operation parts promote to adapt to linear speed.
2, owing to can produce a lot of reading in the network processing unit and revise and the atomic operation such as write, adopt the two-stage cache structure in the second level of the present invention to be placed in this DDR3 controller, effectively reduce the time-delay that these operations bring.Speed-up ratio formula according to cache
S wherein
pBe speed-up ratio, H is the cache hit rate, T
cBe the access time of cache, about 7 clock period; T
mThe access time of DDR3, about 140 clock period.When hit rate was 90%, speed-up ratio was 6.89.Be about 20 clock period the averaging time of DDR3 access this moment, effectively shortened the access time-delay.And the further locality of development data of the adding of second level cache, the data that storage more writes recently are to improve the cache hit rate.
3, compared to Chinese patent CN102543195A described in the prior art, (Wang Hongbin, a kind of DDR controller and its implementation and chip), the third level by this controller has not only been hidden activation and precharge delay, refresh more and more frequently now time-delay but also hidden, so that the utilization factor of DDR3 interface is further enhanced.
Adopted the controller that is applied to the DDR3 storer in the network processing unit of this invention, it comprises parallel bus interface module, cache module and DDR3 memory interface module.The parallel bus interface module comprises at least parallel bus interface of two-way, and each road bus interface includes Bus Interface Unit and the feature operation unit that links to each other with described Bus Interface Unit, and each feature operation unit is the Connection Cache module respectively; Cache module comprises level cache and a L2 cache identical with described parallel bus interface quantity, and each level cache is connected in the interface unit of one tunnel bus interface respectively, and all connects described L2 cache; Described cache module connects the DDR3 storer by described DDR3 memory interface module, and the DDR3 memory interface module has further been hidden and refreshed time-delay on the basis of realizing hiding bank activation and precharge delay.Thereby increased substantially on the whole the memory access efficient of DDR3 storer, can satisfy the requirement of network processing unit, and the controller that is applied to the DDR3 storer in the network processing unit of the present invention is simple in structure, with low cost, range of application is comparatively extensive.
In this instructions, the present invention is described with reference to its specific embodiment.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (6)
1. controller that is applied to the DDR3 storer in the network processing unit, it is characterized in that, described controller comprises the parallel bus interface module, cache module and DDR3 memory interface module, described parallel bus interface module comprises at least parallel bus interface of two-way, each road bus interface includes Bus Interface Unit and the feature operation unit that links to each other with described Bus Interface Unit, described Bus Interface Unit is in order to obtain the order relevant with the memory access of DDR3 storer from bus, described feature operation unit is in order to carry out the relevant order of described memory access, described each feature operation unit connects described cache module respectively, and described cache module connects the DDR3 storer by described DDR3 memory interface module.
2. the controller that is applied to the DDR3 storer in the network processing unit according to claim 1 is characterized in that, described feature operation unit comprises reading and writing data subelement, atomic operation subelement and queue operation subelement.
3. the controller that is applied to the DDR3 storer in the network processing unit according to claim 1 is characterized in that, described parallel bus interface module comprises four tunnel parallel bus interface.
4. each described controller that is applied to the DDR3 storer in the network processing unit in 3 according to claim 1, it is characterized in that, described cache module comprises level cache and a L2 cache identical with described parallel bus interface quantity, described each level cache is connected in the interface unit of one tunnel bus interface respectively, and all connecting described L2 cache, described level cache is in order to storage packet that write recently and that be not read out and the most frequently used routing table; Described L2 cache connects described DDR3 memory interface module, in order to store routing table commonly used.
5. the controller that is applied to the DDR3 storer in the network processing unit according to claim 4 is characterized in that, described DDR3 memory interface module comprises:
Six FIFO, wherein a FIFO and the 2nd FIFO are that the first group command FIFO, the 3rd FIFO and the 4th FIFO are the second group command FIFO, described the first group command FIFO and the second group command FIFO are used for depositing described memory access order, the read-write requests demanded storage of even number bank is in a described FIFO and the 3rd FIFO, the read-write requests demanded storage of odd number bank is in described the 2nd FIFO and the 4th FIFO, the 5th FIFO is read data FIFO, and the 6th FIFO is for writing data FIFO;
Two counters, the first counter is connected to a FIFO and the 2nd FIFO of described the first group command FIFO, the second counter is connected to the 3rd FIFO and the 4th FIFO of described the second group command FIFO, count when reading and writing processing in order to this group command FIFO that connects at a counter, and will reach the refresh cycle time, jump to another group command FIFO and read and write processing, with this hiding refreshes clock period;
Two anticipation logical blocks, the first anticipation logical block connects respectively a FIFO and the 2nd FIFO of described the first group command FIFO, the second anticipation logical block connects respectively the 3rd FIFO and the 4th FIFO of described the second group command FIFO, and described anticipation logical block activates and the precharge clock period in order to hide;
A status command converting unit, connect described the first group command FIFO by described the first anticipation logical block respectively, connect described the second group command FIFO by described the second anticipation logical block, and connect described read data FIFO and write data FIFO, in order to according to described each FIFO of control;
An initialization logic unit is connected in described status command converting unit, in order to realize the initialization of described status command converting unit.
6. the controller that is applied to the DDR3 storer in the network processing unit according to claim 5, it is characterized in that, the width of a described FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 27, and the degree of depth of a FIFO, the 2nd FIFO, the 3rd FIFO and the 4th FIFO is 32; The width of described the 5th FIFO and the 6th FIFO is 128, and the degree of depth of the 5th FIFO and the 6th FIFO is 128.
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| CN112052206A (en) * | 2020-08-31 | 2020-12-08 | 浙江双成电气有限公司 | Multi-port data storage system based on arbitration |
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| CN102543159A (en) * | 2010-12-29 | 2012-07-04 | 炬才微电子（深圳）有限公司 | Double data rate (DDR) controller and realization method thereof, and chip |
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