CN102929644A - Embedded operational control logic used for computer hardware experimental microprocessor - Google Patents
Embedded operational control logic used for computer hardware experimental microprocessor Download PDFInfo
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Abstract
The invention particularly relates to an embedded operational control logic used for a computer hardware experimental microprocessor, which belongs to the technical field of an experimental apparatus in computer teaching. The embedded operational control logic comprises a machine instruction single step end mark shifting register submodule, an operating control command shifting register submodule, a breakpoint data shifting register submodule, an operating condition controller submodule, a machine instruction single step end judging logic submodule and a breakpoint matching logic submodule. The operational control logic and an experimental microprocessor circuit are arranged in the same FPGA (field programmable gate array) chip, has operational control modes such as single clock pulse, microinstruction single step, instruction single step, microinstruction breakpoint, instruction breakpoint, continuous operation, stopping operation, and reset for the microprocessor and is applicable to the microprocessor under microprocess control and hard wire control.
Description
Technical field
The invention belongs to computer teaching experimental apparatus technical field, be specifically related to a kind of embedded operation steering logic for the computer hardware experiment microprocessor, the education experiment of main computer-oriented theory of constitution, Computer Systems Organization also can be used for the experiment of the computer hardware series courses such as DLC (digital logic circuit), Computer Interface Technology.
Background technology
Present stage, domestic each university computer theory of constitution and Computer Systems Organization course adopt the FPGA(field programmable gate array) carry out the experimental teaching mode that the microprocessor Design experiment has become a kind of advanced person, also there have been some experimental provisions to occur.In the prior art, experimental provision uses the mode of independent control desk to control the operation of experiment microprocessor, control desk is in the different chips with the experiment microcontroller circuit, the experimenter produces various control signals by operating on computers the control control desk, the operation of control experiment microprocessor.Adopt the chip microcontroller control desk such as patent of invention CN1741094, realize CPU is carried out the control of half clock, 1 clock and continuous operation, but the breakpoint operation can not be set, also do not have the operation of micro-order single step run and micro-order breakpoint; Patent of invention CN101290724 adopts custom-designed FPGA as control chip, be used for sending rambus all control signals, monitor the register information of experiment chip, externally send message, control the operation of experiment CPU by the clock of control experiment chip, but lack equally the operation control of microprogram, the breakpoint operation shortage that can improve conventional efficient is provided powerful support for; The FD-MCES Computer Systems Organization experiment instrument that Fudan University sky glad Science ﹠ Teaching Instrument factory produces adopts SCM﹠FPGA jointly to realize control desk, can carry out to the experiment microprocessor of microprogram control or Hardwired control single step or continuously operation control, but the operation control of micro-order can only be provided under the microprogram control mode, can not be take machine instruction as the unit controlling run.In addition, above-mentioned prior art adopts independently chip realization control desk, and its function need to design curing in advance for specific experiment, and is opaque to the experimenter, can not be by experimenter's flexible configuration; Control desk is fixed with the annexation of experiment chip, has limited to a certain extent the design of experiment microprocessor, has retrained the performance of experimenter's innovation ability.
In sum, the operation steering logic that lacks at present the operation of a kind of effective control experiment microprocessor, can be applicable to the microprocessor of microprogram control and Hardwired control, has comprehensive, efficient operation control method, such as micro-order single step, instruction single step, micro-order breakpoint, instruction breakpoint and the continuous operation control method such as operation at full speed, and can embed test chip internal, transparent to the experimenter, can be by experimenter's flexible configuration.
Summary of the invention
Limitation and deficiency that the implementation of controlling in the operation of experiment microprocessor for above-mentioned prior art Computer hardware experiments device exists, a kind of embedded operation steering logic for computer hardware experiment experiment microprocessor has been proposed, it is inner that this operation steering logic and experiment microcontroller circuit are present in same fpga chip, has the single clock pulse, the micro-order single step, the instruction single step, the micro-order breakpoint, instruction breakpoint, continuously operation, the microprocessor operation control method such as out of service and reset is applicable to the microprocessor of microprogram control and Hardwired control.
To achieve these goals, the present invention proposes a kind of operation steering logic for computer hardware experiment experiment microprocessor, comprise machine instruction single step end mark shift register, operation control command shift register, the breakpoint data shift register, the running status controller, the machine instruction single step finishes decision logic and six submodules of breakpoint matching logic, wherein, machine instruction single step end mark shift register, operation control command shift register and breakpoint data shift register are connected in turn in the shift register group, and data are transmitted logic by information and write in the mode that is shifted; Machine instruction single step end mark shift register is used for depositing the single step of experiment microprocessor machine instruction and finishes judgement symbol; Operation control command shift register is used for depositing microprocessor operation control command; The breakpoint data shift register is used for depositing the breakpoint data; The running status controller adopts the mode of automat to produce the reset signal of experiment microprocessor, the operation control signal of experiment microprocessor different running method and the enable signal that the machine instruction single step finishes decision logic and breakpoint matching logic; The machine instruction single step finishes decision logic according to the current state of experiment microprocessor and running status controller, sends current machine instruction to the running status controller and carries out end mark; The breakpoint matching logic sends the breakpoint match flag according to the current state of experiment microprocessor and running status controller to the running status controller.
Further, the running status controller comprises two automats, and an automat produces the reset signal of experiment microprocessor, makes the experiment microprocessor enter original state; Another automat can produce the enable signal that the machine instruction single step finishes decision logic and breakpoint matching logic, and realizes 7 kinds of methods of operation such as the single clock pulsing operation of experiment microprocessor, continuously operation, out of service, micro-order single step run, machine instruction single step run, the operation of micro-order breakpoint, the operation of machine instruction breakpoint.Wherein, the single clock pulsing operation makes the operation control signal effective, and the experiment microprocessor enters running status, discharges the operation control signal behind the processor clock cycle, and the experiment microprocessor enters halted state; Continuously operation makes operation control signal continuously effective, and the experiment microprocessor enters running status, until the operation steering logic when receiving order out of service, discharges the operation control signal, tests microprocessor and enters halted state; Mode out of service makes the operation control signal invalid, and the experiment microprocessor enters halted state, and this operation control function is only working under the operation control continuously; Micro-order single step run mode makes the operation control signal effective, and the experiment microprocessor enters running status, behind two processor clock cycles, discharges the operation control signal, and the experiment microprocessor enters halted state; Machine instruction single step run mode makes the operation control signal effective, and the experiment microprocessor enters running status, until detect when testing complete bar machine instruction of microprocessor executed, discharges the operation control signal, and the experiment microprocessor enters halted state; The micro-order breakpoint operation method of operation makes the operation control signal effective, the experiment microprocessor enters running status, until detect when testing the complete set breakpoint micro-order of microprocessor executed, discharge the operation control signal, the experiment microprocessor enters halted state, the experimenter sends before this order, and the breakpoint micro-order need to be set in advance; The machine instruction breakpoint operation method of operation makes the operation control signal effective, thereby make the experiment microprocessor enter running status, until detect when testing the complete set breakpoint machine instruction of microprocessor executed, discharge the operation control signal, the experiment microprocessor enters halted state; The experimenter sends before this order, and the breakpoint micro-order need to be set in advance.
Further, whether executed is to represented micro-order or the machine instruction of break value according to micro address register, programmable counter and the break value judgment experiment microprocessor of testing microprocessor for the breakpoint matching logic, and sends the breakpoint match flag to the running status controller.The breakpoint matching logic comprises Bp demoder, micro-order breakpoint comparer, machine instruction breakpoint comparer and selector switch, and wherein, the Bp demoder is resolved the breakpoint data according to the form of breakpoint data; Micro-order breakpoint comparer is responsible for micro-order breakpoint coupling; Machine instruction breakpoint comparer is responsible for machine instruction breakpoint coupling; Selector switch is selected output to the output of micro-order breakpoint comparer and machine instruction breakpoint comparer.
Further, the machine instruction single step finishes decision logic and comprises StepEndFlag register and comparer, wherein the StepEndFlag register is deposited the machine instruction end of run judgement symbol by machine instruction single step end mark shift register propagation, and comparer judges according to current microinstruction address and machine instruction end of run judgement symbol whether current machine instruction carries out end.
The embedded operation steering logic of experiment microprocessor that the present invention realizes has more comprehensive operation control method, is not only applicable to the microprocessor of hard wire, also is applicable to microprogrammed microprocessor; For microprogrammed experiment microprocessor, not only have micro-order single step and the micro-order breakpoint method of operation, also have machine instruction single step and the breakpoint method of operation, improved experiment convenience and efficient.The embedded operation steering logic of experiment microprocessor that the present invention realizes is in same FPGA inside with the experiment microprocessor, need not the extra chips such as single-chip microcomputer as control desk, and cost is low; Transparent to the experimenter, can by the internal register of experimenter according to the design configurations operation steering logic of experiment microprocessor, have larger dirigibility and stronger practicality.
Description of drawings
Figure 1 shows that the specific embodiment of embedded operation steering logic in the computer hardware experiment system;
Figure 2 shows that the structured flowchart of the embedded operation steering logic of computer hardware experiment microprocessor of the present invention;
Figure 3 shows that the state transition diagram of the automat 1 of running status controller in the embedded operation steering logic of computer hardware experiment microprocessor of the present invention;
Figure 4 shows that the state transition diagram of the automat 2 of running status controller in the embedded operation steering logic of computer hardware experiment microprocessor of the present invention;
Figure 5 shows that the structured flowchart of the embedded operation steering logic of computer hardware experiment microprocessor of the present invention point of interruption matching logic;
Figure 6 shows that the structured flowchart of machine instruction single step end decision logic in the embedded operation steering logic of computer hardware experiment microprocessor of the present invention.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and embodiment.
Be illustrated in figure 1 as embedded operation steering logic at a specific embodiment of computer hardware experiment system, the present embodiment adopts fpga chip to transmit the carries chips of logic and experiment microprocessor as operation steering logic, information, namely move steering logic, information transmission logic and experiment microprocessor and be configured in same fpga chip inside, the experiment microprocessor uses 16 micro-order processors of independent development JU-C2.As can be seen from the figure, information transfer module links to each other with computing machine by the USB-JTAG protocol converter, reception is from service data and the control command of the experiment microprocessor of computing machine, send to the operation steering logic after the processing, the operation steering logic produces the operation control signal of experiment microprocessor.
Be illustrated in figure 2 as the structured flowchart of the embedded operation steering logic of the computer hardware experiment microprocessor that the present invention proposes, move as can be seen from Figure 2 steering logic by machine instruction single step end mark shift register, operation control command shift register, the breakpoint data shift register, the running status controller, the machine instruction single step finishes decision logic and 6 parts of breakpoint matching logic form, wherein, machine instruction single step end mark shift register, operation control command shift register and breakpoint data shift register are connected in turn in the scan chain of USB-JTAG protocol converter, and TDI and TDO be data input pin and the data output end of corresponding displaced register group respectively.Machine instruction single step end mark shift register is responsible for receiving and storage information is transmitted the data of logical delivery, produces machine instruction end of run judgement symbol Flag signal; Operation control command shift register is responsible for receiving and storage information is transmitted the data of logical delivery, produces processor operation control command Cmd signal; The breakpoint data shift register is responsible for receiving and storage information is transmitted the data of logical delivery, produces breakpoint data Bp signal, and the Bp signal is divided into micro-order break value and machine instruction break value according to its data encoding rule; The running status controller is according to the microprocessor operation control command Cmd of operation control command shift register propagation, use 2 automats to produce respectively experiment microprocessor operation control signal Run and experiment microprocessor reset signal CPUReset, and produce the machine instruction single step finish decision logic enable control signal StepRun and breakpoint matching logic enable control signal BpRun; Whether executed is to break-poing instruction according to breakpoint data Bp, the experiment programmable counter PC of microprocessor and micro address register uAR judgment experiment microprocessor for the breakpoint matching logic, and sends breakpoint match flag BpStop to the running status controller; The machine instruction single step finishes decision logic, and whether executed finishes according to the current machine instruction of the micro address register uAR judgment experiment microprocessor of machine instruction end of run judgement symbol Flag signal and experiment microprocessor, and carries out end mark StepStop to the instruction of running status controller distribution of machine.
Above-mentioned machine instruction single step end mark shift register, operation control command shift register and breakpoint data shift register transmit logic by the information in the experimental provision data are provided, and are connected in turn in the shift register group; Machine instruction single step end mark shift register finishes decision logic with the machine instruction single step and links to each other by the Flag signal wire; The breakpoint data shift register is connected by the Bp signal wire with the breakpoint matching logic; The running status controller is connected by the Cmd signal wire with operation control command shift register, finishing decision logic with the machine instruction single step links to each other with the StepStop signal wire by StepRun, link to each other with the BpStop signal wire by BpRun with the breakpoint matching logic, link to each other by Run and CPUReset signal wire with the experiment microprocessor; The machine instruction single step finishes decision logic and links to each other by the uAR signal wire with the experiment microprocessor; The breakpoint matching logic links to each other with programmable counter PC signal wire by micro address register uAR with the experiment microprocessor.
Above-mentioned running status controller can be realized single clock pulse, continuously operation, out of service, micro-order single step run, machine instruction single step run, the operation of micro-order breakpoint and seven kinds of microprocessor methods of operation of machine instruction breakpoint operation by its inner automat 1, automat 1 is output as the Run signal, wherein:
The single clock pulse: it is effective that the operation steering logic produces operation control signal Run signal, makes the experiment microprocessor enter running status, and the Run signal is only kept the effective time of a processor clock cycle, is used for controlling the single step run of experiment microprocessor;
Continuously operation: it is effective that the operation steering logic produces operation control signal Run signal, makes the experiment microprocessor enter running status, and continue to keep the Run signal effective;
Out of service: the operation steering logic makes operation control signal Run invalidating signal, makes the experiment microprocessor enter halted state, and this operation control command is only working in the effective situation of operation control command continuously;
The micro-order single step: it is effective that the operation steering logic produces operation control signal Run signal, make the experiment microprocessor enter running status, after the Run signal was kept two processor clock cycles, it is invalid that the automatic release of Run signal becomes, and the experiment microprocessor enters halted state;
The machine instruction single step: it is effective that the operation steering logic produces operation control signal Run signal, make the experiment microprocessor enter running status, begin to carry out current machine instruction, and make the StepRun signal that sends to machine instruction single step end decision logic effective, the operation steering logic finishes the state of the StepStop input experiment microprocessor of decision logic loopback by the machine instruction single step, until detect complete bar machine instruction of experiment microprocessor executed, be that the StepStop signal is effective, discharge Run and StepRun signal, the experiment microprocessor enters halted state;
The operation of micro-order breakpoint: the experimenter sends before this order to the operation steering logic, and the breakpoint data shift register need to be set in advance.It is effective that the operation steering logic produces operation control signal Run signal, make the experiment microprocessor enter running status, and make the BpRun signal that sends to the breakpoint matching logic effective, the operation steering logic is by the state of the BpStop input experiment microprocessor of breakpoint matching logic loopback, until detect the complete set breakpoint micro-order of experiment microprocessor executed, be that the BpStop signal is effective, discharge Run and BpRun signal, the experiment microprocessor enters halted state;
The operation of machine instruction breakpoint: the experimenter sends before this order to the operation steering logic, and the breakpoint data shift register need to be set in advance.It is effective that the operation steering logic produces operation control signal Run signal, make the experiment microprocessor enter running status, and make the BpRun signal that sends to the breakpoint matching logic effective, the operation steering logic is by the state of the BpStop input experiment microprocessor of breakpoint matching logic loopback, until detect the complete set breakpoint micro-order of experiment microprocessor executed, be that the BpStop signal is effective, discharge Run and BpRun signal, the experiment microprocessor enters halted state.
Above-mentioned running status controller can by automat 1 produce the machine instruction single step finish decision logic enable control signal StepRun signal and breakpoint matching logic enable control signal BpRun signal; The running status controller can produce experiment microprocessor reset signal by automat 2, and namely the CPUReset signal makes microprocessor enter original state.
Be illustrated in figure 3 as the state transition diagram of the inside automat 1 of running status controller, comprise seven states, be respectively IDLE, BeginRun, ExecuteRun, WaitBreak, WaitEnd, WaitStop and EndRun state, wherein:
The IDLE state: automat 1 enters the IDLE idle condition after reset signal Reset is effective, this moment, the operation control signal Run of running status controller output was invalid, under the effect of single step, breakpoint and continuous operation operation control command, state transitions occurs in automat 1, and next state is the BeginRun state;
BeginRun state: under this state, the operation control signal Run of running status controller output is effective, the experiment microprocessor enters running status, and the difference according to experiment microprocessor operation control command enters different states at the next efficient clock edge of running status controller.When the operation control command was the single clock pulse, next state was the EndRun state; Otherwise next state is the ExecuteRun state;
ExecuteRun state: under this state, the operation control signal Run of running status controller output is effective, the experiment microprocessor is in running status, and the difference according to experiment microprocessor operation control command enters different states at the next efficient clock edge of running status controller.When the operation control command was continuously operation, next state was the WaitStop state; When the operation control command was the micro-order single step, next state was the EndRun state; When the operation control command was the machine instruction single step, next state was the WaitEnd state; When the operation control command was the operation of micro-order breakpoint or the operation of machine instruction breakpoint, next state was the WaitBreak state;
The WaitBreak state: under this state, the operation control signal Run of running status controller output is effective, and the BpRun signal that is sent to the breakpoint matching logic is effective, and the experiment microprocessor is in running status.At this moment, uAR and the PC of breakpoint matching logic cycle detection experiment microprocessor are until after processor moved to the micro-order breakpoint or machine instruction breakpoint that has arranged, the output BpStop of breakpoint matching logic was effective, state transitions occurs in operation control automat 1, and next state is the EndRun state;
The WaitEnd state: under this state, the operation control signal Run of running status controller output is effective, and the StepRun signal that is sent to machine instruction sheet EOS decision logic is effective, and the experiment microprocessor is in running status.At this moment, the machine instruction single step finishes the uAR of decision logic cycle detection experiment microprocessor, until processor executes this machine instruction, the output StepStop signal of machine instruction single step end decision logic is effective, state transitions occurs in operation control automat 1, and next state is the EndRun state;
The WaitStop state: under this state, the operation control signal Run of running status controller output is effective, and the experiment microprocessor is in running status.At this moment, running status controller cycle detection is received from the processor operation control command Cmd that information is transmitted logic, if Cmd is control command out of service, state transitions occurs automat 1, and next state is the EndRun state;
The EndRun state: under this state, the operation control signal Run of running status controller output is invalid, and the experiment microprocessor enters halted state, and at the next efficient clock edge of running status controller, state transitions occurs automat 1, and next state is the IDLE state.
Be illustrated in figure 4 as the state transition diagram of the inside automat 2 of running status controller, comprise two states, be respectively IDLE, ResetOP state.Automat 2 enters the IDLE idle condition after reset signal Reset is effective, this moment, the output signal CPUReset of running status controller was invalid, and under the effect of cpu reset operation control command, state transitions occur automat 2, and next state is the ResetOP state;
Figure 5 shows that the structured flowchart of breakpoint matching logic, comprise Bp demoder, micro-order breakpoint comparer, machine instruction breakpoint comparer and selector switch, wherein, the Bp demoder is resolved according to the form of the breakpoint data output Bp to the breakpoint data shift register, and the Sel signal that produces micro-order break value uARBp, machine instruction break value PCBp and distinguish machine instruction and micro-order breakpoint; Micro-order breakpoint comparer compares at uAR signal and the micro-order break value uARBp to the experiment microprocessor, produces matched signal uAROK; Machine instruction breakpoint comparer compares uAR signal, PC signal and the machine instruction break value PCBp of experiment microprocessor, produces matched signal PCOK; Selector switch is selected output uAROK and PCOK signal according to the Sel signal that the Bp demoder produces, and produces the BpStop signal.After the running status controller receives the operation of micro-order breakpoint or machine instruction breakpoint operation control command, make breakpoint matching logic enable signal BpRun effective, the breakpoint matching logic is according to value uAR, value PC and the break value Bp of programmable counter of the micro address register of experiment microprocessor, whether executed is to represented micro-order or the machine instruction of break value Bp for the judgment experiment microprocessor, and sends breakpoint match flag BpStop to the running status controller.
Figure 6 shows that the machine instruction single step finishes the structured flowchart of decision logic, comprise StepEndFlag register and comparer, wherein the StepEndFlag register is deposited the machine instruction end of run judgement symbol Flag by machine instruction single step end mark shift register propagation; Comparer is responsible for current microinstruction address uAR and machine instruction end of run judgement symbol StepEndFlag are compared, and output StepStop signal, if whether current microinstruction address uAR equates to judge with StepEndFlag whether current machine instruction carries out end, when equating the current machine instruction executed of expression with StepEndFlag, the value of uAR finishes, put the StepStop signal effective, otherwise that the StepStop signal is set to is invalid.After the running status controller receives machine instruction single step run control command, make the machine instruction single step finish decision logic enable signal StepRun effective, the machine instruction single step finishes decision logic and judges that according to the value uAR of experiment microprocessor micro address register and the Flag of machine instruction single step end mark shift register output whether executed finishes current machine instruction, carries out end mark StepStop to the instruction of running status controller distribution of machine.
Claims (4)
1. an embedded operation steering logic that is used for the computer hardware experiment microprocessor is characterized in that comprising that machine instruction single step end mark shift register, operation control command shift register, breakpoint data shift register, running status controller, machine instruction single step finish decision logic and breakpoint matching logic;
Described machine instruction single step end mark shift register is used for depositing the single step of experiment microprocessor machine instruction and finishes judgement symbol;
Described operation control command shift register is used for depositing microprocessor operation control command;
Described breakpoint data shift register is used for depositing the breakpoint data;
Reset signal, experiment microprocessor operation control signal and the machine instruction single step that described running status controller adopts the mode of automat to produce the experiment microprocessor finishes the enable signal of decision logic and breakpoint matching logic;
Described machine instruction single step finishes decision logic according to the current state of experiment microprocessor and running status controller, sends current machine instruction to the running status controller and carries out end mark;
Described breakpoint matching logic sends the breakpoint match flag according to the current state of experiment microprocessor and running status controller to the running status controller;
Described machine instruction single step end mark shift register, operation control command shift register and breakpoint data shift register are connected in turn in the shift register group, and data are transmitted logic by information and write in the mode that is shifted.
2. the embedded operation steering logic for the computer hardware experiment microprocessor as claimed in claim 1, it is characterized in that, described running status controller comprises two automats, automat produces the reset signal of experiment microprocessor, and another automat can realize testing 7 kinds of methods of operation such as the single clock pulsing operation of microprocessor, continuously operation, out of service, micro-order single step run, machine instruction single step run, the operation of micro-order breakpoint, the operation of machine instruction breakpoint;
Single clock pulsing operation mode: make the operation control signal effective, the experiment microprocessor enters running status, discharges the operation control signal behind the processor clock cycle, and the experiment microprocessor enters halted state;
Continuously-running duty: make operation control signal continuously effective, the experiment microprocessor enters running status, until the operation steering logic when receiving order out of service, discharges the operation control signal, tests microprocessor and enters halted state;
Mode out of service: make the operation control signal invalid, the experiment microprocessor enters halted state, and this operation control function is only working under the operation control continuously;
Micro-order single step run mode: make the operation control signal effective, the experiment microprocessor enters running status, behind two processor clock cycles, discharges the operation control signal, and the experiment microprocessor enters halted state;
Machine instruction single step run mode: make the operation control signal effective, the experiment microprocessor enters running status, until detect when testing complete bar machine instruction of microprocessor executed, discharges the operation control signal, and the experiment microprocessor enters halted state;
The micro-order breakpoint method of operation: make the operation control signal effective, the experiment microprocessor enters running status, until detect when testing the complete set breakpoint micro-order of microprocessor executed, discharge the operation control signal, the experiment microprocessor enters halted state; The experimenter sends before this order, and the breakpoint micro-order need to be set in advance;
The machine instruction breakpoint method of operation: make the operation control signal effective, thereby make the experiment microprocessor enter running status, until detect when testing the complete set breakpoint machine instruction of microprocessor executed, discharge the operation control signal, the experiment microprocessor enters halted state; The experimenter sends before this order, and break-poing instruction need to be set in advance.
3. the embedded operation steering logic for the computer hardware experiment microprocessor as claimed in claim 1, it is characterized in that, described breakpoint matching logic comprises Bp demoder, micro-order breakpoint comparer, machine instruction breakpoint comparer and selector switch, wherein, the Bp demoder is resolved the breakpoint data according to the form of breakpoint data; Micro-order breakpoint comparer is responsible for micro-order breakpoint coupling; Machine instruction breakpoint comparer is responsible for machine instruction breakpoint coupling; Selector switch is selected output to the output of micro-order breakpoint comparer and machine instruction breakpoint comparer.
4. the embedded operation steering logic for the computer hardware experiment microprocessor as claimed in claim 1, it is characterized in that, described machine instruction single step finishes decision logic and comprises StepEndFlag register and comparer, wherein the StepEndFlag register is deposited the machine instruction end of run judgement symbol by machine instruction single step end mark shift register propagation, and comparer judges according to current microinstruction address and machine instruction end of run judgement symbol whether current machine instruction carries out end.
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| CN108710554A (en) * | 2018-05-21 | 2018-10-26 | 上海兆芯集成电路有限公司 | processor debugging system and method |
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| US20020188889A1 (en) * | 2001-05-16 | 2002-12-12 | Phan Michael Huy | Performance measurement for embedded systems |
| CN1741094A (en) * | 2005-09-16 | 2006-03-01 | 清华大学科教仪器厂 | Experimental apparatus for computer composition principle and system structure |
| CN101290724A (en) * | 2008-06-13 | 2008-10-22 | 清华大学 | Computer hardware series course experimental device |
| CN101826052A (en) * | 2010-05-04 | 2010-09-08 | 中国人民解放军国防科学技术大学 | Implementation method of break point for maintaining time-delay consistency in NUAL (Non-unit Assumed Operation Latencies) execution semantic microprocessor |
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| US20020188889A1 (en) * | 2001-05-16 | 2002-12-12 | Phan Michael Huy | Performance measurement for embedded systems |
| CN1741094A (en) * | 2005-09-16 | 2006-03-01 | 清华大学科教仪器厂 | Experimental apparatus for computer composition principle and system structure |
| CN101290724A (en) * | 2008-06-13 | 2008-10-22 | 清华大学 | Computer hardware series course experimental device |
| CN101826052A (en) * | 2010-05-04 | 2010-09-08 | 中国人民解放军国防科学技术大学 | Implementation method of break point for maintaining time-delay consistency in NUAL (Non-unit Assumed Operation Latencies) execution semantic microprocessor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108710554A (en) * | 2018-05-21 | 2018-10-26 | 上海兆芯集成电路有限公司 | processor debugging system and method |
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