CN102915277A - Method for improving copying speed of internal data of flash memory chips, flash memory storage system and controller of system - Google Patents
Method for improving copying speed of internal data of flash memory chips, flash memory storage system and controller of system Download PDFInfo
- Publication number
- CN102915277A CN102915277A CN2012103944472A CN201210394447A CN102915277A CN 102915277 A CN102915277 A CN 102915277A CN 2012103944472 A CN2012103944472 A CN 2012103944472A CN 201210394447 A CN201210394447 A CN 201210394447A CN 102915277 A CN102915277 A CN 102915277A
- Authority
- CN
- China
- Prior art keywords
- page
- copied
- data
- flash
- error rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a method for improving the copying speed of internal data of flash memory chips. Each flash memory chip comprises a plurality of storage blocks, and each storage block comprises a plurality of pages. The method comprises the following steps of: detecting the noise margin of a page to be copied under the current worst condition, and acquiring the current maximum bit error rate of the page to be copied according to the noise margin under the worst condition; detecting whether at least one available copied target page exists in all the flash memory chips, and ensuring that the accumulated bit error rate of the current maximum bit error rate of the copied target page and the current maximum bit error rate of the page to be copied can be tolerated by applied error correcting codes; if so, directly reading the data of the page to be copied, and copying the data into any one copied target page. The invention also discloses a flash memory storage system and a controller thereof. According to the invention, the influence on the operating speed of the solid-stage storage system can be alleviated in the running process of transfer layer firmware by effectively utilizing the operating characteristics of a storage unit of the flash memory chip, and the implementation process is easy and feasible.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of method, flash-memory storage system and controller thereof that improves flash chip internal data copying speed.
Background technology
[0002] as the solid-state non-volatile data storing technology of unique main flow, flash memory has become a ring with the fastest developing speed in the global semiconductor industrial system.Market intelligence showed in 2010, and the market of flash memory products has been broken through 20,000,000,000 dollars.Solid-state data-storage system based on flash chip mainly comprises a solid-state memory system controller and an above flash chip.
The essential information storage unit of flash chip is floating gate transistor (Floating-Gate Transistor).The threshold voltage of floating gate transistor can enter floating boom by the electronics of injection some and change.Therefore, by the accurate control to number of electrons in the floating boom, each storage unit, namely floating gate transistor can store a plurality of bit informations.Accurately the process of number of electrons is commonly called programming in the control floating boom.Before each storage unit can be programmed, all electronics in its floating boom must be removed, thereby so that its threshold voltage is set to minimumly, this process is called as wipes.In the process to information memory cell programming, industry uses a kind of method of gradual " programming-verification-again programming " with the accurate control of realization to number of electrons in the floating boom." program/erase " operation that repeats directly causes the aging gradually of flash memory chip data storage unit, and its noise tolerance limit is reduced gradually.After a storage unit lives through many " program/erase " operations, will lose the data storage function of its nominal.In order to prolong the serviceable life of flash chip, must the wear out operation of balanced (Wear-leveling) of solid-state memory system controller chip, its purpose is as far as possible so that almost identical " program/erase " number of operations of all flash memory physical pages experience, degree of aging that like this can balanced all pages.But in aging balanced operating process, in order to reach the purpose of " program/erase " number of operations equilibrium, can introduce unnecessary data copy operation.
Information memory cell array in the flash chip is divided into a plurality of storage blocks, and each storage block comprises a plurality of memory pages.As base unit, the user data that comprises in each page is generally 4096 bytes (byte), 8192 bytes or 16384 bytes to the flash memory chip data read-write operation with the page (page).The memory page of some (such as 256,512) forms a storage block, and flash chip is made of the storage block of a large amount of equal sizes and necessary peripheral auxiliary circuits.Data erase operation must be take storage block as unit.
All storage unit in each storage block must be erased simultaneously, but the programming of storage unit and reading then take the page as unit.In system's operational process, before wiping a certain storage block, must with in it all still active data be copied in another storage block.All these data copy operations are finished by solid-state data-storage system conversion layer (Flash Translation Layer) firmware design.
Number of patent application is 6,040, No. 997 United States Patent (USP)s have been introduced patentee and a kind of technology that other people are known, flash memory system wherein comprises an internal buffer, directly be rewritten to the second place the flash memory so that the data communication device that the primary importance within flash memory reads is crossed the internal buffer, need not these data are passed out outside the flash memory.This has just improved data transfer time.But, this known technology does not provide error checking and correction (ECC), but supposes that simply the data that read from first flash locations are accurately.
Yet, in order at utmost to improve the reliability of data storage, must first the data of the page to be copied be read in and carry out in the solid-state data storage system controller again these data being write in the another one page after error correction decode operates to obtain right-on raw data.Although this mode of operation can at utmost improve the reliability of data storage, can take simultaneously valuable system bus resource and error-correcting code decoder resource, and then reduce the travelling speed of data-storage system integral body.
Application number is that China of 201110008910. 0 applies for a patent and discloses a kind of flash memory system that has error-detecting and calibration function in page or leaf replicate run process.This flash memory system can prevent from from page or leaf transcription error position to, source copying page or leaf.The embodiment of this invention flash memory comprises a correcting circuit that is used for being stored under the school bit-errors of page buffer source data, one is disposed to such an extent that be suitable for providing source data to correcting circuit and the circuit of correction data to page buffer is provided, and one is disposed to such an extent that be suitable for copy source data to page buffer and correction data stored into the duplicate circuit of another page from page buffer.The source data of the primary importance of memory cell array is stored in the impact damper, then the bit-errors of the source data of detection of stored in impact damper, when detecting bit-errors, proofread and correct this bit-errors, and after described correction, the source data after proofreading and correct is copied on the second place of memory cell array.When although disclosed system can improve the reliability of data storages and reduce to a certain extent the FTL operation for the impact of flash-memory storage system performance, but the process more complicated of utilizing this system to realize, or need to carry out error correction to source data and judge, no matter whether source data has the possibility that bit-errors occurs; But also need to change the program/erase procedure of existing flash-memory storage system and realize, be unfavorable for popularizing and use.
Summary of the invention
Embodiments of the invention provide a kind of method, flash-memory storage system and controller thereof that improves flash chip internal data copying speed, on the impact of solid-state memory system travelling speed, and implementation procedure was simple, easy row when the operating characteristic that can effectively utilize flash memory chip storage unit reduced the operation of conversion layer firmware.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of method that improves flash chip internal data copying speed, wherein each flash chip has a plurality of storage blocks, and each storage block comprises a plurality of pages, and the method comprising the steps of:
Detect the noise tolerance limit under the current worst condition of the page to be copied, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition;
Detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If then the data of the page to be copied are directly read and are copied in arbitrary described copy targeting page.
A kind of controller comprises:
Microprocessing unit;
Flash interface is coupled to described microprocessing unit and a plurality of flash chip, and wherein each flash chip has a plurality of storage blocks, and each storage block comprises a plurality of pages;
The flash memory management module, be coupled to described microprocessing unit by microprocessing unit described a plurality of flash chips are carried out the flash memory process program, comprise: detect the noise tolerance limit under the current worst condition of the page to be copied, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition; Detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If then the data of the page to be copied are directly read and are copied in arbitrary described copy targeting page.
A kind of flash-memory storage system comprises:
A plurality of flash chips, each flash chip has a plurality of storage blocks, and each storage block comprises a plurality of storage unit;
Controller is coupled to described a plurality of flash chip detecting the noise tolerance limit under the current worst condition of the page to be copied, and obtains the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition; Detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If there is at least one described copy targeting page, then the data of the page to be copied directly read and copied in arbitrary described copy targeting page.
A kind of method, flash-memory storage system and controller thereof that improves flash chip internal data copying speed that the embodiment of the invention provides passes through to detect the noise tolerance limit under the current worst condition of the page to be copied, and obtains the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition; And detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If there is at least one described copy targeting page, then the data of the page to be copied are directly read and are copied in arbitrary described copy targeting page; If there is not the described copy targeting page, then first the data reading of the page to be copied to be processed to carry out error correcting code, the correct page data after will processing through error correcting code again copies in another available page.Namely be, use when of the present invention, if the bit error rate of the page to be copied is enough low, make and have another free Page in the flash memory, so that the bit error rate of this two page also can not exceed the error correcting capability of error correcting code after directly cumulative, then directly page data to be copied is copied so far free Page, obviously, under the prerequisite that does not reduce storage system stability, can directly reduce taking and then reduce conversion layer firmware when operation to the impact of solid-state memory system travelling speed system resource.Therefore, when the operating characteristic that effectively utilizes flash memory chip storage unit reduces the operation of conversion layer firmware on the impact of solid-state memory system travelling speed, reach the purpose that improves flash chip internal data copying speed, and design of the present invention and the design of existing solid-state memory system are directly compatible, and implementation procedure is simple.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the composition frame chart of a kind of flash-memory storage system in the embodiment of the invention 1;
Fig. 2 is the composition frame chart of flash chip in the embodiment of the invention 1;
Fig. 3 ~ 4th, prior art compares synoptic diagram with the operational process that the flash-memory storage system that utilizes in the embodiment of the invention 1 is realized;
Fig. 5 is the composition frame chart of a kind of controller in the embodiment of the invention 2;
Fig. 6 is a kind of method flow diagram that improves flash chip internal data copying speed in the embodiment of the invention 3.
Fig. 7 is the another kind of method flow diagram that improves flash chip internal data copying speed in the embodiment of the invention 4.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Embodiment 1
The embodiment of the invention provides a kind of flash-memory storage system, as shown in Figure 1, flash-memory storage system 100 comprises controller 110 and flash memory 120, usually flash-memory storage system 100 can use with main frame 140, and by communication interface 130 connections, so that main frame 140 can write to data storage system 100 or reading out data from storage system 100.In the present embodiment, main frame 140 can be any system that computing machine, digital camera, video camera, communicator, audio player or video player etc. can be stored data.Communication interface 130 can be USB interface, PCI Express interface, SATA interface, MS interface, MMC interface, SD interface, CF interface, ide interface or other data transmission interfaces that is fit to.In the present embodiment, described flash-memory storage system 100 is solid state hard disc (Solid State Drive, SDD), but intelligible, this flash-memory storage system 100 also can be Portable disk or storage card in other embodiments.
Flash interface 110b is electrically connected to microprocessing unit 110a and in order to access flash memory 120, and namely, the user data that main frame 140 wants to write to flash memory 120 can be converted to 120 receptible forms of flash memory via flash interface 110b.Particularly, in this enforcement, flash memory management module 110c is to the acquisition of information of flash memory 120 and to send control command etc. also be to need by flash interface 110b.
Error correcting code coding module 110d is electrically connected to microprocessing unit 210a and is used for the user data of wanting to write is carried out the error correcting code coding, thereby produce corresponding error correcting code coding redundancy and therewith data together be stored in the same flash memory pages 124 of flash chip 122, wherein afterwards when from flash memory pages 124, reading these data, error correcting code coding module 110d can check whether data are correct according to the error correcting code coding redundancy, perhaps attempts the data of mistake are reverted to correct data when data are incorrect.The error correcting code coding redundancy is to be determined by selected error correcting code itself.The size of error correcting code coding redundancy amount has directly determined the error correction intensity of error correcting code coding module.
Flash memory management module 110c is electrically connected to microprocessing unit 110a by microprocessing unit described a plurality of flash chips are carried out the flash memory management program.Flash memory management module 110c is used for management flash memory 120, such as carrying out average abrasion (wear 1eve1ing) method, bad block management, safeguarding mapping table (mapping table) etc.Particularly, in embodiments of the present invention, flash memory management module 110c is also for detection of the operating position of flash memory 120, to control the current flash memory erase operation time.Implementation is as follows: detect the noise tolerance limit under the current worst condition of the page to be copied, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition; Detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If there is at least one described copy targeting page, then the data of the page to be copied are directly read and are copied in arbitrary described copy targeting page; If there is not the described copy targeting page, then first the data reading of the page to be copied to be processed to carry out error correcting code, the correct page data after will processing through error correcting code again copies in another available page.
In the specific implementation, the flash memory management module 110c of controller 110 is by before carrying out erase operation to arbitrary storage block 124, the program/erase number of times that the flash memory pages 126 of real-time each flash chip of detection record lives through, and estimate noise tolerance limit under the worst condition of flash memory pages 126 of each flash chip according to the program/erase number of times of record, and obtain the current maximal bit error rate of Hash memory pages 126 of each flash chip according to the noise tolerance limit under the described worst condition; In addition, before needs carry out erase operation to storage piece 124, need with in the flash memory pages 126 in this storage block 124 still active data (being page data to be copied) copy (the copy targeting page in the available page of other storage blocks to, be about to the page that page data to be copied is copied to), when selecting the copy targeting page, at first to obtain the noise tolerance limit under the current worst condition of the page to be copied, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition, detect simultaneously whether have at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance (error correcting capability that also can not exceed error correcting code after namely the bit error rate of two pages directly adds up); Like this, if fruit is found to have at least one described copy targeting page, then the data of the page to be copied are directly read and copied in arbitrary described copy targeting page, need not to process through error correcting code; If there is not the described copy targeting page in fruit, then utilizing error correcting code coding module 110d to carry out error correcting code in the controller of flash memory system the data reading of the page to be copied first processes, to correct all error bits, then correct page data is copied in the page available in another storage block.
In order further to set forth the effect of the embodiment of the invention, prior art and essential distinction of the present invention are described in now contrast.Fig. 3 ~ 4th, prior art compares synoptic diagram with the operational process that the flash-memory storage system that utilizes in the embodiment of the invention 1 is realized.As shown in Figure 3, in the prior art, in existing solid-state memory system design, with a certain page (page to be copied) data copy during to another memory page (the copy targeting page), at first be to utilize the conversion layer firmware first this page data to be copied to be read (first step), then the transmits page data are to solid-state data storage system controller interior (second step), in controller, utilize error correction code module that these data are carried out error correction decode and operate to obtain right-on raw data (the 3rd step), again this right-on original data transmissions backflash is deposited at last (the 4th step) and write (the 5th step) in the copy targeting page.Although this mode of operation can at utmost improve the reliability of data storage, can take simultaneously valuable system bus resource and error-correcting code decoder resource, and then reduce the travelling speed of data-storage system integral body.。And use when of the present invention, as shown in Figure 4, with a certain page (page to be copied) data copy during to another memory page (the copy targeting page), if the bit error rate of the page to be copied is enough low, so that there is another free Page (the copy targeting page), so that the bit error rate of these two pages also can not exceed the error correcting capability of error correcting code after directly cumulative, then can directly read page data to be copied (first step), then transmit page data to be copied (second step) and write (the 3rd step) in the copy targeting page.Obviously, under the prerequisite that does not reduce storage system stability, can directly reduce taking and then reduce conversion layer firmware when operation to the impact of solid-state memory system travelling speed system resource.
The solid-state memory system controller only uses an error correcting code coded system of fixing and write onesize user data in each flash memory physical page, and all flash memory pages writing speeds are set as a fixed value simultaneously.In service at real system, different user data can have very different lossless data compression, when use is of the present invention, data-storage system can utilize this lossless data compression in real time, improve as much as possible data storage error correcting code ground error correcting capability, and then utilize more formidably error correcting capability to allow more highland flash memory chip data writing speed, to reach the purpose that improves the solid-state memory system travelling speed.
In addition, though be not illustrated in present embodiment, controller 110 can comprise also that general flash controller is normal
The functional module of seeing is such as power management module etc.
In the embodiment of the invention, flash memory management module 110c is set in the controller 110 of flash-memory storage system 100, and this flash memory management module 110c has set up arbitrary storage block has been carried out before the erase operation and need to be with the data copy of the page to be copied in the copy targeting page, at first detect the noise tolerance limit under the current worst condition of the page to be copied, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition, and detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If there is at least one described copy targeting page, then the data of the page to be copied are directly read and are copied in arbitrary described copy targeting page; If there is not the described copy targeting page, then first the data reading of the page to be copied to be processed to carry out error correcting code, the correct page data after will processing through error correcting code again copies in another available page.Namely be, use when of the present invention, if the bit error rate of the page to be copied is enough low, make and have another free Page in the flash memory, so that the bit error rate of this two page also can not exceed the error correcting capability of error correcting code after directly cumulative, then directly page data to be copied is copied so far free Page, obviously, under the prerequisite that does not reduce storage system stability, can directly reduce taking and then reduce conversion layer firmware when operation to the impact of solid-state memory system travelling speed system resource.Therefore, when the operating characteristic that effectively utilizes flash memory chip storage unit reduces the operation of conversion layer firmware on the impact of solid-state memory system travelling speed, reach the purpose that improves flash chip internal data copying speed, and design of the present invention and the design of existing solid-state memory system are directly compatible, and implementation procedure is simple.
Embodiment 2
The embodiment of the invention provides a kind of controller, be applicable to have on the flash-memory storage system of flash memory, wherein, this flash memory comprises a plurality of flash chips, each flash chip has a plurality of storage blocks, and be provided with a plurality of pages in each storage block, please refer to the associated description of Fig. 2 and above-described embodiment about the concrete structure of flash chip.As shown in Figure 5, the controller 300 of the embodiment of the invention comprises microprocessing unit 310, flash interface 320, flash memory management module 330 and error correcting code coding module 340.
Flash interface 320 is electrically connected to microprocessing unit 310 and in order to the access flash memory, namely, the user data that the controller wish will write to flash memory can be converted to 120 receptible forms of flash memory via flash interface 320.Particularly, in this enforcement, the acquisition of information of 330 pairs of flash memories of flash memory management module and transmission control command etc. also is to need to send by flash interface 320.
Error correcting code coding module 340 is electrically connected to microprocessing unit 310 and is used for the user data of wanting to write is carried out the error correcting code coding, thereby produce corresponding error correcting code coding redundancy and therewith data together be stored in the same flash memory pages of flash chip, wherein afterwards when from flash memory pages, reading these data, error correcting code coding module 340 can check whether data are correct according to the error correcting code coding redundancy, perhaps attempts the data of mistake are reverted to correct data when data are incorrect.The error correcting code coding redundancy is to be determined by selected error correcting code itself.The size of error correcting code coding redundancy amount has directly determined the error correction intensity of error correcting code coding module.
Flash memory management module 330 is electrically connected to microprocessing unit 310.Flash memory management module 330 is used for the management flash memory, particularly, in embodiments of the present invention, flash memory management module 330 is also for detection of the operating position of flash memory, to control current flash memory erase operation and data copy operation, specifically comprise program/erase number of times record cell 332, noise tolerance limit evaluation unit 334, page data storage errors rate evaluation unit 336 and copy targeting page selected cell 338:
Program/erase number of times record cell 332 is used for the program/erase number of times that each page lives through in the real time record flash memory;
Noise tolerance limit evaluation unit 334 is for the noise tolerance limit of estimating according to the program/erase number of times of record under each worst condition of depositing the page;
Page data storage errors rate evaluation unit 336 is used for estimating the maximal bit error rate that each page is current according to the noise tolerance limit under the worst condition of described noise tolerance limit evaluation unit estimation;
Copy targeting page selected cell 338, for detection of whether there being at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If exist, then send order in arbitrary described copy targeting page is directly read and copied to the data of the page to be copied; Otherwise order is processed the data reading of the page to be copied first to carry out error correcting code, and the correct page data after will processing through error correcting code again copies in another available page.In the specific implementation, the flash memory management module 330 of controller 300 is by before carrying out erase operation to arbitrary storage block 124, the program/erase number of times that flash memory pages by program/erase number of times record cell 332 real-time each flash chip of detection record lives through, and utilize noise tolerance limit evaluation unit 334 to estimate noise tolerance limit under the worst condition of flash memory pages of each flash chip according to the program/erase number of times of record, and utilize page data storage errors rate evaluation unit 336 to obtain the current maximal bit error rate of flash memory pages of each flash chip according to the noise tolerance limit under the described worst condition; In addition, before needs carry out erase operation to the storage piece, need with in the flash memory pages in this storage block still active data (being page data to be copied) copy (the copy targeting page in the available page of other storage blocks to, be about to the page that page data to be copied is copied to), when selecting the copy targeting page, at first described copy targeting page selected cell 338 obtains the current maximal bit error rate of the described page to be copied by page data storage errors rate evaluation unit 336, and detect in all flash chips whether have at least one available copy targeting page by page data storage errors rate evaluation unit 336 simultaneously, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance (error correcting capability that also can not exceed error correcting code after namely the bit error rate of two pages directly adds up); Like this, if find there is at least one described copy targeting page in fruit, then sends order in arbitrary described copy targeting page is directly read and copied to the data of the page to be copied, need not to process through error correcting code; If there is not the described copy targeting page in fruit, then order utilizes the error correcting code coding module to carry out the error correcting code processing in the controller of flash memory system the data reading of the page to be copied first, to correct all error bits, then correct page data is copied in the page available in another storage block.
In the embodiment of the invention, the flash memory management module is set in controller, and this flash memory management module has been set up arbitrary storage block has been carried out before the erase operation and need to be with the data copy of the page to be copied in the copy targeting page, at first detect the noise tolerance limit under the current worst condition of the page to be copied, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition, and detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If there is at least one described copy targeting page, then the data of the page to be copied are directly read and are copied in arbitrary described copy targeting page; If there is not the described copy targeting page, then first the data reading of the page to be copied to be processed to carry out error correcting code, the correct page data after will processing through error correcting code again copies in another available page.Namely be, use when of the present invention, if the bit error rate of the page to be copied is enough low, make and have another free Page in the flash memory, so that the bit error rate of this two page also can not exceed the error correcting capability of error correcting code after directly cumulative, then directly page data to be copied is copied so far free Page, obviously, under the prerequisite that does not reduce storage system stability, can directly reduce taking and then reduce conversion layer firmware when operation to the impact of solid-state memory system travelling speed system resource.Therefore, when the operating characteristic that effectively utilizes flash memory chip storage unit reduces the operation of conversion layer firmware on the impact of solid-state memory system travelling speed, reach the purpose that improves flash chip internal data copying speed, and design of the present invention and the design of existing solid-state memory system are directly compatible, and implementation procedure is simple.
Embodiment 3
The embodiment of the invention provides a kind of method that improves flash chip internal data copying speed, be applicable in the control of controller to flash memory of flash-memory storage system, wherein, this flash memory comprises a plurality of flash chips, each flash chip has a plurality of storage blocks, and be provided with a plurality of pages in each storage block, please refer to the associated description of Fig. 2 and above-described embodiment about the concrete structure of flash chip.As shown in Figure 6, the method comprises:
Step S101: detect the noise tolerance limit under the current worst condition of the page to be copied, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition;
Concrete, in the present embodiment, can detect by multiple existing mode the noise tolerance limit of flash memory chip storage unit, for example the data by the detection of stored unit read the bit error rate to detect the noise tolerance limit, to pass through the program/erase operations number of times of record flash information storage unit to detect the noise tolerance limit.
Step S102: detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If then the data of the page to be copied are directly read and are copied in arbitrary described copy targeting page.
Concrete, when selecting the copy targeting page, at first obtain noise tolerance limit under the current worst condition of the page to be copied by step 101, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition, then detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance (error correcting capability that also can not exceed error correcting code after namely the bit error rate of two pages directly adds up); Like this, if fruit is found to have at least one described copy targeting page, then the data of the page to be copied are directly read and copied in arbitrary described copy targeting page, need not to process through error correcting code.Obviously, under the prerequisite that does not reduce storage system stability, can directly reduce taking and then reduce conversion layer firmware when operation to the impact of solid-state memory system travelling speed system resource.
Fig. 6 is the process flow diagram according to the method for the raising flash chip internal data copying speed shown in the embodiment of the invention, and wherein these steps are that the mechanical order that the microprocessor of the controller of flash-memory storage system is carried out the flash memory management module is finished.It must be appreciated, the method step of raising flash chip internal data copying speed proposed by the invention is not limited to execution sequence shown in Figure 6, and those skilled in the art can change arbitrarily the method step that improves flash chip internal data copying speed according to spirit of the present invention.
Embodiment 4
The embodiment of the invention provides the another kind of method that improves flash chip internal data copying speed, be applicable in the control of controller to flash memory of flash-memory storage system, wherein, this flash memory comprises a plurality of flash chips, each flash chip has a plurality of storage blocks, and be provided with a plurality of pages in each storage block, please refer to the associated description of Fig. 2 and above-described embodiment about the concrete structure of flash chip.As shown in Figure 7, the method comprises:
Step S201: the real-time program/erase number of times that lives through of the flash memory pages of each flash chip of detection record, and estimate noise tolerance limit under the worst condition of flash memory pages of each flash chip according to the program/erase number of times of record;
Step S202: the current maximal bit error rate of flash memory pages of estimating each flash chip according to the noise tolerance limit under the described worst condition;
Step S203: detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance;
Concrete, before arbitrary storage block is carried out erase operation, need with in the flash memory pages in this storage block still active data (being page data to be copied) copy (the copy targeting page in the available page of other storage blocks to, be about to the page that page data to be copied is copied to), when selecting the copy targeting page, at first obtain the current maximal bit error rate of the described page to be copied, and detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance (error correcting capability that also can not exceed error correcting code after namely the bit error rate of two pages directly adds up).In addition, the error correction tolerance limit of error correcting code is set by the error correction module of controller, error correction module be used for to the data of wanting to write produce one group of error correcting code and therewith data together be stored to flash memory, when from flash memory, reading these data, can check whether data are correct according to error correcting code wherein, perhaps when data are incorrect, attempt the data of mistake are reverted to correct data, according to the error correction intensity of employed error correcting code, also can not exceed the error correcting capability of error correcting code after the bit error rate of judging the page to be copied and two pages of the copy targeting page is directly cumulative.And notice that the copy page belongs to different storage blocks with the copy targeting page.
Step S204: if there is at least one described copy targeting page, then the data of the page to be copied are directly read and copied in arbitrary described copy targeting page;
Step S205: if there is not the described copy targeting page, then first the data reading of the page to be copied is processed to carry out error correcting code, the correct page data after will processing through error correcting code again copies in the available page of another storage block.
Fig. 7 is the process flow diagram according to the method for the raising flash chip internal data copying speed shown in the embodiment of the invention, and wherein these steps are that the mechanical order that the microprocessor of the controller of flash-memory storage system is carried out the flash memory management module is finished.It must be appreciated, the method step of raising flash chip internal data copying speed proposed by the invention is not limited to execution sequence shown in Figure 7, and those skilled in the art can change arbitrarily the method step that improves flash chip internal data copying speed according to spirit of the present invention.
One of ordinary skill in the art will appreciate that all or part of flow process that realizes in above-described embodiment method, to realize by the mode that software adds necessary common hardware, can certainly finish by hardware, but the former is better embodiment in a lot of situation.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product is stored in the storage medium that can read, floppy disk, hard disk or CD etc. such as computing machine, comprise that some instructions are with so that a computer equipment (can make personal computer, server, perhaps network equipment etc.) carry out the described method of elder brother embodiment of the present invention.
The above is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also are considered as protection scope of the present invention.
Claims (10)
1. method that improves flash chip internal data copying speed, wherein each flash chip has a plurality of storage blocks, and each storage block comprises a plurality of pages, it is characterized in that, and the method comprising the steps of:
Detect the noise tolerance limit under the current worst condition of the page to be copied, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition;
Detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If then the data of the page to be copied are directly read and are copied in arbitrary described copy targeting page.
2. the method for raising flash chip internal data copying speed as claimed in claim 1 is characterized in that, also comprises step:
If there is not the described copy targeting page, then first the data reading of the page to be copied to be processed to carry out error correcting code, the correct page data after will processing through error correcting code again copies in another available page.
3. the method for raising flash chip internal data copying speed as claimed in claim 1 is characterized in that, the program/erase number of times that lives through by each page in the real time record flash memory is estimated the noise tolerance limit under the worst condition of each page.
4. such as the method for each described raising flash chip internal data copying speed in the claim 1 ~ 3, it is characterized in that the described copy targeting page and the page to be copied do not belong to same storage block.
5. a controller is characterized in that, comprising:
Microprocessing unit;
Flash interface is coupled to described microprocessing unit and a plurality of flash chip, and wherein each flash chip has a plurality of storage blocks, and each storage block comprises a plurality of pages;
The flash memory management module, be coupled to described microprocessing unit by microprocessing unit described a plurality of flash chips are carried out the flash memory process program, comprise: detect the noise tolerance limit under the current worst condition of the page to be copied, and obtain the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition; Detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If there is at least one described copy targeting page, then the data of the page to be copied directly read and copied in arbitrary described copy targeting page.
6. controller as claimed in claim 5, it is characterized in that, described flash memory management module also comprises execution: if there is not the described copy targeting page, then first the data reading of the page to be copied is processed to carry out error correcting code, the correct page data after will processing through error correcting code again copies in another available page.
7. controller as claimed in claim 5 is characterized in that, described flash memory management module comprises:
Program/erase number of times record cell is used for the program/erase number of times that each page lives through in the real time record flash memory;
Noise tolerance limit evaluation unit is for the noise tolerance limit under the worst condition of estimating each page according to the program/erase number of times of record;
Page data storage errors rate evaluation unit is used for estimating the maximal bit error rate that each page is current according to the noise tolerance limit under the worst condition of described noise tolerance limit evaluation unit estimation;
Copy targeting page selected cell, for detection of whether there being at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If exist, then send order in arbitrary described copy targeting page is directly read and copied to the data of the page to be copied; Otherwise order is processed the data reading of the page to be copied first to carry out error correcting code, and the correct page data after will processing through error correcting code again copies in another available page.
8. such as each described controller of claim 5 ~ 7, it is characterized in that the described copy targeting page and the page to be copied do not belong to same storage block.
9. a flash-memory storage system is characterized in that, comprising:
A plurality of flash chips, each flash chip has a plurality of storage blocks, and each storage block comprises a plurality of storage unit;
Controller is coupled to described a plurality of flash chip detecting the noise tolerance limit under the current worst condition of the page to be copied, and obtains the current maximal bit error rate of the described page to be copied according to the noise tolerance limit under the described worst condition; Detect whether there is at least one available copy targeting page in all flash chips, making the bit error rate after the current maximal bit error rate of the current maximal bit error rate of the described copy targeting page and the page to be copied adds up can be employed error correcting code tolerance; If then the data of the page to be copied are directly read and are copied in arbitrary described copy targeting page.
10. flash-memory storage system as claimed in claim 9, it is characterized in that, described controller also comprises execution: if there is not the described copy targeting page, then first the data reading of the page to be copied is processed to carry out error correcting code, the correct page data after will processing through error correcting code again copies in another available page.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103944472A CN102915277A (en) | 2012-10-17 | 2012-10-17 | Method for improving copying speed of internal data of flash memory chips, flash memory storage system and controller of system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103944472A CN102915277A (en) | 2012-10-17 | 2012-10-17 | Method for improving copying speed of internal data of flash memory chips, flash memory storage system and controller of system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102915277A true CN102915277A (en) | 2013-02-06 |
Family
ID=47613650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103944472A Pending CN102915277A (en) | 2012-10-17 | 2012-10-17 | Method for improving copying speed of internal data of flash memory chips, flash memory storage system and controller of system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102915277A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106547491A (en) * | 2016-11-22 | 2017-03-29 | 郑州云海信息技术有限公司 | The method and system of data-moving in a kind of solid state hard disc |
| CN107015918A (en) * | 2017-03-31 | 2017-08-04 | 建荣半导体（深圳）有限公司 | A kind of flash management system, method and flash chip |
| CN117420963A (en) * | 2023-12-18 | 2024-01-19 | 合肥康芯威存储技术有限公司 | Memory and control method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101030167A (en) * | 2007-01-17 | 2007-09-05 | 忆正存储技术(深圳)有限公司 | Flash-memory zone block management |
| CN102298543A (en) * | 2011-09-15 | 2011-12-28 | 成都市华为赛门铁克科技有限公司 | Memory management method and memory management device |
| CN102323901A (en) * | 2011-07-28 | 2012-01-18 | 张岭 | A kind of method that improves solid-state memory system error correcting code service efficiency |
| CN102385553A (en) * | 2010-08-31 | 2012-03-21 | 点序科技股份有限公司 | Access device and access method for flash memory |
-
2012
- 2012-10-17 CN CN2012103944472A patent/CN102915277A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101030167A (en) * | 2007-01-17 | 2007-09-05 | 忆正存储技术(深圳)有限公司 | Flash-memory zone block management |
| CN102385553A (en) * | 2010-08-31 | 2012-03-21 | 点序科技股份有限公司 | Access device and access method for flash memory |
| CN102323901A (en) * | 2011-07-28 | 2012-01-18 | 张岭 | A kind of method that improves solid-state memory system error correcting code service efficiency |
| CN102298543A (en) * | 2011-09-15 | 2011-12-28 | 成都市华为赛门铁克科技有限公司 | Memory management method and memory management device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106547491A (en) * | 2016-11-22 | 2017-03-29 | 郑州云海信息技术有限公司 | The method and system of data-moving in a kind of solid state hard disc |
| CN107015918A (en) * | 2017-03-31 | 2017-08-04 | 建荣半导体（深圳）有限公司 | A kind of flash management system, method and flash chip |
| CN107015918B (en) * | 2017-03-31 | 2019-11-05 | 建荣半导体（深圳）有限公司 | A kind of flash management system, method and flash chip |
| CN117420963A (en) * | 2023-12-18 | 2024-01-19 | 合肥康芯威存储技术有限公司 | Memory and control method thereof |
| CN117420963B (en) * | 2023-12-18 | 2024-02-23 | 合肥康芯威存储技术有限公司 | Memory and control method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10169143B2 (en) | Preferred state encoding in non-volatile memories | |
| US10102059B2 (en) | Data storage device capable of preventing a data retention fail of a nonvolatile memory device and operating method thereof | |
| US8650463B2 (en) | Solid state drive and method of controlling an error thereof | |
| US10249383B2 (en) | Data storage device and operating method thereof | |
| TWI527037B (en) | Data storing method, memory control circuit unit and memory storage apparatus | |
| JP5686516B2 (en) | Programming management data for NAND memory | |
| US9229851B2 (en) | Memory controller, semiconductor memory device and control method thereof | |
| US8984253B2 (en) | Transaction log recovery | |
| US9678827B2 (en) | Access counts for performing data inspection operations in data storage device | |
| US9240235B2 (en) | Mitigating disturb effects for non-volatile memory | |
| US20160350179A1 (en) | Decoding method, memory storage device and memory control circuit unit | |
| US10503433B2 (en) | Memory management method, memory control circuit unit and memory storage device | |
| WO2021026036A1 (en) | Read disturb scan consolidation | |
| US20160179596A1 (en) | Operating method of data storage device | |
| CN102915770B (en) | Method for reducing inter-crosstalk of internal data of flash memory chip, flash memory storage system and controller thereof | |
| US11836392B2 (en) | Relocating data to low latency memory | |
| TW202338851A (en) | Method of sudden power off recovery, memory controlling circuit unit and memory storage device | |
| CN102880554A (en) | Flash-memory storage system and controller thereof and method for improving storage efficiency of flash memory chips | |
| US20210019086A1 (en) | Memory controller, memory device, memory system, and operating method thereof | |
| CN102880432B (en) | Method and system for increasing writing speeds of flash memory chips by aid of limited lives of data and controller of system | |
| US11216334B1 (en) | Data reading method, memory storage device and memory control circuit unit | |
| CN102915277A (en) | Method for improving copying speed of internal data of flash memory chips, flash memory storage system and controller of system | |
| CN114822664A (en) | Risk assessment method based on data priority, storage device and control circuit | |
| CN106980464B (en) | System optimization method using oversampled reads | |
| CN113434331B (en) | Cross-frame code management method, memory storage device and memory control circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130206 |