CN102903686B

CN102903686B - TSV (through silicon via) three-dimensional integration interconnection structure based on SOI (silicon on insulator)

Info

Publication number: CN102903686B
Application number: CN201210371907.XA
Authority: CN
Inventors: 单光宝; 孙有民; 刘松; 蔚婷婷; 李翔
Original assignee: 771 Research Institute of 9th Academy of CASC
Current assignee: 771 Research Institute Of Ninth Research Institute Of China Aerospace Science And Technology Corp Co ltd; Zhuhai Tiancheng Advanced Semiconductor Technology Co ltd
Priority date: 2012-09-29
Filing date: 2012-09-29
Publication date: 2015-04-08
Anticipated expiration: 2032-09-29
Also published as: CN102903686A

Abstract

The invention discloses a TSV three-dimensional integration interconnection structure based on an SOI. The interconnection structure comprises a barrier layer, a side wall insulation layer, and a conductive filler, wherein a copper pillar is the conductive filler; the barrier layer and the side wall insulation layer sequentially wrap the outer wall of the copper pillar; the copper pillar penetrates through a top silicon layer, a buried oxide layer and substrate silicon of the SOI longitudinally to form the TSV; the TSV above the buried oxide layer has a diameter W1; the TSV below the buried oxide layer has a diameter W2 smaller than W1, and is coaxial with the TSV above the buried oxide layer. The interconnection structure provided by the invention not only can realize three-dimensional integration of the SOI-based process device and meet the process requirement for TSV three-dimensional integration of a hardened device and a high-voltage/low-leakage device, but also can reduce the influences of Notching effect on the subsequent side wall insulation process, thereby improving breakdown voltage, enhancing reliability of an SOI-based TSV three-dimensional integration device, saving chip area, and lowering development cost.

Description

The three-dimensional integrated interconnection structure of TSV based on SOI

Technical field

The present invention relates to microelectronics technology.

Background technology

The three-dimensional integrated interconnection structure of usual TSV all realizes on monocrystalline silicon wafer crystal, " ladder " the type structure that the KOH of employing anisotropic etch is formed more or " I " font structure (see Fig. 1) based on ICP dry etching.The major defect adopting above-mentioned interconnection structure to exist has:

(1) above-mentioned interconnect architecture all realizes on monocrystalline silicon wafer crystal, and etachable material is silicon, cannot meet soi structure Si/SiO2/Si material etching.

(2) in KOH anisotropic etch due to the existence of (111) crystal face and the intrinsic angle of (100) crystal face, so TSV through hole opening can become large along with corrosion depth and increase, make such " ladder " type structure TSV through hole area occupied excessive, economical difference, and this technique uses KOH easily to introduce K+ pollution as attached liquid, K+ can be caused to pollute to CMOS technology line.

(3) write in " Via First Approach Optimisation for Through Silicon Via Applications(ECTC2009.59th) " document: bury oxygen medium layer owing to existing in soi structure, so easily form charge accumulated at Si and oxygen buried layer interface, in Si/SiO2 interface, ion direction can deflect and to corrode in sidewall, forms " Notching " structure (see Fig. 2).Due to the existence of " Notching " structure, according to above-mentioned interconnection structure, the follow-up insulation of through-hole side wall, barrier/seed layers make, via metal is undertaken being difficult to, and can cause electric leakage increase, withstand voltage reduction, affect the three-dimensional integrated device Performance And Reliability of SOI.

Summary of the invention

Existing TSV interconnection structure cannot meet the many material etchings of SOI technology, high interconnection density, and affect lateral wall insulation characteristic and device performance and less economical deficiency, the present invention proposes a kind of novel three-dimensional integrated interconnection structure of TSV that can be used for SOI technology, the process devices solid that this structure not only can realize based on SOI is integrated, meet radiation hardened device, the process requirements that high pressure/Low dark curient device TSV is three-dimensional integrated, and reduce the impact of " Notching " effect on follow-up lateral wall insulation technique, promote puncture voltage, increase the three-dimensional integrated device reliability of TSV based on SOI, save chip area, reduce development cost.

The technical solution adopted for the present invention to solve the technical problems is: the three-dimensional integrated interconnection structure of a kind of TSV based on SOI, comprise barrier layer, side wall insulating layer and conductive filler, with copper post for conductive filler, at copper column outer wall coated successively barrier layer and side wall insulating layer, copper post has longitudinally run through SOI top layer silicon, oxygen buried layer and substrate silicon, form TSV through hole, TSV through hole diameter above oxygen buried layer is W1, TSV through hole diameter W2 below oxygen buried layer, upper and lower TSV hole is coaxial, and the difference of W1>W2, W1 and W2 is 3 μm ~ 6 μm.

The invention has the beneficial effects as follows: the three-dimensional integrated interconnection structure of the TSV based on SOI that the present invention proposes can produce the TSV through hole interconnection of high density, high-aspect-ratio.Compared with conventional interconnect is all on monocrystalline silicon wafer crystal, this structure sidewall insulator layers, barrier layer, copper post have longitudinally run through SOI top layer silicon, oxygen buried layer and substrate silicon, realize the many material etchings of Si/SiO2/Si, meet SOI technology device solid integrated, the process requirements that radiation hardened device, high pressure/Low dark curient device TSV is three-dimensional integrated.

Compared with KOH wet etching, owing to there is not (111) crystal face and the intrinsic angle of (100) crystal face in anisotropic etch, via openings can not increase along with etching depth and become large, so " falling terraced " type structure saving chip area more of the structural rate KOH wet etching of the present invention's proposition, when via depth (50 μm ~ 100 μm) is identical, can saving chip area 94% ~ 97%, have more economic benefit.

Because interconnection structure is in " T " font, namely above oxygen buried layer, through-hole diameter W1 is greater than through-hole diameter W2 below oxygen buried layer, so can leave etching surplus W3 and W4(see Fig. 3 on oxygen buried layer window level direction).When etching oxygen buried layer and below through hole thereof, even if there is situation about laterally inwardly corroding, due to the existence of lateral etching surplus, so " Notching " structure of top layer silicon/oxygen buried layer/silicon base interface also can not cave inward excessive.The size that top layer silicon/oxygen buried layer/silicon base interface etches in sidewall can be reduced to several microns thus, " Notching " structure that effective solution traditional SOI TSV interconnection structure etching produces is on the impact of follow-up lateral wall insulation, barrier/seed layers technique, reduce follow-up technology difficulty, promote puncture voltage, add the three-dimensional integrated device reliability of TSV based on SOI.

Accompanying drawing explanation

Fig. 1 is the traditional TSV interconnect architecture of based single crystal Silicon Wafer,

Wherein, (a) is " I " font structure, and (b) is " falling terraced " type structural representation;

1-monocrystalline substrate, 2-sidewall SiO ₂insulating barrier, 3-barrier layer Ta/TaN, 4-conductive filler Cu;

Fig. 2 is traditional TSV " I " type interconnection structure in SOI technology makes, " Notching " structural representation that oxygen buried layer interface is formed;

Wherein, 1-Si substrate, 2-top layer silicon, 3-oxygen buried layer, " Notching " structure;

Fig. 3 is that the present invention proposes " T " font TSV interconnection structure schematic diagram;

Wherein, 1-Si substrate, 2-sidewall SiO ₂insulating barrier, 3-barrier layer Ta/TaN, 4-conductive filler Cu, 5-oxygen buried layer, 6-top layer silicon.

Embodiment

Below in conjunction with drawings and Examples, the present invention is further described.

The present invention proposes the three-dimensional integrated interconnection structure of a kind of TSV based on SOI, the technical characteristic of this structure is that side wall insulating layer, barrier layer, copper post have longitudinally run through SOI top layer silicon, oxygen buried layer and substrate silicon.Above oxygen buried layer, TSV through hole diameter is W1, TSV through hole diameter W2 below oxygen buried layer, upper and lower TSV hole is coaxial, and W1>W2(is see Fig. 3), W3 and W4 size minimum value controls within the scope of 1.5 μm ~ 3 μm, and overall interconnect architecture is in " T " font structure.

Embodiment 1:

As shown in Figure 3, SOI wafer top layer silicon 3000 oxygen buried layer 2500 silicon base 80 μm.Top layer silicon window W1=8 μm, oxygen buried layer window W2=5 μm, oxygen buried layer etching surplus W3, W4 are respectively 1.5 μm, insulating barrier SiO2 thickness 0.6 μm, barrier layer Ta/TaN thickness is 0.4 μm, and center conductive filler is copper, and side wall insulating layer SiO2, barrier layer Ta/TaN, copper post have longitudinally run through SOI top layer silicon, oxygen buried layer and substrate silicon, via depth is 50 μm, and overall interconnect architecture is in " T " font structure.

Embodiment 2:

As shown in Figure 3, SOI wafer top layer silicon 3500 oxygen buried layer 3000 silicon base 80 μm.Top layer silicon window W1=15 μm, oxygen buried layer window W2=10 μm, oxygen buried layer etching surplus W3, W4 are respectively 2.5 μm, thickness of insulating layer 0.8 μm, barrier layer Ta/TaN thickness is 0.6 μm, and center conductive filler is copper, and side wall insulating layer SiO2, barrier layer Ta/TaN, copper post have longitudinally run through SOI top layer silicon, oxygen buried layer and substrate silicon, via depth is 70 μm, and overall interconnect architecture is in " T " font structure.

Embodiment 3:

As shown in Figure 3, SOI wafer top layer silicon 3500 oxygen buried layer 3000 silicon base 80 μm.Top layer silicon window W1=30 μm, oxygen buried layer window W2=24 μm, oxygen buried layer etching surplus W3, W4 are respectively 3 μm, thickness of insulating layer 1 μm, barrier layer Ta/TaN thickness is 0.8 μm, and center conductive filler is copper, and side wall insulating layer SiO2, barrier layer Ta/TaN, copper post have longitudinally run through SOI top layer silicon, oxygen buried layer and substrate silicon, via depth is 70 μm, and overall interconnect architecture is in " T " font structure.

Claims

1. the three-dimensional integrated interconnection structure of the TSV based on SOI, comprise barrier layer, side wall insulating layer and conductive filler, it is characterized in that: with copper post for conductive filler, at copper column outer wall coated successively barrier layer and side wall insulating layer, copper post has longitudinally run through SOI top layer silicon, oxygen buried layer and substrate silicon, form TSV through hole, TSV through hole diameter above oxygen buried layer is W1, TSV through hole diameter W2 below oxygen buried layer, upper and lower TSV hole is coaxial, and the difference of W1>W2, W1 and W2 is 3 μm ~ 6 μm; Oxygen buried layer window level direction can be left etching surplus W3 and W4.