CN102902296B - Not by the temperature-compensation circuit in the precision constant current source of process deviation influence - Google Patents
Not by the temperature-compensation circuit in the precision constant current source of process deviation influence Download PDFInfo
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- CN102902296B CN102902296B CN201210426500.2A CN201210426500A CN102902296B CN 102902296 B CN102902296 B CN 102902296B CN 201210426500 A CN201210426500 A CN 201210426500A CN 102902296 B CN102902296 B CN 102902296B
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Abstract
The present invention relates to a kind of not by the temperature-compensation circuit in the precision constant current source of process deviation influence, the technology which solved in the past is subject to process deviation influence to such an extent as to current source precision is low, the problem of poor stability.The present invention is rational in infrastructure, successful, and it is convenient to implement, and is beneficial to and applies.
Description
Technical field
The present invention is applied to Analogous Integrated Electronic Circuits in integrated circuit (IC) design and hydrid integrated circuit design field, especially be applied in and have in the chip design of very high-precision requirement to constant current source, such as, in the design of the chips such as multidigit high-precision ADC, DAC or loop power supply instrument in simulation or Mixed Design.
Background technology
In the industry of integrated circuit (IC) design, reference voltage source and reference current source are the key modules during Analogous Integrated Electronic Circuits and hydrid integrated circuit design all the time, be widely used in the circuit such as digital to analog converter, oscillator, amplifier, their precision directly can affect the performance of chip entirety.Especially, in the design of the high-precision ADC of multidigit and DAC chip, high requirement is had to the precision of reference current source.The reference current source of high precision, high stability supports high performance circuit, so design a High-accuracy reference current source have very important realistic meaning.Wherein the technique for temperature compensation of electric current is the gordian technique realizing high precise current source.
The domestic and international research to reference current source is fewer at present, does not also have ripe circuit structure can produce reference current source within 10ppm/ DEG C in report.The method of general generation reference current source converts voltage signal to current signal by a resistance on the basis of reference voltage, so the precision of resistance also directly affects the precision of constant current source.Resistance is an amount extremely responsive to flow-route and temperature, the design of most simulation or hybrid chip all can trim this direct resistance affecting precision, allow its precision reach a more accurate index, wanting to improve precision further then needs to introduce technique for temperature compensation.The method that conventional current source temperature compensates utilizes the positive and negative temperature coefficient of branch current to superpose simply to carry out two-stage temperature compensation, this temperature compensation needs the variable of introducing four compensating parameters, be difficult to control simultaneously, and being subject to the impact of process deviation, the current source temperature coefficient after compensation is accidentally desirable.But along with the develop rapidly of integrated circuit, simulation or the requirement of hybrid chip to precision more and more higher, study a kind of not by process deviation influence current temperature compensation technique can play critical effect to the development of industry.
Summary of the invention
Goal of the invention: the present invention relates to a kind of not by the temperature-compensation circuit in the precision constant current source of process deviation influence, its objective is that solution technology is in the past subject to process deviation influence to such an extent as to current source precision is low, the problem of poor stability.
Technical scheme: the present invention is achieved by the following technical solutions:
Not by the temperature-compensation circuit in the precision constant current source of process deviation influence, it is characterized in that: this circuit is made up of resitstance voltage divider and multiple transistor; Resitstance voltage divider is a termination 2.5V reference voltage of the first resistance R1, the second resistance R2 and the 3rd resistance R3, the R1 be cascaded, R3 other end ground connection; First PMOS transistor P1, nmos pass transistor N1 and the 4th resistance R4 produce a branch current, the source of PMOS transistor P1 meets power supply VCC, grid leak short circuit, connect the drain terminal of the first nmos pass transistor N1, the grid of the first nmos pass transistor N1 connect 2.5V reference voltage, the source of the first nmos pass transistor N1 connects one end of the 4th resistance R4, the 4th resistance R4 other end ground connection; Second PMOS transistor P2 and the first NPN transistor Q1 and the second NPN transistor Q2 forms a branch road, the source termination power VCC of the second PMOS transistor P2, grid connect the grid of the first PMOS transistor P1, the base stage of the first NPN transistor Q1 and collector short circuit connect the drain terminal of the second PMOS transistor P2, second NPN transistor Q2 base stage and collector short circuit connect the emitter of the first NPN transistor Q1, the grounded emitter of the second NPN transistor Q2, the drain terminal extraction voltage signal Vtemp of the second PMOS transistor P2; 3rd PMOS transistor P3 and the second nmos pass transistor N2 forms branch road, the source termination power VCC of the 3rd PMOS transistor P3, and grid connect the grid of the first PMOS transistor P1, and the second nmos pass transistor N2 grid leak short circuit connects the leakage of the 3rd PMOS transistor P3, source ground connection; The drain terminal extraction voltage signal VB of the 3rd PMOS transistor P3;
4th PMOS transistor P4, 5th PMOS transistor P5, 7th PMOS transistor P7, 8th PMOS transistor P8 and the 3rd nmos pass transistor N3, 4th nmos pass transistor N4, 5th nmos pass transistor N5 forms a comparer, 5th nmos pass transistor N5 provides tail current for differential pair, grid meet voltage VB, source ground, 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is the differential pair of comparer, the drain terminal of the 5th nmos pass transistor N5 is connect together with then 3rd nmos pass transistor N3 is connected together with the source of the 4th nmos pass transistor N4, the grid of the 3rd nmos pass transistor N3 meet 1.6V, the grid of the 4th nmos pass transistor N4 meet voltage signal Vtemp, the grid leak short circuit of load pipe the 7th PMOS transistor P7 connects the drain terminal of the 3rd nmos pass transistor N3, the grid of load pipe the 8th PMOS transistor P8 connect the grid of the 7th PMOS transistor P7, miss the leakage of the 4th nmos pass transistor N4, 4th PMOS transistor P4 grid leak short circuit connects the source of the 7th PMOS transistor P7, the source of the 4th PMOS transistor P4 meets power supply VCC, 5th PMOS transistor P5 grid leak short circuit connects the source of the 8th PMOS transistor P8, the source of the 5th PMOS transistor P5 meets power supply VCC,
9th PMOS transistor P9, the tenth PMOS transistor P10, the 12 PMOS transistor P12, the 13 PMOS transistor P13 and the 6th nmos pass transistor N6, the 7th nmos pass transistor N7, the 8th nmos pass transistor N8 form a comparer, 8th nmos pass transistor N8 provides tail current for differential pair, grid meet voltage VB, source ground, 6th nmos pass transistor N6, 7th nmos pass transistor N7 is the differential pair of comparer, the drain terminal of the 8th nmos pass transistor N8 is connect again after together with 6th nmos pass transistor N6 connects with the source of the 7th nmos pass transistor N7, the grid of the 6th nmos pass transistor N6 meet 1.0V, the grid of the 7th nmos pass transistor N7 meet Vtemp, the grid leak short circuit of load pipe the 12 PMOS transistor P12 connects the drain terminal of the 7th nmos pass transistor N7, the grid of load pipe the 13 PMOS transistor P13 connect the grid of the 12 PMOS transistor P12, the leakage missing the 6th nmos pass transistor N6 of the 13 PMOS transistor P13, 9th PMOS transistor P9 grid leak short circuit connects the source of the 12 PMOS transistor P12, the source of the 9th PMOS transistor P9 meets power supply VCC, tenth PMOS transistor P10 grid leak short circuit connects the source of the 13 PMOS transistor P13, the source of the tenth PMOS transistor P10 meets power supply VCC, the grid of the 6th PMOS transistor P6 connect the grid of the 5th PMOS transistor P5 in comparer (1), the source of the 6th PMOS transistor P6 meets power supply VCC, the grid of the 11 PMOS transistor P11 connect the grid of the tenth PMOS transistor P10 in comparer (2), the source of the 11 PMOS transistor P11 meets power supply VCC, and the drain terminal of the 6th PMOS transistor P6 and the 11 PMOS transistor P11 is connected together.
Advantage and effect: the invention provides a kind of not by the temperature-compensation circuit in the precision constant current source of process deviation influence, this compensating circuit is not by process deviation influence, avoid electric current directly by the problem of certain resistance with certain transistors influence, carry out current compensation in the low-temperature zone and high temperature section that originally to present parabolic shape constant current source temperature curve, make constant current source at the temperature coefficient of each process corner all within 8ppm/ DEG C.
Concrete advantage of the present invention is as follows:
(1) not by the impact of process deviation, the characteristic of offset current is not by the impact that the process deviation of resistance or transistor causes.
(2) circuit design method that proposes of the present invention is simple, can the person of being designed be applied to integrated circuit die easily and fit in the middle of the design of hybrid circuit.
accompanying drawing illustrates:
Fig. 1 is traditional current superposition temperature-compensation circuit
Fig. 2 is the temperature-compensation circuit be not subject in the precision constant current source of process deviation influence of invention
Fig. 3 is the constant-current source circuit figure using amplifier structure to produce.
embodiment:below in conjunction with accompanying drawing, the present invention is described further:
As shown in Figure 2, the invention provides a kind of not by the temperature-compensation circuit in the precision constant current source of process deviation influence, it is characterized in that: this circuit is made up of resitstance voltage divider and multiple transistor; Resitstance voltage divider is a termination 2.5V reference voltage of the first resistance R1, the second resistance R2 and the 3rd resistance R3, the R1 be cascaded, and R3 other end ground connection, produces 1.6V voltage between R1 and R2, produce 1.0V voltage between R2 and R3; First PMOS transistor P1, nmos pass transistor N1 and the 4th resistance R4 produce a branch current, the source of PMOS transistor P1 meets power supply VCC, grid leak short circuit, connect the drain terminal of the first nmos pass transistor N1, the grid of the first nmos pass transistor N1 connect 2.5V reference voltage, the source of the first nmos pass transistor N1 connects one end of the 4th resistance R4, the 4th resistance R4 other end ground connection; Second PMOS transistor P2 and the first NPN transistor Q1 and the second NPN transistor Q2 forms a branch road, the source termination power VCC of the second PMOS transistor P2, grid connect the grid of the first PMOS transistor P1, the base stage of the first NPN transistor Q1 and collector short circuit connect the drain terminal of the second PMOS transistor P2, second NPN transistor Q2 base stage and collector short circuit connect the emitter of the first NPN transistor Q1, the grounded emitter of the second NPN transistor Q2, the drain terminal extraction voltage signal Vtemp of the second PMOS transistor P2; 3rd PMOS transistor P3 and the second nmos pass transistor N2 forms branch road, the source termination power VCC of the 3rd PMOS transistor P3, and grid connect the grid of the first PMOS transistor P1, and the second nmos pass transistor N2 grid leak short circuit connects the leakage of the 3rd PMOS transistor P3, source ground connection; The drain terminal extraction voltage signal VB of the 3rd PMOS transistor P3;
4th PMOS transistor P4, 5th PMOS transistor P5, 7th PMOS transistor P7, 8th PMOS transistor P8 and the 3rd nmos pass transistor N3, 4th nmos pass transistor N4, 5th nmos pass transistor N5 forms a comparer 1, 5th nmos pass transistor N5 provides tail current for differential pair, grid meet voltage VB, source ground, 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is the differential pair of comparer, the drain terminal of the 5th nmos pass transistor N5 is connect together with then 3rd nmos pass transistor N3 is connected together with the source of the 4th nmos pass transistor N4, the grid of the 3rd nmos pass transistor N3 meet 1.6V, the grid of the 4th nmos pass transistor N4 meet Vtemp, the grid leak short circuit of load pipe the 7th PMOS transistor P7 connects the drain terminal of the 3rd nmos pass transistor N3, the grid of load pipe the 8th PMOS transistor P8 connect the grid of the 7th PMOS transistor P7, miss the leakage of the 4th nmos pass transistor N4, 4th PMOS transistor P4 grid leak short circuit connects the source of the 7th PMOS transistor P7, the source of the 4th PMOS transistor P4 meets power supply VCC, 5th PMOS transistor P5 grid leak short circuit connects the source of the 8th PMOS transistor P8, the source of the 5th PMOS transistor P5 meets power supply VCC,
9th PMOS transistor P9, the tenth PMOS transistor P10, the 12 PMOS transistor P12, the 13 PMOS transistor P13 and the 6th nmos pass transistor N6, the 7th nmos pass transistor N7, the 8th nmos pass transistor N8 form a comparer 2,8th nmos pass transistor N8 provides tail current for differential pair, grid meet voltage VB, source ground, 6th nmos pass transistor N6, 7th nmos pass transistor N7 is the differential pair of comparer, the drain terminal of the 8th nmos pass transistor N8 is connect again after together with 6th nmos pass transistor N6 connects with the source of the 7th nmos pass transistor N7, the grid of the 6th nmos pass transistor N6 meet 1.0V, the grid of the 7th nmos pass transistor N7 meet Vtemp, the grid leak short circuit of load pipe the 12 PMOS transistor P12 connects the drain terminal of the 7th nmos pass transistor N7, the grid of load pipe the 13 PMOS transistor P13 connect the grid of the 12 PMOS transistor P12, the leakage missing the 6th nmos pass transistor N6 of the 13 PMOS transistor P13, 9th PMOS transistor P9 grid leak short circuit connects the source of the 12 PMOS transistor P12, the source of the 9th PMOS transistor P9 meets power supply VCC, tenth PMOS transistor P10 grid leak short circuit connects the source of the 13 PMOS transistor P13, the source of the tenth PMOS transistor P10 meets power supply VCC, the grid of the 6th PMOS transistor P6 connect the grid of the 5th PMOS transistor P5 in comparer 1, the source of the 6th PMOS transistor P6 meets power supply VCC, the grid of the 11 PMOS transistor P11 connect the grid of the tenth PMOS transistor P10 in comparer 2, the source of the 11 PMOS transistor P11 meets power supply VCC, and the drain terminal of the 6th PMOS transistor P6 and the 11 PMOS transistor P11 is connected together.
Fig. 2 is of the present invention not by the particular circuit configurations of temperature-compensation circuit in the precision constant current source of process deviation influence, and overall thought utilizes the temperature coefficient of PN junction forward junction pressure drop to propose a kind of Segmented temperature compensation technology avoiding process deviation influence by the relation property of load current and differential pair positive and negative terminal voltage difference in the characteristic of process deviation influence and amplifier hardly.Changed by the voltage difference variation with temperature of comparer differential pair positive and negative terminal, cause the electric current distribution condition generation significant change in two-way load pipe, by varying with temperature the contrary two-way electric current of trend in two comparers by superposing after mirror image, define the temperature-compensated current under total temperature.
As shown in Figure 2, circuit of the present invention comprises resistor voltage divider circuit, and 2.5V reference voltage source produces 1.6V and 1.0V voltage through the first resistance R1, the second resistance R2, the 3rd resistance R3; Comprise the current source be made up of the first PMOS transistor P1, the first nmos pass transistor N1, the 4th resistance R4, the first nmos pass transistor N1 is as amplifier tube, and grid connects 2.5V reference voltage, and the first PMOS transistor P1 does load pipe; The subcircuits of the second PMOS transistor P2, the first NPN transistor Q1 and the second NPN transistor Q2 composition is got by the grid of the second PMOS transistor P2 and the grid of the first PMOS transistor P1 mirror image that is connected together, this branch road two PN junctions superposition generations voltage signal Vtemp; The branch road that 3rd PMOS transistor P3 and the second nmos pass transistor N2 forms, its circuit is got by the 3rd PMOS transistor P3 grid and the first PMOS transistor P1 grid mirror image that is connected together, and this branch road produces a bias voltage VB by the grid leak short circuit of the second nmos pass transistor N2; 4th PMOS transistor P4, the 5th PMOS transistor P5, the 7th PMOS transistor P7, the 8th PMOS transistor P8, the 3rd nmos pass transistor N3, the 4th nmos pass transistor N4 and the 5th nmos pass transistor N5 form comparer, the positive termination voltage Vtemp of differential pair, negative termination voltage 1.6V, for difference branch road provides the gate voltage of the 5th nmos pass transistor N5 of electric current to be provided by bias voltage VB, the 4th PMOS transistor P4, the 5th PMOS transistor P5, the 7th PMOS transistor P7, the 8th PMOS transistor P8 are load pipes; 9th PMOS transistor P9, the tenth PMOS transistor P10, the 12 PMOS transistor P12, the 13 PMOS transistor P13, the 6th nmos pass transistor N6, the 7th nmos pass transistor N7 form and previous mutually isostructural comparer with the 8th nmos pass transistor N8, the positive termination voltage 1.0V of differential pair, negative termination voltage Vtemp; Electric current I 5 through the 6th PMOS transistor P6 is come by the 5th PMOS transistor P5 mirror image, and the electric current I 6 through the 11 PMOS transistor P11 is come by the tenth PMOS transistor P10 mirror image, offset current I
obe the equal of just two comparers two branch currents superposition produce.
The size of offset current carrys out size and the ratio of regulating resistance R1, R2, R3 according to actual needs in actual applications, thus the input voltage being connected to two comparer differential pairs is changed, and then its load current distribution condition can change.A practical application is the offset current I that Fig. 2 produces
oend is connected to the drain terminal of the first PMOS in Fig. 3, for constant current source provides temperature-compensated current.
The present invention is rational in infrastructure, successful, and it is convenient to implement, and is beneficial to and applies.
Claims (1)
1., not by the temperature-compensation circuit in the precision constant current source of process deviation influence, it is characterized in that: this circuit is made up of resitstance voltage divider and multiple transistor; Resitstance voltage divider is a termination 2.5V reference voltage of the first resistance R1, the second resistance R2 and the 3rd resistance R3, the R1 be cascaded, R3 other end ground connection; First PMOS transistor P1, nmos pass transistor N1 and the 4th resistance R4 produce a branch current, the source termination power VCC of the first PMOS transistor P1, grid leak short circuit, connect the drain terminal of the first nmos pass transistor N1, the grid termination 2.5V reference voltage of the first nmos pass transistor N1, the source of the first nmos pass transistor N1 connects one end of the 4th resistance R4, the 4th resistance R4 other end ground connection; Second PMOS transistor P2 and the first NPN transistor Q1 and the second NPN transistor Q2 forms a branch road, the source termination power VCC of the second PMOS transistor P2, the grid of grid termination first PMOS transistor P1, the base stage of the first NPN transistor Q1 and collector short circuit connect the drain terminal of the second PMOS transistor P2, second NPN transistor Q2 base stage and collector short circuit connect the emitter of the first NPN transistor Q1, the grounded emitter of the second NPN transistor Q2, the drain terminal extraction voltage signal Vtemp of the second PMOS transistor P2; 3rd PMOS transistor P3 and the second nmos pass transistor N2 forms branch road, the source termination power VCC of the 3rd PMOS transistor P3, the grid of grid termination first PMOS transistor P1, and the second nmos pass transistor N2 grid leak short circuit connects the leakage of the 3rd PMOS transistor P3, source ground connection; The drain terminal extraction voltage signal VB of the 3rd PMOS transistor P3;
4th PMOS transistor P4, 5th PMOS transistor P5, 7th PMOS transistor P7, 8th PMOS transistor P8 and the 3rd nmos pass transistor N3, 4th nmos pass transistor N4, 5th nmos pass transistor N5 forms a comparer, 5th nmos pass transistor N5 provides tail current for differential pair, grid termination voltage VB, source ground, 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is the differential pair of comparer, the drain terminal of the 5th nmos pass transistor N5 is connect together with then 3rd nmos pass transistor N3 is connected together with the source of the 4th nmos pass transistor N4, the grid termination 1.6V of the 3rd nmos pass transistor N3, the grid termination voltage signal Vtemp of the 4th nmos pass transistor N4, the grid leak short circuit of load pipe the 7th PMOS transistor P7 connects the drain terminal of the 3rd nmos pass transistor N3, the grid of grid termination the 7th PMOS transistor P7 of load pipe the 8th PMOS transistor P8, drain terminal connects the leakage of the 4th nmos pass transistor N4, 4th PMOS transistor P4 grid leak short circuit connects the source of the 7th PMOS transistor P7, the source termination power VCC of the 4th PMOS transistor P4, 5th PMOS transistor P5 grid leak short circuit connects the source of the 8th PMOS transistor P8, the source termination power VCC of the 5th PMOS transistor P5,
9th PMOS transistor P9, the tenth PMOS transistor P10, the 12 PMOS transistor P12, the 13 PMOS transistor P13 and the 6th nmos pass transistor N6, the 7th nmos pass transistor N7, the 8th nmos pass transistor N8 form a comparer, 8th nmos pass transistor N8 provides tail current for differential pair, grid termination voltage VB, source ground, 6th nmos pass transistor N6, 7th nmos pass transistor N7 is the differential pair of comparer, the drain terminal of the 8th nmos pass transistor N8 is connect again after together with 6th nmos pass transistor N6 connects with the source of the 7th nmos pass transistor N7, the grid termination 1.0V of the 6th nmos pass transistor N6, the grid termination Vtemp of the 7th nmos pass transistor N7, the grid leak short circuit of load pipe the 12 PMOS transistor P12 connects the drain terminal of the 7th nmos pass transistor N7, the grid of grid termination the 12 PMOS transistor P12 of load pipe the 13 PMOS transistor P13, the drain terminal of the 13 PMOS transistor P13 connects the leakage of the 6th nmos pass transistor N6, 9th PMOS transistor P9 grid leak short circuit connects the source of the 12 PMOS transistor P12, the source termination power VCC of the 9th PMOS transistor P9, tenth PMOS transistor P10 grid leak short circuit connects the source of the 13 PMOS transistor P13, the source termination power VCC of the tenth PMOS transistor P10, the grid of the 5th PMOS transistor P5 in the grid termination comparer 1 of the 6th PMOS transistor P6, the source termination power VCC of the 6th PMOS transistor P6, the grid of the tenth PMOS transistor P10 in the grid termination comparer 2 of the 11 PMOS transistor P11, the source termination power VCC of the 11 PMOS transistor P11, the drain terminal of the 6th PMOS transistor P6 and the 11 PMOS transistor P11 is connected together.
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| CN201210426500.2A CN102902296B (en) | 2012-10-31 | 2012-10-31 | Not by the temperature-compensation circuit in the precision constant current source of process deviation influence |
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| CN102902296B true CN102902296B (en) | 2015-10-28 |
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| CN104199503B (en) * | 2014-09-06 | 2016-09-21 | 辛晓宁 | A kind of temperature-compensation circuit |
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| US5430395A (en) * | 1992-03-02 | 1995-07-04 | Texas Instruments Incorporated | Temperature compensated constant-voltage circuit and temperature compensated constant-current circuit |
| US7026860B1 (en) * | 2003-05-08 | 2006-04-11 | O2Micro International Limited | Compensated self-biasing current generator |
| CN101178610A (en) * | 2007-12-05 | 2008-05-14 | 西安标新电子科技有限责任公司 | Circuit outputting adjustable positive and negative or zero-temperature coefficient electrical current and voltage reference |
| CN101901018A (en) * | 2009-05-26 | 2010-12-01 | 上海华虹Nec电子有限公司 | Voltage reference circuit |
| CN102375468A (en) * | 2010-08-23 | 2012-03-14 | 联咏科技股份有限公司 | Band gap reference circuit and band gap reference current source |
| CN202870667U (en) * | 2012-10-31 | 2013-04-10 | 沈阳工业大学 | Temperature compensating circuit in precision constant flow source not affected by craft deviation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006043452A1 (en) * | 2005-09-30 | 2007-04-19 | Texas Instruments Deutschland Gmbh | Reference current source |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430395A (en) * | 1992-03-02 | 1995-07-04 | Texas Instruments Incorporated | Temperature compensated constant-voltage circuit and temperature compensated constant-current circuit |
| US7026860B1 (en) * | 2003-05-08 | 2006-04-11 | O2Micro International Limited | Compensated self-biasing current generator |
| CN101178610A (en) * | 2007-12-05 | 2008-05-14 | 西安标新电子科技有限责任公司 | Circuit outputting adjustable positive and negative or zero-temperature coefficient electrical current and voltage reference |
| CN101901018A (en) * | 2009-05-26 | 2010-12-01 | 上海华虹Nec电子有限公司 | Voltage reference circuit |
| CN102375468A (en) * | 2010-08-23 | 2012-03-14 | 联咏科技股份有限公司 | Band gap reference circuit and band gap reference current source |
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