CN102890961A - Storage body structure - Google Patents
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- CN102890961A CN102890961A CN2012103724311A CN201210372431A CN102890961A CN 102890961 A CN102890961 A CN 102890961A CN 2012103724311 A CN2012103724311 A CN 2012103724311A CN 201210372431 A CN201210372431 A CN 201210372431A CN 102890961 A CN102890961 A CN 102890961A
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Abstract
The invention discloses a storage body structure. Nine front-surface storage body units, namely a front-surface first storage body unit, a front-surface second storage body unit, a front-surface third storage body unit, a front-surface fourth storage body unit, a front-surface fifth storage body unit, a front-surface sixth storage body unit, a front-surface seventh storage body unit, a front-surface eighth storage body unit and a front-surface ninth storage body unit, are arranged on the front surface of a printed plate side by side. Nine back-surface storage body units, namely a back-surface first storage body unit, a back-surface second storage body unit, a back-surface third storage body unit, a back-surface fourth storage body unit, a back-surface fifth storage body unit, a back-surface sixth storage body unit, a back-surface seventh storage body unit, a back-surface eighth storage body unit and a back-surface ninth storage body unit, are arranged at the positions, opposite to the front-surface storage body units, of the back surface of the printed plated side by side. The nine front-surface storage body units arranged on the front surface of the printed circuit belong to a first path of storage control; and the nine back-surface storage body units arranged on the back surface of the printed circuit belong to a second path of storage control.
Description
Technical field
The present invention relates to computer technology, more particularly, the present invention relates to a kind of bank structure and memory bank method for arranging.
Background technology
Up to now, be the indispensable fundamental of high-performance computing sector by each for the memory bank that memory chip makes up.Fast development along with high-performance processor, " storage wall " problem has been introduced in relatively lagging behind of internal memory development, and " storage wall " mainly comprises the bottleneck of the aspects such as storage depth (depending on storage bit wide and single-bit storage density), memory bandwidth (depending on storage bit wide and single-bit memory rate); Meanwhile, high-performance calculation itself requires also day by day harsh to the internal memory packing density, as the important fixed part of compute node layout, improves the main memory layout density and is conducive to improve packing density.
At present, meeting JEDEC(Joint Electron Device Engineering Council) the commercial memory standard of standard evolved to the internal memory of third generation Double Data Rate (being DDR3), with reference to JEDEC normative document " DDR3 SDRAM Standard:JESD79-3E, July 2010 ", this standard definition * 8(data bits, also have in addition * 4 and * 1 6) DDR3 SDRAM(memory chip, be also referred to as memory grain in some data) interconnect signal and package pins distribution (the 18 page).
In addition, also there is unified standard in commercial internal memory.With reference to the product Guide Book " DDR3 SDRAM Memory Product Guide " of Samsung (Feb.2011), handbook provides the ins and outs (the 17th page) of Samsung's standard commercial internal memory, finish 1 tunnel 64 (8 memory grain of support at the area of 133.35mm * 30.00mm, be not with the ECC calibration function) or 1 tunnel 72 (9 memory grain, band ECC calibration function) depositing control (deposits the concept of control, be the standard block that control chip carries out Memory control, control chip supports multichannel to deposit control usually) the memory bank layout.Under standard conditions, if improve packing density and memory bandwidth, can only 1. select the short version of VLP(Very Low Profile) memory bar (selecting little encapsulation memory chip compression memory bar height to 18mm) or 2. adopt the more chip of high data rate (DDR3 speed 800Mbps/1066Mbps/1333Mbps/1600Mbps/2133Mbps etc. are optional).The below provides organizational structure, method for arranging and the lead plate strategy (concept of lead plate is the fan-out process that chip signal is led to wiring layer in printed board from pad, usually need to change to wiring layer from surface drilling) of standard commercial internal memory.
Take with 72 memory bars of ECC check bit as example, commercial UDIMM memory bar is divided into 9 chips of single RANK(single face) and two two-sided 18 chips of RANK() two kinds.
Take the memory chip (for example 2Gb chip) that adopts same capability as example, single RANK and pair RANK differences between the two are:
1. two RANK can increase storage depth, the extension storage capacity.
2. two RANK can increase a small amount of group of addresses signal, wherein, clock and control signal quantity double and keep 1 to push away 9 Fly-by topology, address and command signal quantity remain unchanged but load to increase the weight of be 1 to push away 18 Fly-by topology, load increases the weight of there is impact in signal transmission quality, affects the efficient of memory access.
3. the group of addresses number of signals of two RANK remains unchanged, but topology changes into from point to points 1 and push away 2, and load increases the weight of there is impact in signal transmission quality, affects the raising (may cause Bandwidth Reduction) of signal rate.
Jointly being between the two:
1. every memory chip layout areas all needs to draw 11 bit data group signals, the single Rank of 28()～the two Rank of 33() bit address group signal.
2. the address signal of leap (Fly-by) topology need to be realized interconnection between the adjacent memory chip, and then the data-signal with the point-to-point topology is directly connected to the golden finger fixed position, is connected at last the control chip of computing mainboard by socket.
In view of layout density and method for arranging that the present invention carries have comparability, in Fig. 1, schematically show the two RANK UDIMM memory bars of standard commercial its positive arrange with and reverse side arrange.In its front, Memory cell A1, A2, A3, A4, A5, A6, A7, A8, A9 are arranged side by side.At its reverse side, Memory cell B1, B2, B3, B4, B5, B6, B7, B8, B9 are arranged side by side.
Two RANK use for standard commercial, in chip layout in the internal memory of prior art, the signal lead plate, data-signal connects 2 two-sided chips by 1 boring, address signal also is to connect 2 two-sided chips by 1 boring, storage core panel region lead plate and drill hole density less (density that single RANK uses is less) design comparatively simple.
By selecting the VLP memory bar based on the two-forty memory chip, can improve packing density and memory bandwidth.For example, the commercial standard (CS) memory bar is replaced by the VLP memory bar, and layout area reduces by 40%; In the situation that control chip is supported, memory chip is replaced with the particle of supporting 1600Mbps from the particle of supporting 800Mbps, and memory bandwidth can increase by 1 times.
But the two-forty memory chip is the inevitable choice of high-performance calculation, so said method only improves packing density and have limited action, and can not be when improving packing density the Effective Raise memory bandwidth.
Summary of the invention
Technical matters to be solved by this invention is for there being defects in the prior art, provides a kind of and can improve memory bandwidth when improving packing density, simultaneously not the bank structure take the victim signal quality as cost and memory bank method for arranging.
According to the present invention, a kind of bank structure is provided, and it comprises: nine front Memory cells that the front of printed board is arranged side by side: positive the first Memory cell, positive the second Memory cell, positive the 3rd Memory cell, positive the 4th Memory cell, positive the 5th Memory cell, positive the 6th Memory cell, positive the 7th Memory cell, positive the 8th Memory cell and positive the 9th Memory cell; Nine reverse side Memory cells that the reverse side of the printed board position corresponding with described nine front Memory cells is arranged side by side: reverse side the first Memory cell, reverse side the second Memory cell, reverse side the 3rd Memory cell, reverse side the 4th Memory cell, reverse side the 5th Memory cell, reverse side the 6th Memory cell, reverse side the 7th Memory cell, reverse side the 8th Memory cell and reverse side the 9th Memory cell; Nine front Memory cells that install in the front of printed board belong to the first via and deposit control; And described nine the reverse side Memory cells that are used for that the reverse side of printed board is installed belong to the second the tunnel and deposit control.
Preferably, described nine front Memory cells are arranged in a row, and described nine reverse side Memory cells correspondingly are arranged in a row.9 chips of RANK(single face) and two two-sided 18 chips of RANK() two kinds of existing commercial products: single Rank is 9 of single face one rows, and two Rank are 9 (total 18) of two-sided each row.
Further preferably, the part of described nine front Memory cells is lined up the front first row, and the remainder of described nine front Memory cells is lined up the front second row, and the orientation of described front first row is vertical with the orientation of described front second row; Correspondingly, the part of described nine reverse side Memory cells is lined up the reverse side first row, and the remainder of described nine reverse side Memory cells lines up the reverse side second row, and the orientation of described reverse side first row is vertical with the orientation of described reverse side second row.
Further preferably, described positive the first Memory cell, described positive the second Memory cell, described positive the 3rd Memory cell and described positive the 4th Memory cell, described positive the 5th Memory cell are disposed in the first row of front, described positive the 6th Memory cell, described positive the 7th Memory cell, described positive the 8th Memory cell and described positive the 9th Memory cell are disposed in the second row of front, wherein, the orientation of described front first row is vertical with the orientation of described front second row; Described reverse side the first Memory cell, described reverse side the second Memory cell, described reverse side the 3rd Memory cell and described reverse side the 4th Memory cell, described reverse side the 5th Memory cell are disposed in the first row of front, described reverse side the 6th Memory cell, described reverse side the 7th Memory cell, described reverse side the 8th Memory cell and described reverse side the 9th Memory cell are disposed in the second row of front, wherein, the orientation of described reverse side first row is vertical with the orientation of described reverse side second row.The Memory cell quantity that first row and second row are arranged can suitably be regulated according to the system layout demand.
The part of described nine front Memory cells is lined up the front first row, and the remainder of described nine front Memory cells lines up the front second row, and the orientation of described front first row is parallel with the orientation of described front second row; And the part of described nine reverse side Memory cells is lined up the reverse side first row, and the remainder of described nine reverse side Memory cells lines up the reverse side second row, and the orientation of described reverse side first row is parallel with the orientation of described reverse side second row.Preferably, described positive the first Memory cell, described positive the second Memory cell, described positive the 3rd Memory cell and described positive the 4th Memory cell, described positive the 5th Memory cell are disposed in the first row of front, described positive the 6th Memory cell, described positive the 7th Memory cell, described positive the 8th Memory cell and described positive the 9th Memory cell are disposed in the second row of front, wherein, the orientation of described front first row is parallel with the orientation of described front second row; Described reverse side the first Memory cell, described reverse side the second Memory cell, described reverse side the 3rd Memory cell and described reverse side the 4th Memory cell, described reverse side the 5th Memory cell are disposed in the first row of front, described reverse side the 6th Memory cell, described reverse side the 7th Memory cell, described reverse side the 8th Memory cell and described reverse side the 9th Memory cell are disposed in the second row of front, wherein, the orientation of described reverse side first row is parallel with the orientation of described reverse side second row.The Memory cell quantity that first row and second row are arranged can suitably be regulated according to the system layout demand.
Preferably, in the front of printed board and every one side of reverse side, data group signal is being drawn perpendicular to the direction of Memory cell arragement direction with the topological structure of point-to-point.
Preferably, in the front of printed board and every one side of reverse side, the group of addresses signal of control is deposited with the topological structure of leap in every road, is connected in the direction that is parallel to the Memory cell arragement direction to belong to all Memory cells that control is deposited on this road.
The invention provides a kind of bank structure and memory bank method for arranging, had the large advantage of good, the two Rank layout density of single Rank signal integrity in the standard commercial internal memory concurrently, Effective Raise packing density and memory bandwidth satisfy high-performance calculation and use simultaneously.Specifically, the present invention increases memory bandwidth by increasing same area memory access data bit width; For example, 1 tunnel 72 of same area is deposited control and is increased to 2 the tunnel 72 and deposit control, and bandwidth equals data bit width * data rate.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows according to front layout, the reverse side of the bank structure of prior art and arranges, and the signal annexation.
Fig. 2 schematically shows according to front layout, the reverse side of the bank structure of the embodiment of the invention and arranges, and the signal annexation.
Fig. 3 schematically shows the another kind of arrangement according to the bank structure of the embodiment of the invention, signal annexation and shown in Figure 2 in full accord.
Fig. 4 schematically shows another arrangement according to the bank structure of the embodiment of the invention, signal annexation and shown in Figure 2 in full accord.
Need to prove, accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Note, the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
In the specific embodiment of the present invention, can be in the area that is lower than the VLP memory bar, improve memory bandwidth by the method that doubles data bit width, that is to say that the front is that 1 road memory bank, reverse side are other 1 road memory bank, finishes the memory bank layout of 2 tunnel 64 or 72 (amounting to 144).The below will specifically describe the preferred embodiments of the present invention.That is to say, the present invention increases memory bandwidth by increasing same area memory access data bit width; For example, 1 tunnel 72 of same area is deposited control and is increased to 2 the tunnel 72 and deposit control, and bandwidth equals data bit width * data rate.
The＜the first embodiment 〉
Fig. 2 schematically shows according to front layout, the reverse side of the bank structure of the embodiment of the invention and arranges, and the signal annexation.
As shown in Figure 2, nine the front Memory cells that have been arranged side by side in the front of printed board 1: positive the first Memory cell A1, positive the second Memory cell A2, positive the 3rd Memory cell A3, positive the 4th Memory cell A4, positive the 5th Memory cell A5, positive the 6th Memory cell A6, positive the 7th Memory cell A7, positive the 8th Memory cell A8 and positive the 9th Memory cell A9.
In reverse side and described nine positions that the front Memory cell is corresponding of printed board, nine reverse side Memory cells have been arranged side by side: reverse side the first Memory cell B1, reverse side the second Memory cell B2, reverse side the 3rd Memory cell B3, reverse side the 4th Memory cell B4, reverse side the 5th Memory cell B5, reverse side the 6th Memory cell B6, reverse side the 7th Memory cell B7, reverse side the 8th Memory cell B8 and reverse side the 9th Memory cell B9.
For example, described nine front Memory cells and described nine reverse side Memory cells are DRAM(Dynamic Random Access Memory, i.e. dynamic RAM) storage chip.
Preferably, as shown in Figure 2, described nine front Memory cells are arranged in a row, and described nine reverse side Memory cells correspondingly are arranged in a row.In said structure, " described nine front Memory cells are arranged in a row; and described nine reverse side Memory cells correspondingly are arranged in a row " layout be equivalent to 9 chips of RANK(single face) and two two-sided 18 chips of RANK() comprehensive, be equivalent to two single RANK difference layouts at pro and con, and its layout density is similar but variant with two RANK.Specifically, difference 1: single Rank is 72 bit data, and two Rank are 72 bit data, and the layout of " described nine front Memory cells are arranged in a row, and described nine reverse side Memory cells correspondingly are arranged in a row " is 2 * 72 bit data (density is large); Difference 2: single RANK is 1 tunnel address, 28 bit address group signals, two RANK are 1 tunnel address, 33 bit address group signals, " described nine front Memory cells are arranged in a row, and described nine reverse side Memory cells correspondingly are arranged in a row " is 2 tunnel addresses, every road 28 bit address group signals.And, quantity variance for address and data-signal, can from Fig. 1 and Fig. 2, find out, two Rank address is 2, data are 3, " described nine front Memory cells are arranged in a row; and described nine reverse side Memory cells correspondingly are arranged in a row " the address of layout be 2/4, data are 3/5, so increased quantity and all increased by one times because deposit the control way.
The layout area of bank structure according to the embodiment of the invention shown in Figure 2 can be 120.00mm * 15.00mm particularly; Compare packing density with standard commercial memory bar shown in Figure 1 and improved more than 1 times, the regional W1(that has saved address introducing and SPD layout than VLP memory bar is shown in Figure 1), and data bit width doubles to bring the amplification of 1 times of memory bandwidth.
Use for the typical case, the data-signal of bank structure according to the embodiment of the invention shown in Figure 2 is consistent substantially with lead-out mode and original standard commercial internal memory of address signal, but the number of signals increase is drawn in the part.Specifically, in the front of printed board and every one side of reverse side, data-signal (data-signal 3 of described nine front Memory cells and the data-signal 5 of described nine reverse side Memory cells) with the topological structure of point-to-point, is being drawn perpendicular to the direction of Memory cell arragement direction; Address signal (address signal 2 of described nine front Memory cells and the address signal 4 of described nine reverse side Memory cells) is connected to all Memory cells with the topological structure of leap (Fly-by) in the direction that is parallel to the Memory cell arragement direction.And for example, the data-signal termination is built in memory chip inside, and the address signal termination needs external terminating resistor.
In addition, for the bank structure according to the embodiment of the invention shown in Figure 2, two installed surfaces separately (front and back) of layout different deposit between the control signal separate.That is, described nine front Memory cells that install in the front of printed board belong to the first via and deposit control, and described nine reverse side Memory cells that reverse side is installed belong to the second the tunnel and deposit control.Just deposit control, the Memory cell in front and the reverse side is without any interconnected relationship.
More particularly, for example, the front of printed board is installed the first via that is used for described nine front Memory cells and is deposited control; The reverse side of printed board is installed for the second tunnel of described nine reverse side Memory cells and is deposited control.And for example, in other embodiments, two-way is deposited control and can be integrated on 1 chip, thus two-way deposit the installed surface of control may be all on front or reverse side.
In the bank structure according to the embodiment of the invention shown in Figure 2, make up novel bank structure by 2 tunnel memory chips of depositing control in two installed surface independence layouts, to realize that packing density increases and the purpose that doubles of memory bandwidth.
The novel bank structure of the above embodiment of the present invention can Effective Raise packing density and memory bandwidth, but lead plate, boring and the wiring in memory bank zone proposed very large challenge.By design optimization, the boring that the memory bank zone increases and lead plate be (because signal load is better than two RANK UDIMM, signal rate improves also can be secure) not take the victim signal integrality as cost.Novel bank structure is directly assembled at the computing mainboard, can transfer to adapt to concrete assembling demand by for example right angle turnover and level, and according to dirigibility, cost only is that certain sector address signal elongates on a small quantity in the leap topology aspect package assembly.
The＜the second embodiment 〉
Preferably, the part of described nine front Memory cells is lined up the front first row, and the remainder of described nine front Memory cells lines up the front second row, and the orientation of described front first row is vertical with the orientation of described front second row; And the part of described nine reverse side Memory cells is lined up the reverse side first row, and the remainder of described nine reverse side Memory cells lines up the reverse side second row, and the orientation of described reverse side first row is vertical with the orientation of described reverse side second row.
The specific embodiment of this preferred implementation is described below in conjunction with Fig. 3.
Fig. 3 schematically shows the another kind of arrangement according to the bank structure of the embodiment of the invention; Wherein show the distribution form of right angle turnover, its signal annexation and shown in Figure 2 in full accord.
As shown in Figure 3, positive the first Memory cell A1, positive the second Memory cell A2, positive the 3rd Memory cell A3, positive the 4th Memory cell A4, positive the 5th Memory cell A5 are disposed in the first row of front.
Positive the 6th Memory cell A6, positive the 7th Memory cell A7, positive the 8th Memory cell A8 and positive the 9th Memory cell A9 are disposed in the second row of front.
Wherein, the orientation of front first row is vertical with the orientation of front second row.
Similarly, reverse side the first Memory cell B1, reverse side the second Memory cell B2, reverse side the 3rd Memory cell B3, reverse side the 4th Memory cell B4, reverse side the 5th Memory cell B5 are disposed in the first row of front.
Reverse side the 6th Memory cell B6, reverse side the 7th Memory cell B7, reverse side the 8th Memory cell B8 and reverse side the 9th Memory cell B9 are disposed in the second row of front.
Wherein, the orientation of reverse side first row is vertical with the orientation of reverse side second row.
Thus, above-mentioned arrangement can adapt to specific applicable cases; Wherein, for example, the zone in the corner at the formed right angle of Memory cell, described nine fronts can be used as the wiring zone that control chip takies; Equally, the zone in the corner at described nine formed right angles of reverse side Memory cell can be used as the wiring zone that control chip takies; Finally, flexibly, effectively utilized printed board domain resource.
And the Memory cell quantity that first row and second row are arranged can suitably be regulated according to the system layout demand.
The＜the three embodiment 〉
Preferably, the part of described nine front Memory cells is lined up the front first row, and the remainder of described nine front Memory cells lines up the front second row, and the orientation of described front first row is parallel with the orientation of described front second row; And the part of described nine reverse side Memory cells is lined up the reverse side first row, and the remainder of described nine reverse side Memory cells lines up the reverse side second row, and the orientation of described reverse side first row is parallel with the orientation of described reverse side second row.
The specific embodiment of this preferred implementation is described below in conjunction with Fig. 4.Fig. 4 schematically shows another arrangement according to the bank structure of the embodiment of the invention; Wherein show the distribution form of level turnover, its signal annexation and shown in Figure 2 in full accord.
As shown in Figure 4, positive the first Memory cell A1, positive the second Memory cell A2, positive the 3rd Memory cell A3, positive the 4th Memory cell A4, positive the 5th Memory cell A5 are disposed in the first row of front.
Positive the 6th Memory cell A6, positive the 7th Memory cell A7, positive the 8th Memory cell A8 and positive the 9th Memory cell A9 are disposed in the second row of front.
Wherein, the orientation of front first row is parallel with the orientation of front second row.
Similarly, reverse side the first Memory cell B1, reverse side the second Memory cell B2, reverse side the 3rd Memory cell B3, reverse side the 4th Memory cell B4, reverse side the 5th Memory cell B5 are disposed in the first row of front.
Reverse side the 6th Memory cell B6, reverse side the 7th Memory cell B7, reverse side the 8th Memory cell B8 and reverse side the 9th Memory cell B9 are disposed in the second row of front.
Wherein, the orientation of reverse side first row is parallel with the orientation of reverse side second row.
Thus, above-mentioned arrangement can adapt to specific applicable cases: wherein, for example, with respect to arrangement shown in Figure 2, arrangement shown in Figure 4 has compressed the Memory cell layout, can effectively reduce printed board direction length.And the Memory cell quantity that first row and second row are arranged can suitably be regulated according to the system layout demand.
In addition, need to prove, term in the instructions " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing instructions, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.And in this instructions, term " front " and " reverse side " only are used for two faces are distinguished, rather than are used for other restriction.
Be understandable that, although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. a bank structure is characterized in that comprising: nine front Memory cells that the front of printed board is arranged side by side: positive the first Memory cell, positive the second Memory cell, positive the 3rd Memory cell, positive the 4th Memory cell, positive the 5th Memory cell, positive the 6th Memory cell, positive the 7th Memory cell, positive the 8th Memory cell and positive the 9th Memory cell;
Nine reverse side Memory cells that the reverse side of the printed board position corresponding with described nine front Memory cells is arranged side by side: reverse side the first Memory cell, reverse side the second Memory cell, reverse side the 3rd Memory cell, reverse side the 4th Memory cell, reverse side the 5th Memory cell, reverse side the 6th Memory cell, reverse side the 7th Memory cell, reverse side the 8th Memory cell and reverse side the 9th Memory cell;
Described nine front Memory cells that install in the front of printed board belong to the first via and deposit control; And
Described nine reverse side Memory cells that the reverse side of printed board is installed belong to the second the tunnel and deposit control.
2. bank structure according to claim 1 is characterized in that, described nine front Memory cells are arranged in a row, and described nine reverse side Memory cells correspondingly are arranged in a row.
3. bank structure according to claim 1, it is characterized in that, the part of described nine front Memory cells is lined up the front first row, and the remainder of described nine front Memory cells is lined up the front second row, and the orientation of described front first row is vertical with the orientation of described front second row; Correspondingly, the part of described nine reverse side Memory cells is lined up the reverse side first row, and the remainder of described nine reverse side Memory cells lines up the reverse side second row, and the orientation of described reverse side first row is vertical with the orientation of described reverse side second row.
4. bank structure according to claim 3, it is characterized in that, described positive the first Memory cell, described positive the second Memory cell, described positive the 3rd Memory cell, and described positive the 4th Memory cell, described positive the 5th Memory cell is disposed in the first row of front, described positive the 6th Memory cell, described positive the 7th Memory cell, described positive the 8th Memory cell, and described positive the 9th Memory cell is disposed in the second row of front, wherein, the orientation of described front first row is vertical with the orientation of described front second row;
Described reverse side the first Memory cell, described reverse side the second Memory cell, described reverse side the 3rd Memory cell and described reverse side the 4th Memory cell, described reverse side the 5th Memory cell are disposed in the first row of front, described reverse side the 6th Memory cell, described reverse side the 7th Memory cell, described reverse side the 8th Memory cell and described reverse side the 9th Memory cell are disposed in the second row of front, wherein, the orientation of described reverse side first row is vertical with the orientation of described reverse side second row.
5. bank structure according to claim 1, it is characterized in that, the part of described nine front Memory cells is lined up the front first row, and the remainder of described nine front Memory cells is lined up the front second row, and the orientation of described front first row is parallel with the orientation of described front second row; And the part of described nine reverse side Memory cells is lined up the reverse side first row, and the remainder of described nine reverse side Memory cells lines up the reverse side second row, and the orientation of described reverse side first row is parallel with the orientation of described reverse side second row.
6. bank structure according to claim 5, it is characterized in that, described positive the first Memory cell, described positive the second Memory cell, described positive the 3rd Memory cell, and described positive the 4th Memory cell, described positive the 5th Memory cell is disposed in the first row of front, described positive the 6th Memory cell, described positive the 7th Memory cell, described positive the 8th Memory cell, and described positive the 9th Memory cell is disposed in the second row of front, wherein, the orientation of described front first row is parallel with the orientation of described front second row;
Described reverse side the first Memory cell, described reverse side the second Memory cell, described reverse side the 3rd Memory cell and described reverse side the 4th Memory cell, described reverse side the 5th Memory cell are disposed in the first row of front, described reverse side the 6th Memory cell, described reverse side the 7th Memory cell, described reverse side the 8th Memory cell and described reverse side the 9th Memory cell are disposed in the second row of front, wherein, the orientation of described reverse side first row is parallel with the orientation of described reverse side second row.
7. according to claim 1 to one of 6 described bank structure, it is characterized in that, in the front of printed board and every one side of reverse side, data group signal is being drawn perpendicular to the direction of Memory cell arragement direction with the topological structure of point-to-point.
8. according to claim 1 to one of 6 described bank structure, it is characterized in that, in the front of printed board and every one side of reverse side, the group of addresses signal of control is deposited with the topological structure of leap in every road, is connected in the direction that is parallel to the Memory cell arragement direction to belong to all Memory cells that control is deposited on this road.
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| CN1332457A (en) * | 2000-06-30 | 2002-01-23 | 三星电子株式会社 | Double-channel storage system and storage module of shared control and address bus |
| US20050286334A1 (en) * | 2004-06-29 | 2005-12-29 | Nec Corporation | Stacked semiconductor memory device |
| CN1832165A (en) * | 2004-12-10 | 2006-09-13 | 因芬尼昂技术股份公司 | Stacked dram memory chip for a dual inline memory module (dimm) |
| CN1815622A (en) * | 2005-02-03 | 2006-08-09 | 因芬尼昂技术股份公司 | Semi-conductor memory module with bus construction |
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