CN102882536B - Radio frequency receiver of BeiDou radio determination satellite service (RDSS) satellite navigation system - Google Patents

Abstract

The invention relates to a radio frequency receiver of a BeiDou radio determination satellite service (RDSS) satellite navigation system. According to the receiver, a twice frequency conversion structure is adopted; a radio frequency signal is converted into a first intermediate frequency signal by using down conversion through a radio frequency front-end circuit; after being filtered, the frequency of the first intermediate frequency signal is converted into a clock sampling frequency by using the down conversion; on one hand, after being added with a driver, the clock sampling frequency serves as a sampling operating frequency of post-circuits; and on the other hand, the clock sampling frequency is subjected to divide-by-4 frequency dividing, an intermediate frequency output signal required by a system is acquired, and the intermediate frequency output signal enters the post-circuits. The receiver comprises a low noise amplifier, two stages of mixer, filters, a variable gain amplifier, an automatic gain control circuit, a divide-by-4 frequency divider, a drive circuit, an analog to digital converter, a fractional frequency division phase locked loop of an internal radio frequency voltage control oscillator and a divide-by-3 frequency divider circuit, wherein the internal radio frequency voltage control oscillator generates two stages of local oscillator signals.

Description

The radio-frequency transmitter of Big Dipper RDSS satellite navigation system

Technical field

The present invention relates to a kind of radio-frequency (RF) receiving circuit, a kind of chip circuit of Big Dipper RDSS satellite navigation system radio-frequency transmitter design specifically.

Background technology

Along with the operation of China's Beidou satellite navigation experimental system, the development of GPS (Global Position System) at present has just progressively formed the general layout of cubic your kind effort, is respectively the GPS of the U.S., Muscovite GLONASS, the GALILEO system of European Union and Chinese dipper system.Beidou satellite navigation system is the autonomous construction of China, independent operating, and the GPS (Global Position System) compatible shared with other satellite navigation systems of the world, it creates with development has thoroughly broken the monopolization of western countries at global navigation satellite technical elements, to China and even the world in economy, politics, and military aspect has important and far-reaching meaning.Dipper system can be round-the-clock in the world, and round-the-clock provides high accuracy for all types of user, highly reliable location, and navigation, time service service, and have short message communication capacity concurrently.

Beidou satellite navigation system is made up of vacant terminal, ground surface end and user side three parts.Vacant terminal comprises 5 satellites and 30 non-geo satellites.Ground surface end comprises several ground stations such as master station, injection station and monitoring station.User side by Big Dipper user terminal and with GPS of America, Russia's " GLONASS " (GLONASS), the terminal of other satellite navigation system compatibilities such as European " Galileo " (GALILEO) forms.

Since building up from experimental system in 2000, Beidou satellite navigation system has been launched 10 satellites, has built up fundamental system, plans in the year two thousand twenty left and right, and Beidou satellite navigation system forms Global coverage ability.Therefore,, as the development of the radio frequency reception machine technology of Big Dipper RDSS satellite navigation system significant components, will produce vital impact to dipper system.

Current, the radio-frequency module of Big Dipper terminal adopts discrete device to design mostly, causes system debug difficulty, and small product size is huge, and the utmost point is unfavorable for carrying, and power consumption is high, and cost is high.Meanwhile, part key chip depends on external import, and key technology is still subject to external left and right.All of these factors taken together is all unfavorable for the independent development capability of dipper system and popularizes.

Mostly current Big Dipper RDSS receiver is to adopt single-conversion structure, cause mirror image rejection poor, even if some receiver adopts double conversion structure, but be by two frequency synthesizers, be to provide respectively two-stage local oscillation signal by the voltage controlled oscillator of two different frequency ranges and independent cycle of phase-locked loop part, and for providing the module of time clock feature, subsequent conditioning circuit also need to be produced by phase-locked loop circuit other in receiver chip, so just cause system complex, power consumption is high, serious interference on the sheet of local oscillation signal.The more important thing is, provide the frequency synthesizer of local oscillation signal to adopt integer-N PLL structure, it is at special frequency, under the higher application of frequency dividing ratio, can reduce the phase noise of local oscillation signal, thereby reduce sensitivity and the interference free performance of receiver.

Summary of the invention

The technical program technical problem to be solved is: the shortcoming existing for above prior art, a kind of radio-frequency transmitter of Big Dipper RDSS satellite navigation system is proposed, comprise radiofrequency signal receiver, final intermediate frequency and sheet external clock produce circuit, and local oscillation signal circuit for generating, can improve the mirror image rejection of Big Dipper RDSS satellite navigation system radio-frequency transmitter, avoid the phase mutual interference between many phase-locked loops, improve the sensitivity of radio-frequency transmitter, reduce power consumption, reduce circuit quantity, reduce costs, make receiver be easier to integrated chip.

The technical scheme that solves above technical problem is as follows:

A radio-frequency transmitter for Big Dipper RDSS satellite navigation system, comprises radiofrequency signal receiver and local oscillation signal circuit for generating.

Described local oscillation signal circuit for generating comprises phase-locked loop circuit and three frequency division frequency divider, and this three frequency division frequency divider is connected to the output of phase-locked loop circuit;

Described radiofrequency signal receiver comprises low noise amplifier, two mixer stages and corresponding filter, variable gain amplifier, automatic gain control circuit, four frequency division frequency dividers, driver buffer and analog to digital converter; The input of described low noise amplifier receives external radio-frequency signal; The output of low noise amplifier connects the signal input part of first order frequency mixer; The signal output part of first order frequency mixer connects the signal input part of second level frequency mixer by corresponding filter; The signal output part of second level frequency mixer is divided into two paths of signals output after by corresponding filter, and a road output signal is successively by entering analog to digital converter as the output signal of digital to analog converter after variable gain amplifier and four frequency division frequency dividers; Another road output signal is further divided into two-way output after drive circuit by increasing, respectively as the sampling incoming frequency of analog to digital converter in the clock of the outer late-class circuit of sheet and sheet,

Circuit after the frequency mixer of the described second level forms final intermediate frequency and sheet external clock produces circuit; The output of analog to digital converter is first output of this radio-frequency transmitter, for late-class circuit provides signal; The frequency being produced by drive circuit is output as another output of this radio-frequency transmitter, for late-class circuit provides clock.

The local oscillator input of first order frequency mixer directly connects the output of phase-locked loop circuit; The local oscillator input of second level frequency mixer connects the signal output part of three frequency division frequency divider.

Described phase-locked loop circuit is fractional phase lock loop circuit, and it comprises digital frequency phase detector PFD, charge pump CP, inductance, low pass filter, voltage controlled oscillator VCO, high frequency dual-modulus prescaler PRESCALER and sigma-delta decimal frequency divider;

The high-frequency signal of described voltage controlled oscillator output carries out pre-frequency division through high frequency dual-modulus prescaler, obtain can intermediate frequency process digital signal; This digital signal is sent into sigma-delta decimal frequency divider, obtains comparison clock signal after fractional frequency division; The reference clock signal f of this comparison clock signal and clock output circuit input _inas two input signals of phase frequency detector; These two input signals obtain the phase signal between them through phase frequency detector, and this phase signal obtains the voltage corresponding with phase signal through charge pump, inductance and low pass filter successively; This voltage, as the control voltage of voltage controlled oscillator, carrys out the phase error of compensated voltage controlled oscillator, and in the time that phase error is less than setting, phase-locked loop keeps the lock-out state of dynamic equilibrium, and the now output of voltage controlled oscillator is the output signal of phase-locked loop circuit.

Described low pass filter is the RC passive ring filter being made up of RC passive component.

The distinctive feature of the technical program comprises:

This radio-frequency transmitter adopts double conversion structure, only produces the first local oscillation signal with a phase-locked loop circuit, and the second local oscillation signal carries out three frequency division generation by the first local oscillation signal.

This radio-frequency transmitter can directly be used double conversion structure generation clock circuit, for the outer clock of late-class circuit of sheet and the sample frequency of on-chip circuit.

The signal of the final intermediate frequency output signal of this radio-frequency transmitter after by double conversion carries out four frequency division generations again.

This radio-frequency transmitter is the fractional frequency-division phase-locked loop of built-in voltage controlled oscillator for generation of the phase-locked loop structures of local oscillation signal.

The fractional frequency-division phase-locked loop circuit of this radio-frequency transmitter is to be made up of digital frequency phase detector PFD, charge pump CP, inductance, loop filter, voltage controlled oscillator VCO, high frequency dual-modulus prescaler PRESCALER and a sigma-delta decimal frequency divider.

The output of the charge pump of the fractional frequency-division phase-locked loop circuit of this radio-frequency transmitter connects inductance, then is connected with the loop filter being made up of RC element.

The principle of the technical program is described as follows:

First radio-frequency input signals carries out denoising amplification through low noise amplifier, deliver to first order frequency mixer, carry out difference frequency with the first local oscillation signal, be down to the first intermediate-freuqncy signal (IF1), the first intermediate-freuqncy signal inputs to second level frequency mixer after band-pass filter noise reduction, carry out difference frequency with the second local oscillation signal again, produce the second intermediate frequency clock signal (IF2), be divided into again two-way, leading up to increases drive circuit and divides to sheet the sampling incoming frequency of analog to digital converter in late-class circuit and sheet, separately lead up to and enter modulus as signal after the output of variable gain amplifier and four frequency divisions and turn device.

Local oscillation signal produces circuit and comprises digital frequency phase detector PFD, charge pump CP, inductance, loop filter, voltage controlled oscillator VCO, high frequency dual-modulus prescaler PRESCALER, and the fractional frequency-division phase-locked loop road of sigma-delta decimal frequency divider formation.

The high-frequency signal of voltage controlled oscillator is through the pre-frequency division of high frequency dual-modulus prescaler, formation can intermediate frequency process digital signal, send into sigma-delta decimal frequency divider, the comparison clock signal producing after fractional frequency division and two inputs of the reference clock signal of being inputted by crystal oscillator as phase frequency detector, output at phase frequency detector produces phase difference, send into again charge pump, via inductance, again to RC passive filter, produce and the corresponding voltage of phase difference, send into voltage controlled oscillator, the phase error of compensated voltage controlled oscillator, it is final in the time that phase error is less than a setting, phase-locked loop keeps the lock-out state of dynamic equilibrium, the now output of voltage controlled oscillator is as the local oscillation signal of receiver, send into frequency converter.

The radio-frequency transmitter of the technical program adopts double conversion structure, and double conversion device all adopts low local oscillator, and local oscillation signal frequency is lower than radio frequency signal frequency.The first local oscillation signal obtains the second local oscillation signal divided by 3.The first local oscillation signal adopts fractional frequency-division phase-locked loop structure.

The advantage of the technical program is: the frequency planning of the technical program is ingenious, adopts fractional frequency-division phase-locked loop to realize the low local oscillation signal output of making an uproar mutually of special frequency.A phase-locked loop provides two different local oscillation signals, realizes the structure of receiver double conversion.The second local oscillation signal is obtained divided by 3 by the first local oscillation signal.Receiver double conversion structure only needs the fractional frequency-division phase-locked loop loop of a built-in RF Voltage-Controlled Oscillator, and two frequency dividers, just can produce the needed clock frequency signal of system and intermediate frequency output signal, and without carrying out clocking by other phase-locked loop circuit.

The local oscillation signal that fractional frequency-division phase-locked loop produces can greatly reduce itself and the frequency dividing ratio of inputting crystal oscillator compared with integer phase-locked loop, increase the lasting accuracy of local oscillation signal, improved the performance of making an uproar mutually of local oscillator and receiver link, thereby very big degree sensitivity and the antijamming capability of receiver are improved.Clock frequency signal is also by the structure generation of double conversion, and having changed need increase a phase-locked loop with contact and produce the way of clock circuit, thereby reduced module spending for whole radio-frequency transmitter circuit.Therefore the phase mutual interference between multiple phase-locked loops has been avoided in the application of this radio-frequency transmitter, has both optimized circuit noise and performance, has reduced again circuit quantity, has dwindled chip area, has reduced circuit power consumption and cost.

Accompanying drawing explanation

Fig. 1 is the receiver block diagram of the technical program.

Fig. 2 is the local oscillation signal Organization Chart of the technical program double conversion.

Fig. 3 is the clock output map after the technical program double conversion.

Fig. 4 is the final intermediate frequency output map after the technical program double conversion.

Fig. 5 is the block diagram that the technical program local oscillation signal produces.

Fig. 6 is the circuit block diagram of the technical program fractional frequency-division phase-locked loop.

Fig. 7 is the series system block diagram of the technical program fractional frequency-division phase-locked loop internal inductance.

Fig. 8 is the overall structure block diagram of the technical program;

Fig. 9 is quantizing noise linear model;

Figure 10 a is that same quantization noise power is contributed schematic diagram under general sample mode, and wherein, noise all drops in signal band;

Figure 10 b is that same quantization noise power is contributed schematic diagram under over-sampling mode, and wherein, noise section drops in signal band;

Figure 11 is quantized noise shaping principle schematic;

Figure 12 is single order sigma-delta and noise analysis schematic diagram;

Figure 13 is second order sigma-delta and noise analysis schematic diagram;

Figure 14 is the schematic diagram that is related to of input signal power and signal to noise ratio;

Figure 15 is the schematic diagram that is related to of frequency and power spectral density.

Embodiment

A kind of Big Dipper RDSS satellite navigation system radio-frequency transmitter of the present invention, adopt double conversion structure, first by radio-frequency (RF) front-end circuit, radiofrequency signal is down-converted to the first intermediate-freuqncy signal, after filtering, the first intermediate-freuqncy signal is down-converted to clock sampling frequency again, after this frequency drives by increase on the one hand, as the sampling work frequency of late-class circuit, carries out on the one hand four frequency divisions again, the intermediate frequency output signal that obtains system requirements, enters late-class circuit.Receiver comprises low noise amplifier, two mixer stages, filter, variable gain amplifier, automatic gain control circuit, the frequency divider of four frequency divisions, a drive circuit, an analog to digital conversion circuit comprises the fractional frequency-division phase-locked loop loop of built-in RF Voltage-Controlled Oscillator and the divider circuit of a three frequency division that produce two-stage local oscillation signal simultaneously.Receiver is characterised in that frequency planning is reasonable, adopt the divider circuit of a fractional frequency-division phase-locked loop circuit and a three frequency division just can realize the output of two-stage local oscillation signal, and directly by the clock signal of double conversion structure generation late-class circuit, and intermediate frequency output signal, and without increasing again special clock generation circuit in addition.Its advantage is: double conversion only needs the fractional frequency-division phase-locked loop loop of a built-in RF Voltage-Controlled Oscillator, and two frequency dividers, just can produce the needed clock frequency signal of system and intermediate frequency output signal.The local oscillation signal that fractional frequency-division phase-locked loop produces can greatly reduce itself and the frequency dividing ratio of inputting crystal oscillator compared with integer phase-locked loop, increase the lasting accuracy of local oscillation signal, improved the phase noise of local oscillator and receiver link, thereby greatly degree the sensitivity of receiver and the phase deviation degree of output intermediate frequency are improved.Clock frequency signal is also by the structure generation of double conversion, and having changed need increase a phase-locked loop with contact and produce the way of clock circuit, thereby reduced module spending for whole radio-frequency transmitter circuit.Therefore the phase mutual interference between multiple phase-locked loops has been avoided in the application of this radio-frequency transmitter, has both optimized circuit noise and performance, has reduced again circuit quantity, has dwindled chip area, has reduced circuit power consumption and cost.

The technical program is further illustrated as follows below in conjunction with accompanying drawing and embodiment:

A kind of Big Dipper RDSS satellite navigation system radio-frequency transmitter, comprises low noise amplifier, two mixer stages, variable gain amplifier, filter, automatic gain control circuit, the frequency divider of four frequency divisions, driver, an analog to digital converter.By frequency divider, the driver of four frequency divisions, can directly produce clock circuit and final intermediate frequency output circuit, also comprise in addition a fractional frequency-division phase-locked loop that produces two-stage local oscillation signal, the first local oscillation signal that described voltage controlled oscillator produces is passed to first order frequency mixer, the second local oscillation signal producing is passed to second level frequency mixer, the built-in RF Voltage-Controlled Oscillator of described fractional frequency-division phase-locked loop, is locked in the needed frequency of system voltage controlled oscillator output frequency; First radio-frequency input signals carries out low noise amplification through low noise amplifier, carry out difference frequency by first order frequency mixer and the first local oscillation signal, be down to the first intermediate-freuqncy signal, the first intermediate-freuqncy signal is after band-pass filter, carry out difference frequency by second level frequency mixer and the second local oscillation signal again, produce the second intermediate frequency clock signal, be divided into again two-way, leading up to increases drive circuit and divides to sheet the sampling incoming frequency of analog to digital converter in late-class circuit and sheet, separately leads up to after variable gain amplifier and four frequency divisions are exported, to enter modulus as signal and turn device.

The phase-locked loop circuit that produces two-stage local oscillation signal is to be made up of fractional frequency-division phase-locked loop and RF Voltage-Controlled Oscillator.Fractional frequency-division phase-locked loop is compared and integer-N PLL, can greatly reduce loop frequency-dividing ratio, improves loop bandwidth, improves the output of local oscillation signal and makes an uproar mutually, optimizes the sensitivity of radio-frequency transmitter.

The conversion system of two mixer stages all adopts low local oscillator, and local oscillation signal frequency is lower than radio frequency signal frequency.The first local oscillation signal obtains the second local oscillation signal divided by 3.

In this example:

As seen from Figure 1, first radio-frequency input signals carries out low noise amplification through low noise amplifier LNA, deliver to first order frequency mixer MIXER1, carry out difference frequency with the first local oscillation signal, here adopt low local oscillator, be that local oscillation signal is lower than radio-frequency input signals, signal after difference frequency is the first intermediate-freuqncy signal IF1, IF1 delivers to second level frequency mixer MIXER2 as the input signal of the second frequency conversion after band pass filter IF1 BPF filtering, carry out difference frequency again with the second local oscillation signal of sending into MIXER2, here still adopt low local oscillator, then by MIXER2 output difference frequency signal, be divided into again two-way, leading up to increases drive circuit and divides to sheet the sampling incoming frequency of analog to digital converter in late-class circuit and sheet, separately lead up to after variable gain amplifier and four frequency divisions are exported and enter analog to digital converter as final intermediate-frequency.In figure, RFinput is radio-frequency input signals, and LO1 is the local oscillator input signal of first order frequency mixer MIXER1, and IF1 is the first intermediate frequency output signal, and LO2 is the local oscillator input signal of second level frequency mixer MIXER2, and IF2 is the final intermediate frequency output signal in the second level.

The frequency conversion of two mixer stages all adopts low local oscillator, and LO1 signal frequency is lower than RFinput signal frequency, and LO2 signal frequency is lower than the first intermediate-freuqncy signal IF1 frequency.Adopt the mode of low local oscillator can improve the noiseproof feature of fractional phase lock loop, also can save extra power consumption.Because the first intermediate-freuqncy signal frequency is higher, the mirror image interference signal of this receiver can well be suppressed.

As seen from Figure 2, this radio-frequency transmitter adopts double conversion structure, the input by two local oscillation signals as frequency mixer, and the first local oscillation signal carries out three frequency division and obtains the second local oscillation signal.

As seen from Figure 3, can directly use double conversion structure generation clock circuit, for the outer clock of late-class circuit of sheet and the sample frequency of on-chip circuit.

As seen from Figure 4, the signal of final intermediate frequency output signal after by double conversion carries out four frequency division generations again, is re-used as signal and sends into ADC and change output.

As seen from Figure 5, two local oscillation signals are produced by a fractional frequency-division phase-locked loop, and the second local oscillation signal is undertaken obtaining after three frequency division by the first local oscillator.

As seen from Figure 6, the signal flow graph of fractional frequency-division phase-locked loop is that the output signal fout of voltage controlled oscillator VCO, through dual-modulus prescaler PRESCALER, delivers to sigma-delta decimal frequency divider, the comparison clock signal producing after fractional frequency division and reference clock signal f _invia phase frequency detector PFD phase difference output, by charge pump CP, series inductance, and low pass filter LPF, convert voltage signal to again, controls VCO and produce the needed frequency signal of circuit.Fractional frequency-division phase-locked loop is compared and integer-N PLL, can greatly reduce loop frequency-dividing ratio, improves loop bandwidth, improves the output of local oscillation signal and makes an uproar mutually, optimizes the sensitivity of radio-frequency transmitter.

As seen from Figure 7, the charge pump output rear class series inductance of fractional frequency-division phase-locked loop, then the loop filter being formed by RC element of connecting.Can reduce like this fractional stray being caused by incoming frequency, optimize more total phase error of output frequency.

As seen from Figure 8, Big Dipper RDSS satellite navigation system radio-frequency transmitter of the present utility model only needs a RF Voltage-Controlled Oscillator VCO and a fractional frequency-division phase-locked loop PLL just can realize twice mixing, and directly both can produce the required clock of subsequent conditioning circuit by the structure of double conversion, also can further produce the desired final intermediate-frequency of system.This overlaps voltage controlled oscillator and two cover phase-locked loops than needs two, the traditional Big Dipper RDSS satellite navigation system radio-frequency transmitter that also needs other clock generation circuit to form has been saved a lot of circuit, both avoided the phase mutual interference between multiple voltage controlled oscillators, reduce again circuit quantity, greatly reduced system power dissipation and cost.∑-Δ module of decimal frequency divider has adopted the mechanism of over-sampling, make signal noise broadening in larger frequency band, so just reduce the noise in letter band, use the quantized noise shaping mechanism of multistage sigma-delta further letter in-band noise part to be moved to high frequency band simultaneously, use again series inductance and traditional RC low pass filter of rear class, just can curb most noise, wherein introduce inductance series connection charge pump, can eliminate introduced by incoming frequency spuious, comprise that decimal low frequency and high frequency are spuious, thereby the making an uproar and greatly improved mutually of fractional phase lock loop.Thereby utilize this local oscillator generation circuit, can greatly improve the signal to noise ratio of radio-frequency transmitter, the performance index such as sensitivity and dynamic range.

It is as follows that the sigma-delta decimal frequency divider of the technical program is realized fractional frequency division concrete grammar:

If

for the mean value of decimal, by the mode sequence of sigma-delta decimal frequency divider Dynamic Generation and integral frequency divisioil value phase and generation;

equal k/2 ⁿ, k is the numerator value of decimal, n is the figure place of accumulator in decimal frequency divider;

Total frequency dividing ratio of fractional phase lock loop circuit is fout=fin (M _b+ k/2 ⁿ), M _brepresent integral frequency divisioil value.

The principle of described sigma-delta decimal frequency divider device is as follows:

Quantizing noise linear model (as shown in Figure 9):

Noise power: Pe=△ ²/ 12, △ is for quantizing stepping length;

The difference contribution (as Figure 10 (a) and Figure 10 (b) shown in) of same quantization noise power under general sampling and over-sampling mode: sample mode, noise all drops in signal band; Under over-sampling mode, noise section drops in signal band;

Noise power spectral density: $N_e\left(f\right)={{\mathrm{<figure-callout\; id="2"\; label="S\; e"\; filenames="HDA00002065429300032.png,HDA00002065429300033.png"\; state="\{\{state\}\}">S</figure-callout>}}_e}^2=\frac{{\mathrm{\&Delta;}}^2}{12}\frac{1}{f_s},$

Signal in-band noise:

for over-sampling rate OSR(Oversampling Ratio), if over-sampling rate improves 2 times, letter in-band noise can reduce 3dB, approximately improves 0.5dB in precision.

Quantized noise shaping principle (as shown in figure 11):

Signal transfer function: $\mathrm{STF}\left(z\right)=\frac{Y\left(z\right)}{U\left(z\right)}=\frac{H\left(z\right)}{1+H\left(z\right)}$

Noise transmission function: $\mathrm{NTF}\left(z\right)=\frac{Y\left(z\right)}{E\left(z\right)}=\frac{1}{1+H\left(z\right)}$

STF (z) is all-pass inband signaling, and NTF (z) is high communication number.Letter in-band noise is shaped tremendously high frequency district.

Single order sigma-delta and noise analysis following (with reference to Figure 12):

$H\left(z\right)=\frac{z^{-1}}{1-z^{-1}},$ $\mathrm{STF}=\frac{H\left(z\right)}{1+H\left(z\right)}=z^{-1},$ $\mathrm{NTF}=\frac{1}{1+H\left(z\right)}=1-z^{-1},$ $z=e^{\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HDA00002065429300032.png,HDA00002065429300033.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;f}/f_s}$

$\mathrm{NTF}\left(f\right)=1-e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HDA00002065429300032.png,HDA00002065429300033.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;f}/f_s}=\sin \left(\frac{\mathrm{\&pi;f}}{f_s}\right)\&times;2j\&times;e^{-\mathrm{j\&pi;f}/f_s},$ $\left|\mathrm{NTF}\left(f\right)\right|=2\sin \left(\frac{\mathrm{\&pi;f}}{f_s}\right)$

In letter band, quantization noise power is:

$P_e={\&Integral;}_{-f_B}^{f_B}\left(\frac{{\mathrm{\&Delta;}}^2}{12}\frac{1}{f_s}\right){\left|\mathrm{NTF}\left(f\right)\right|}^2\mathrm{df}\&cong;\frac{{\mathrm{\&Delta;}}^2{\mathrm{\&pi;}}^2}{36}{\left(\frac{2f_B}{f_s}\right)}^3=\frac{{\mathrm{\&Delta;}}^2{\mathrm{\&pi;}}^2}{36{\left(\mathrm{OSR}\right)}^3}$

Along with the raising of over-sampling rate, in letter band, quantization noise power can reduce.

Second order sigma-delta and noise analysis following (with reference to Figure 13):

Y=[(X-Y)H ₁-Y]H ₂+E，Y=z ^-1X+(1-z ^-1) ²E

NTF(f)＝(1-z ^-1) ²， $\left|\mathrm{NTF}\left(f\right)\right|={4\mathrm{<figure-callout\; id="2"\; label="sin"\; filenames="HDA00002065429300032.png,HDA00002065429300033.png"\; state="\{\{state\}\}">sin</figure-callout>}}^2\frac{\mathrm{\&pi;f}}{f_s}$

$P_e={\&Integral;}_{-f_B}^{f_B}\left(\frac{{\mathrm{\&Delta;}}^2}{12}\frac{1}{f_s}\right){\left|4{\sin }^2(\mathrm{\&pi;f}/f_s)\right|}^2\mathrm{df}\&cong;\frac{{\mathrm{\&Delta;}}^2{\mathrm{\&pi;}}^4}{60{\left(\mathrm{OSR}\right)}^5}$

Along with the raising of sigma-delta exponent number, in letter band, quantization noise power can reduce.

Along with the raising of sigma-delta exponent number, signal to noise ratio snr also can be further improved simultaneously, as shown in figure 14:

Be reflected in circuit aspect, the effect of this programme is, the sigma-delta module of decimal frequency divider has adopted the mechanism of over-sampling, make signal noise broadening in larger frequency band, so just reduce the noise in letter band, use the quantized noise shaping mechanism of multistage sigma-delta further letter in-band noise part to be moved to high frequency band, as shown in figure 15 simultaneously.

Claims (2)

1. the radio-frequency transmitter of a Big Dipper RDSS satellite navigation system, comprise radiofrequency signal receiver and local oscillation signal circuit for generating, it is characterized in that described local oscillation signal circuit for generating comprises phase-locked loop circuit and three frequency division frequency divider, this three frequency division frequency divider is connected to the output of phase-locked loop circuit;

Described radiofrequency signal receiver comprises low noise amplifier, two mixer stages and corresponding filter, variable gain amplifier, automatic gain control circuit, four frequency division frequency dividers, driver buffer and analog to digital converter; The input of described low noise amplifier receives external radio-frequency signal; The output of low noise amplifier connects the signal input part of first order frequency mixer; The signal output part of first order frequency mixer connects the signal input part of second level frequency mixer by corresponding filter; The signal output part of second level frequency mixer is divided into two paths of signals output after by corresponding filter, and a road output signal is successively by entering analog to digital converter as the output signal of digital to analog converter after variable gain amplifier and four frequency division frequency dividers; Another road output signal is further divided into two-way output after drive circuit by increasing, respectively as the sampling incoming frequency of analog to digital converter in the clock of the outer late-class circuit of sheet and sheet;

The local oscillator input of first order frequency mixer directly connects the output of phase-locked loop circuit; The local oscillator input of second level frequency mixer connects the signal output part of three frequency division frequency divider;

Described phase-locked loop circuit is fractional phase lock loop circuit, and it comprises digital frequency phase detector PFD, charge pump CP, inductance, low pass filter, voltage controlled oscillator VCO, high frequency dual-modulus prescaler PRESCALER and ∑-⊿ decimal frequency dividers;

The high-frequency signal of described voltage controlled oscillator output carries out pre-frequency division through high frequency dual-modulus prescaler, obtain can intermediate frequency process digital signal; This digital signal is sent into ∑-⊿ decimal frequency dividers, obtains comparison clock signal after fractional frequency division; The reference clock signal f of this comparison clock signal and clock output circuit input _inas two input signals of phase frequency detector; These two input signals obtain the phase signal between them through phase frequency detector, and this phase signal obtains the voltage corresponding with phase signal through charge pump, inductance and low pass filter successively; This voltage, as the control voltage of voltage controlled oscillator, carrys out the phase error of compensated voltage controlled oscillator, and in the time that phase error is less than setting, phase-locked loop keeps the lock-out state of dynamic equilibrium, and the now output of voltage controlled oscillator is the output signal of phase-locked loop circuit.

2. the radio-frequency transmitter of Big Dipper RDSS satellite navigation system according to claim 1, is characterized in that described low pass filter is the RC passive ring filter being made up of RC passive component.

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