CN113037307B - Satellite receiver chip and satellite receiver system - Google Patents
Satellite receiver chip and satellite receiver system Download PDFInfo
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- CN113037307B CN113037307B CN202010139660.3A CN202010139660A CN113037307B CN 113037307 B CN113037307 B CN 113037307B CN 202010139660 A CN202010139660 A CN 202010139660A CN 113037307 B CN113037307 B CN 113037307B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/1851—Systems using a satellite or space-based relay
- H04B7/18515—Transmission equipment in satellites or space-based relays
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The utility model provides a satellite receiver chip, especially relates to a satellite receiver chip that high accuracy GNSS receiver used, includes clock phase-locked loop and multichannel parallel radio frequency receiving channel, the clock phase-locked loop respectively with reference frequency and multichannel parallel radio frequency receiving channel links to each other, every way the bandwidth and the central frequency of parallel radio frequency receiving channel can be disposed, wherein, multichannel parallel radio frequency receiving channel divide into two sets ofly, every group all includes at least one way parallel radio frequency receiving channel, and the first group is used for receiving GNSS satellite signal, and the second group is used for receiving SBAS satellite correction signal in the parallel radio frequency receiving channel. The receiver satellite receiver chip can simultaneously realize full frequency point GNSS signal receiving and SBAS signal receiving, can reduce the number of used radio frequency chips and the number of discrete devices/modules, and is beneficial to realizing the miniaturization, high integration and low power consumption of the GNSS receiver.
Description
Technical Field
The present invention relates to a satellite receiver chip, and more particularly, to a satellite receiver chip used in a high-precision GNSS receiver and a satellite receiver system.
Background
With the beginning of gradually providing services by beidou and galileo, more and more satellite navigation frequencies and signals can be provided for use, and the reception of multiple signal frequencies provides challenges for receivers of the current traditional technology, and the requirements of high integration, miniaturization, low power consumption and low cost on receivers of new technology are strong. The method is influenced by various aspects such as satellite navigation errors, user positions and the like, a part of areas such as valleys with complex terrain cannot achieve an ideal navigation and positioning effect only depending on GNSS, and meanwhile, in fields with special requirements on navigation performance, such as aviation and other fields, the navigation and positioning services with corresponding requirements cannot be completed by singly using the GNSS. Based on the above reasons, a series of navigation enhancement systems including Satellite Based Augmentation System (Satellite Based Augmentation System) have been developed, and the assistance of the enhancement System is matched with the use of GNSS, so that the navigation performance such as positioning accuracy of GNSS is further improved, and the special positioning service requirements in different areas and different fields are met. The SBAS system can provide a navigation function with lower cost and higher availability for the field of aviation and navigation, and brings huge economic and social benefits.
A satellite-based augmentation system (SBAS) carries a satellite navigation augmentation signal transponder through a geostationary orbit (GEO) satellite, can broadcast various correction information such as ephemeris error, satellite clock error, ionospheric delay and the like to a user, and realizes improvement of positioning accuracy of an original satellite navigation system.
Currently, SBAS systems have been established globally, such as the Wide Area Augmentation System (WAAS) in the united states, the russian differential correction and monitoring System (SDCM), the European Geostationary Navigation Overlay Service (EGNOS) in europe, the japanese multi-function satellite-based augmentation system (MSAS), and the indian GPS-assisted geostationary orbit augmentation navigation system (GAGAN). In the civil and commercial field, a plurality of SBAS systems are also established.
The high-precision solution realized based on the GNSS and assisted by inertial navigation and SBAS technologies can improve the positioning precision and reliability, and is characterized by global all-weather work, high positioning and direction finding precision and multiple functions and wide application.
The GNSS receiver generally consists of three functional modules, namely radio frequency front end processing, baseband digital signal processing and positioning navigation operation. The front-end radio frequency circuit of the GNSS receiver is the core of the GNSS receiver, and the performance of the front-end radio frequency circuit of the GNSS receiver determines the performance of the whole receiver.
As shown in fig. 1, most of the radio frequency circuits at the front end of the current GNSS receiver use a GNSS-specific radio frequency chip with a higher integration level, and the radio frequency circuit at the front end of the SBAS signal currently uses an SBAS-specific radio frequency chip or uses a discrete device module to build an analog circuit. In the prior art, GNSS and SBAS signals are received, independent double chips or multi-chip multi-discrete modules are used for receiving the signals, and at least two special radio frequency chips and external discrete devices or discrete modules are required.
The GNSS radio frequency chip amplifies and filters GNSS signals, mixes the signals with local oscillation signals generated by a local oscillator, down-converts the signals into IF (intermediate frequency) signals, and converts the intermediate frequency signals into digital intermediate frequency signals through analog/digital conversion by combining with Automatic Gain Control (AGC). And outputting the analog intermediate frequency or digital intermediate frequency signal to a baseband chip. After the SBAS radio frequency chip amplifies and filters the SBAS signal, the SBAS radio frequency chip mixes the signal with a local oscillator signal generated by a local oscillator and then down-converts the signal into an IF (intermediate frequency) signal, and then the IF signal is converted into a digital intermediate frequency signal through analog/digital conversion by combining with Automatic Gain Control (AGC). And outputting the analog or digital intermediate frequency signal to a baseband chip.
In the case of non-ideal chip integration, the two chips need to add discrete modules such as filters, phase-locked loops and the like externally to complete the function of front-end radio frequency processing. The use of multiple chips and multiple discrete modules has the disadvantages of large volume, high power consumption and high cost. In the prior art, radio frequency processing of the front ends of GNSS and SBAS signals can be completed simultaneously by using a plurality of chips or a plurality of external discrete modules, so that the circuit has large volume, high power consumption and high cost, and does not meet the development requirements of high integration degree miniaturization, low power consumption and low cost of a receiver. At present, no radio frequency chip with high integration can simultaneously receive GNSS satellite signals and SBAS signals.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a satellite receiver chip and a satellite receiver system.
One aspect of the invention provides a satellite receiver chip, which comprises a clock phase-locked loop and a plurality of parallel radio frequency receiving channels, wherein the clock phase-locked loop is respectively connected with a reference frequency and the plurality of parallel radio frequency receiving channels, and the bandwidth and the central frequency of each parallel radio frequency receiving channel can be configured, wherein the plurality of parallel radio frequency receiving channels are divided into two groups, each group comprises at least one parallel radio frequency receiving channel, the first group of parallel radio frequency receiving channels are used for receiving GNSS satellite signals, and the second group of parallel radio frequency receiving channels are used for receiving SBAS satellite correction signals.
Preferably, in the first set of parallel radio frequency reception channels:
each of the parallel radio frequency receiving channels comprises a low noise amplifier, a mixer, an intermediate frequency filter, a programmable gain amplifier, an automatic gain control circuit, an analog-to-digital conversion circuit and a phase-locked loop circuit, wherein,
the input end of the low noise amplifier is used for receiving the GNSS satellite signal;
the phase-locked input end of the phase-locked loop circuit is connected with the reference frequency, the first local oscillation frequency output end of the phase-locked loop circuit is connected with the first local oscillation frequency input end of the frequency mixer, and the second local oscillation frequency output end of the phase-locked loop circuit is connected with the second local oscillation frequency input end of the frequency mixer;
a first input end and a second input end of the mixer are both connected with an output end of the low noise amplifier, a first output end of the mixer is connected with a first input end of the intermediate frequency filter, and a second output end of the mixer is connected with a second input end of the intermediate frequency filter;
a first input end of the programmable gain amplifier is connected with a first output end of the intermediate frequency filter, and a second input end of the programmable gain amplifier is connected with a second output end of the intermediate frequency filter;
a first input end of the analog-to-digital conversion circuit is connected with a first output end of the programmable gain amplifier, a second input end of the analog-to-digital conversion circuit is connected with a second output end of the programmable gain amplifier, a first feedback output end of the analog-to-digital conversion circuit is connected with a first gain input end of the automatic gain control circuit, a second feedback output end of the analog-to-digital conversion circuit is connected with a second gain input end of the automatic gain control circuit, a phase-locked end of the analog-to-digital conversion circuit is connected with the clock phase-locked loop, and an output end of the analog-to-digital conversion circuit is used for being connected with the baseband chip;
and a first gain output end of the automatic gain control circuit is connected with a first amplification input end of the programmable gain amplifier, and a second gain output end of the automatic gain control circuit is connected with a second amplification input end of the programmable gain amplifier.
Preferably, for any of the first set of parallel rf receive channels:
the low noise amplifier is used for amplifying the GNSS satellite signals and outputting the GNSS satellite signals to the mixer;
the frequency mixer is used for performing down-conversion processing on the amplified GNSS satellite signal by using a first local oscillator signal and a second local oscillator signal respectively, and outputting the frequency-converted GNSS satellite signal to the intermediate frequency filter, wherein the phase-locked loop circuit is used for providing local oscillator frequencies corresponding to the first local oscillator signal and the second local oscillator signal for the frequency mixer respectively;
the intermediate frequency filter is used for filtering out an intermediate frequency GNSS satellite signal meeting the requirement from the GNSS satellite signal after frequency conversion according to the preset filter bandwidth, and outputting the intermediate frequency GNSS satellite signal to the automatic gain control circuit;
the programmable gain amplifier is used for amplifying the received intermediate frequency GNSS satellite signals, controlling the output analog intermediate frequency GNSS satellite signals to be stabilized within a preset amplitude range through the automatic gain circuit, and outputting the analog intermediate frequency GNSS satellite signals to the analog-to-digital conversion circuit;
and the analog-to-digital conversion circuit is used for carrying out digital quantization on the received analog intermediate frequency GNSS satellite signals, buffering and outputting the signals to the baseband chip for resolving.
Preferably, the intermediate frequency filter is a five-order Chebyshev structure filter, has a bandwidth of 10MHz to 40MHz, and comprises an RC module and an OP module.
Preferably, in the second set of parallel radio frequency reception channels:
each path of parallel radio frequency receiving channel comprises a low noise amplifier, a mixer, a first-stage programmable gain amplifier, an intermediate frequency band-pass filter, a second-stage programmable gain amplifier, an automatic gain control circuit, an analog-to-digital conversion circuit and a phase-locked loop circuit,
the input end of the low noise amplifier is used for receiving the SBAS satellite correction signal;
the phase-locked input end of the phase-locked loop circuit is connected with the reference frequency, the first local oscillation frequency output end of the phase-locked loop circuit is connected with the first local oscillation frequency input end of the frequency mixer, and the second local oscillation frequency output end of the phase-locked loop circuit is connected with the second local oscillation frequency input end of the frequency mixer;
a first input end and a second input end of the frequency mixer are both connected with an output end of the low noise amplifier, a first output end of the frequency mixer is connected with a first input end of the first-stage programmable gain amplifier, and a second output end of the frequency mixer is connected with a second input end of the first-stage programmable gain amplifier;
a first input end of the intermediate frequency band-pass filter is connected with a first output end of the first-stage programmable gain amplifier, and a second input end of the intermediate frequency band-pass filter is connected with a second output end of the first-stage programmable gain amplifier;
the input end of the second-stage programmable gain amplifier is connected with the output end of the intermediate frequency band-pass filter, and the output end of the second-stage programmable gain amplifier is connected with the input end of the analog-to-digital conversion circuit;
the phase-locked end of the analog-to-digital conversion circuit is connected with the clock phase-locked loop, and the output end of the analog-to-digital conversion circuit is connected with the baseband chip;
the first gain output end of the automatic gain control circuit is connected with the first amplification input end of the first-stage programmable gain amplifier, the second gain output end of the automatic gain control circuit is connected with the second amplification input end of the first-stage programmable gain amplifier, and the third gain output end of the automatic gain control circuit is connected with the amplification input end of the second-stage programmable gain amplifier.
Preferably, for any one of the second group of parallel rf receiving channels:
the low noise amplifier is used for amplifying the SBAS satellite correction signal and outputting the signal to the mixer;
the mixer performs down-conversion processing on the amplified SBAS satellite correction signal by using a first local oscillation signal and a second local oscillation signal respectively, and the frequency-converted SBAS satellite correction signal is output to the first-stage programmable gain amplifier, wherein the phase-locked loop circuit provides local oscillation frequencies corresponding to the first local oscillation signal and the second local oscillation signal for the mixer respectively;
the first-stage programmable gain amplifier is used for amplifying the SBAS satellite correction signal after frequency conversion, controlling the SBAS satellite correction signal output by the automatic gain circuit to be stabilized within a preset amplitude range, and outputting the SBAS satellite correction signal to the intermediate-frequency band-pass filter;
the intermediate frequency band-pass filter is used for filtering an intermediate frequency SBAS satellite correction signal meeting the requirement from the SBAS satellite correction signal according to the preset filter bandwidth and outputting the intermediate frequency SBAS satellite correction signal to the second-stage programmable gain amplifier;
the second-stage programmable gain amplifier is used for amplifying the intermediate frequency SBAS satellite correction signal, controlling the output analog intermediate frequency SBAS satellite correction signal to be stabilized within a preset amplitude range through the automatic gain circuit, and outputting the analog intermediate frequency SBAS satellite correction signal to the analog-to-digital conversion circuit;
and the analog-to-digital conversion circuit is used for carrying out digital quantization on the analog intermediate frequency SBAS satellite correction signal, buffering and outputting the signal to the Baseband Chip (BC) for resolving.
Preferably, the intermediate frequency band-pass filter is a complex band-pass filter with a five-order Chebyshev structure, has a bandwidth of 2MHz, and comprises an RC module, an intermediate frequency shift module, a gain control module and an OP module.
Preferably, the satellite receiver chip has an SPI serial peripheral bus interface, and the internal register of the satellite receiver chip is configured through the SPI serial peripheral bus interface, and the SPI serial peripheral bus interface includes: serial clock line, chip select signal line, data line.
Preferably, the low noise amplifier is a broadband low noise amplifier, and the bandwidth is 1.1GHz-1.7 GHz; the mixer is a passive quadrature mixer structure and consists of a Gm level, a current-driven passive switch and a transimpedance amplifier; the phase-locked frequency synthesizer of the phase-locked loop circuit is based on a phase-locked loop structure and comprises a voltage-controlled oscillator, a high-speed frequency divider, a dual-mode prescaler, a programmable counter, a phase frequency detector, a charge pump and a loop filter; the programmable counter comprises a P counter, an S counter and an R counter; and/or the presence of a gas in the gas,
the analog-to-digital conversion circuit is a 4-bit ADC with a successive approximation type structure.
In another aspect of the present invention, a satellite receiver system is provided, which includes a satellite receiver and a satellite receiver chip, wherein the satellite receiver chip employs the satellite receiver chip described above
The invention relates to a satellite receiver chip and a satellite receiver system, which are low-noise, high-integration, low-power consumption and small-volume satellite receiver chips, adopt a near-zero intermediate frequency radio frequency front-end topological structure, integrate a clock phase-locked loop and four parallel radio frequency receiving channels, can simultaneously receive full-frequency point GNSS signals and SBAS signals, can cover radio frequency signals in a frequency band of 1.1GHz-1.7GHz by four channels, and can be configured in bandwidth and central frequency of the four channels, wherein the first three parallel channels are used for receiving the GNSS satellite signals, and the fourth channel is used for receiving satellite correction parameters of the SBAS. Compared with the prior art, the invention adopts 1 radio frequency chip to simultaneously complete the receiving of GNSS satellite signals and SBAS signals, thereby reducing the number of chips, occupying the area of a PCB and reducing the cost and the power consumption.
Drawings
FIG. 1 is a schematic diagram of a conventional GNSS receiver front-end RF circuit.
Fig. 2 is a block diagram of a satellite receiver chip architecture of the present invention.
Fig. 3 is a block diagram of the first, second, and third parallel rf receiving channels of the present invention.
Fig. 4 is a block diagram of a fourth parallel rf receiving channel according to the present invention.
Fig. 5 is a block diagram of the structure of the active antenna device AANT of the present invention.
Detailed Description
In one aspect of the invention, a multichannel satellite receiver Chip RF Chip with low noise, high integration, low power consumption and small volume is provided, which can simultaneously receive GNSS signals and SBAS signals. A near-zero intermediate frequency radio frequency front end topological structure is adopted, and a clock phase-locked loop and a plurality of paths of parallel radio frequency receiving channels are integrated. The multi-channel parallel radio frequency receiving channels can cover radio frequency signals of a frequency band of 1.1GHz-1.7GHz, the bandwidth and the center frequency of the multi-channel parallel radio frequency receiving channels can be configured, the multi-channel parallel radio frequency receiving channels are divided into two groups, the first group of parallel radio frequency receiving channels are used for receiving GNSS satellite signals, and the second group of parallel radio frequency receiving channels are used for receiving SBAS satellite correction signals.
The satellite receiver chip of the embodiment integrates two groups of parallel radio frequency receiving channels, wherein one group is used for receiving GNSS satellite signals, and the other group is used for receiving SBAS satellite correction signals, so that the GNSS satellite signals and the SBAS satellite correction signals can be simultaneously received by one radio frequency chip.
The following description will be given by taking an example that the first group of parallel rf receiving channels includes three parallel rf receiving channels, and the second group of parallel rf receiving channels includes one parallel rf receiving channel, but the present invention is not limited thereto, and those skilled in the art can expand the present invention according to actual needs.
As shown in fig. 2, fig. 3, and fig. 4, the satellite receiver chip of the present invention includes a clock phase-locked loop CLK PLL and four parallel rf receiving channels CH1, CH2, CH3, and CH4, where the bandwidth and the center frequency of each parallel rf receiving channel are configurable, where the first, second, and third parallel rf receiving channels CH1, CH2, and CH3 are used to receive GNSS satellite signals, and the fourth parallel rf receiving channel CH4 is used to receive satellite correction parameters of SBAS.
The first path, the second path and the third path of the satellite receiver chip are the same as the parallel radio frequency receiving channels CH1, CH2 and CH3, and all comprise: a low noise amplifier LNA, a MIXER, an intermediate frequency filter LPF, a programmable gain amplifier PGA, an automatic gain control circuit AGC, an analog-to-digital conversion circuit ADC, and a phase locked loop circuit PLL.
Specifically, as shown in fig. 3, the input terminal of the low noise amplifier LNA is used for receiving the GNSS satellite signal. The phase-locked input end of the phase-locked loop circuit PLL is used for receiving the reference frequency, the first local oscillation frequency output end of the phase-locked loop circuit PLL is connected with the first local oscillation frequency input end of the MIXER MIXER, and the second local oscillation frequency output end of the phase-locked loop circuit PLL is connected with the second local oscillation frequency input end of the MIXER MIXER. The first input end and the second input end of the MIXER MIXER are connected with the output end of the low noise amplifier LNA, the first output end of the MIXER MIXER is connected with the first input end of the intermediate frequency filter LPF, and the second output end of the MIXER MIXER is connected with the second input end of the intermediate frequency filter LPF. A first input end of the programmable gain amplifier PGA is connected to a first output end of the intermediate frequency filter LPF, and a second input end of the programmable gain amplifier PGA is connected to a second output end of the intermediate frequency filter LPF. The first input end of the analog-to-digital conversion circuit ADC is connected with the first output end of the programmable gain amplifier PGA, the second input end of the analog-to-digital conversion circuit ADC is connected with the second output end of the programmable gain amplifier PGA, the first feedback output end of the analog-to-digital conversion circuit ADC is connected with the first gain input end of the automatic gain control circuit AGC, the second feedback output end of the analog-to-digital conversion circuit ADC is connected with the second gain input end of the automatic gain control circuit AGC, the phase locking end of the analog-to-digital conversion circuit ADC is connected with the clock phase-locked loop CLK PLL, and the output end of the analog-to-digital conversion circuit ADC is used for being connected with the baseband chip BC. A first gain output end of the automatic gain control circuit AGC is connected to a first amplification input end of the programmable gain amplifier PGA, and a second gain output end of the automatic gain control circuit AGC is connected to a second amplification input end of the programmable gain amplifier PGA.
Specifically, as shown in fig. 4, the fourth parallel rf receiving channel CH4 includes: the low noise amplifier LNA, the MIXER MIXER, the first programmable gain amplifier PGA1 and the second programmable gain amplifier PGA2, the intermediate frequency band pass filter BPF, the automatic gain control circuit AGC, the analog-to-digital conversion circuit ADC and the phase-locked loop circuit PLL.
In particular, as shown in fig. 4, the input of the low noise amplifier LNA is used to receive the SBAS satellite correction signal. The phase-locked input end of the phase-locked loop circuit PLL is used for receiving the reference frequency, the first local oscillation frequency output end of the phase-locked loop circuit PLL is connected with the first local oscillation frequency input end of the MIXER MIXER, and the second local oscillation frequency output end of the phase-locked loop circuit PLL is connected with the second local oscillation frequency input end of the MIXER MIXER. The first input end and the second input end of the MIXER MIXER are both connected with the output end of the low noise amplifier LNA, the first output end of the MIXER MIXER is connected with the first input end of the first-stage programmable gain amplifier PGA1, and the second output end of the MIXER MIXER is connected with the second input end of the first-stage programmable gain amplifier PGA 1. A first input end of the intermediate frequency band-pass filter BPF is connected to a first output end of the first-stage programmable gain amplifier PGA1, and a second input end of the intermediate frequency band-pass filter BPF is connected to a second output end of the first-stage programmable gain amplifier PGA 1. The input end of the second-stage programmable gain amplifier PGA2 is connected to the output end of the intermediate frequency band-pass filter BPF, and the output end of the second-stage programmable gain amplifier PGA2 is connected to the input end of the analog-to-digital conversion circuit ADC. And the phase-locked end of the analog-to-digital conversion circuit ADC is connected with the clock phase-locked loop CLK PLL, and the output end of the analog-to-digital conversion circuit ADC is used for being connected with the baseband chip BC. A first gain output end of the automatic gain control circuit AGC is connected to a first amplification input end of the first-stage programmable gain amplifier PGA1, a second gain output end of the automatic gain control circuit AGC is connected to a second amplification input end of the first-stage programmable gain amplifier PGA1, and a third gain output end of the automatic gain control circuit AGC is connected to an amplification input end of the second-stage programmable gain amplifier PGA 2.
The common local oscillation frequencies of the first path, the second path, the third path and the fourth path of parallel radio frequency receiving channels CH1, CH2, CH3 and CH4 are 1584MHz, 1192MHz, 1242MHz and 1545MHz respectively, and the common local oscillation frequencies can receive full-frequency satellite signals, including signals of GPS, Galileo, BeiDou, GLONASS, QZSS and IRNSS and partial SBAS signals which are simultaneously received in parallel. The common frequency point configuration of each channel can be shown in table 1 below:
TABLE 1 common frequency point allocation for each channel
It is understood that, in addition to the configuration in table 1, the common frequency point configuration for each channel may also be configured by those skilled in the art according to actual needs.
In addition, the main GNSS signal frequency points supported by the satellite receiver chip of the present invention are shown in table 2 below:
TABLE 2 Primary GNSS signal frequency points supported by satellite receiver chip
As can be seen from table 2, the satellite receiver chip provided by the present invention can receive full frequency point satellite signals by means of multiple parallel rf receiving channels, and can simultaneously receive GPS, Galileo, BeiDou, GLONASS, QZSS, IRNSS, and partial SBAS signals in parallel.
The satellite receiver chip of the invention has an SPI serial peripheral bus interface, and the internal register of the satellite receiver chip is configured through the SPI serial peripheral bus interface, and the SPI serial peripheral bus interface comprises: serial clock line SCLK, chip select signal line CS, data lines SADI, SADO.
Referring to fig. 5, the present invention receives satellite signals through an active antenna assembly AANT. Fig. 5 shows the active antenna device AANT connected to the first parallel rf receiving channel CH1, and the active antenna devices AANT connected to the second, third and fourth parallel rf receiving channels CH2, CH3 and CH4 respectively have the same structure.
The active antenna comprises a receiving antenna ANT, a pre-low noise amplifier P-LNA and a pre-band-pass filter P-BPF. The receiving antenna ANT transforms the received electromagnetic wave signals emitted by the satellite into voltage or current signals, which are weak and noise-doped. The voltage or current signal is amplified by a pre-low noise amplifier P-LNA, and then is filtered by a pre-band pass filter P-BPF to remove noise and interference outside a satellite wave band. And the GNSS radio frequency signal and the SBAS radio frequency signal processed by the pre-low noise amplifier P-LNA and the pre-band pass filter P-BPF enter a radio frequency chip.
Referring to fig. 3, for any one of the first, second, and third parallel rf receiving channels CH1, CH2, and CH3, the specific structure is as follows:
GNSS satellite signals are input into the low noise amplifier LNA for amplification and then output to the MIXER MIXER;
the MIXER MIXER performs down-conversion processing on the received GNSS satellite signal by using a first local oscillation signal LO _ I and a second local oscillation signal LO _ Q, and the signal after frequency conversion is output to the LPF;
the phase-locked loop circuit PLL provides local oscillation frequencies of the first local oscillation signal LO _ I and the second local oscillation signal LO _ Q, and default 10MHz crystal oscillator input is provided;
the intermediate frequency filter LPF filters out useful intermediate frequency signals according to the set filter bandwidth and outputs the useful intermediate frequency signals to the automatic gain control circuit PGA;
the PGA amplifies the received intermediate frequency signal, controls the output analog intermediate frequency signal to be stabilized in a set amplitude range through the AGC, and outputs the analog intermediate frequency signal to the ADC;
the analog-to-digital conversion circuit ADC performs digital quantization on the received analog intermediate frequency signal, and the analog intermediate frequency signal is buffered and output to the baseband chip BC for resolving.
Referring to fig. 4, for the fourth parallel rf receiving channel CH4, the specific structure is:
after an SBAS radio-frequency signal is input to the low-noise amplifier LNA for amplification, the SBAS radio-frequency signal is output to the MIXER MIXER;
the MIXER MIXER performs down-conversion processing on the received SBAS radio-frequency signal by using a first local oscillation signal LO _ I and a second local oscillation signal LO _ Q, and the frequency-converted signal is output to the first-stage programmable gain amplifier PGA 1;
the phase-locked loop PLL circuit provides local oscillation frequencies of the first local oscillation signal LO _ I and the second local oscillation signal LO _ Q;
the first-stage programmable gain amplifier PGA1 amplifies the received signal, controls the output signal to be stabilized within a set amplitude range through the automatic gain circuit AGC, and outputs the signal to the intermediate frequency band pass filter BPF.
The intermediate frequency band-pass filter BPF filters out useful intermediate frequency signals according to the set filter bandwidth, and outputs the useful intermediate frequency signals to the second-stage programmable gain amplifier PGA 2;
the second-stage programmable gain amplifier PGA2 amplifies the received single-ended signal, controls the output analog intermediate frequency signal to be stabilized within a set amplitude range through an automatic gain circuit AGC, and outputs the analog intermediate frequency signal to the analog-to-digital conversion circuit ADC;
the analog-to-digital conversion circuit ADC performs digital quantization on the received analog intermediate frequency signal, and the analog intermediate frequency signal is buffered and output to the baseband chip BC for resolving.
The LNA is a broadband LNA with the bandwidth of 1.1GHz-1.7 GHz; the MIXER MIXER is of a passive quadrature MIXER structure and consists of a Gm level, a current-driven passive switch and a transimpedance amplifier TIA; the phase-locked frequency synthesizer of the phase-locked loop circuit PLL is based on a phase-locked loop structure and comprises a voltage-controlled oscillator VCO, a high-speed frequency divider, a dual-mode prescaler, a programmable counter, a phase frequency detector PFD, a charge pump CP and a loop filter LPF; the programmable counters comprise a P counter, an S counter and an R counter.
The LPF is a five-order Chebyshev structure filter, has the bandwidth of 10 MHz-40 MHz, and comprises an RC module and an OP module.
The intermediate frequency band-pass filter BPF is a complex band-pass filter with a five-order Chebyshev structure, has a bandwidth of 2MHz, and comprises an RC module, an intermediate frequency shift module, a gain control module and an OP module.
The analog-to-digital converter ADC is a programmable 4-bit ADC with a successive approximation type structure, and the sampling clock frequency is 20 MHz-110 MHz.
In another aspect of the present invention, a satellite receiver system is provided, which includes a satellite receiver and a satellite receiver chip, and the structure of the processing chip can refer to the satellite receiver chip described above, which is not described herein again.
The satellite receiver system of the present embodiment has the above-mentioned satellite receiver chip, which integrates two sets of parallel rf receiving channels, wherein one set is used for receiving GNSS satellite signals, and the other set is used for receiving SBAS satellite correction signals, so that one rf chip can be used to simultaneously receive GNSS satellite signals and SBAS satellite correction signals.
The present invention is illustrated in detail by the above examples, but the present invention is not limited to the above detailed procedures and compositions. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are merely illustrative of the principles of the invention, but that various changes and modifications may be made without departing from the spirit and scope of the invention, which fall within the scope of the invention as claimed.
Claims (9)
1. A satellite receiver chip, characterized by: the device comprises a clock phase-locked loop and a plurality of parallel radio frequency receiving channels, wherein the clock phase-locked loop is respectively connected with a reference frequency and the plurality of parallel radio frequency receiving channels, and the bandwidth and the central frequency of each parallel radio frequency receiving channel can be configured;
in the first set of parallel radio frequency receive channels:
each of the parallel radio frequency receiving channels comprises a low noise amplifier, a mixer, an intermediate frequency filter, a programmable gain amplifier, an automatic gain control circuit, an analog-to-digital conversion circuit and a phase-locked loop circuit, wherein,
the input end of the low noise amplifier is used for receiving the GNSS satellite signal;
the phase-locked input end of the phase-locked loop circuit is connected with the reference frequency, the first local oscillation frequency output end of the phase-locked loop circuit is connected with the first local oscillation frequency input end of the frequency mixer, and the second local oscillation frequency output end of the phase-locked loop circuit is connected with the second local oscillation frequency input end of the frequency mixer;
a first input end and a second input end of the mixer are both connected with an output end of the low noise amplifier, a first output end of the mixer is connected with a first input end of the intermediate frequency filter, and a second output end of the mixer is connected with a second input end of the intermediate frequency filter;
a first input end of the programmable gain amplifier is connected with a first output end of the intermediate frequency filter, and a second input end of the programmable gain amplifier is connected with a second output end of the intermediate frequency filter;
a first input end of the analog-to-digital conversion circuit is connected with a first output end of the programmable gain amplifier, a second input end of the analog-to-digital conversion circuit is connected with a second output end of the programmable gain amplifier, a first feedback output end of the analog-to-digital conversion circuit is connected with a first gain input end of the automatic gain control circuit, a second feedback output end of the analog-to-digital conversion circuit is connected with a second gain input end of the automatic gain control circuit, a phase-locked end of the analog-to-digital conversion circuit is connected with the clock phase-locked loop, and an output end of the analog-to-digital conversion circuit is used for being connected with the baseband chip;
and a first gain output end of the automatic gain control circuit is connected with a first amplification input end of the programmable gain amplifier, and a second gain output end of the automatic gain control circuit is connected with a second amplification input end of the programmable gain amplifier.
2. The satellite receiver chip of claim 1, wherein for any of a first set of the parallel radio frequency receive channels:
the low noise amplifier is used for amplifying the GNSS satellite signal and outputting the amplified GNSS satellite signal to the mixer;
the frequency mixer is used for performing down-conversion processing on the amplified GNSS satellite signal by using a first local oscillator signal and a second local oscillator signal respectively, and outputting the frequency-converted GNSS satellite signal to the intermediate frequency filter, wherein the phase-locked loop circuit is used for providing local oscillator frequencies corresponding to the first local oscillator signal and the second local oscillator signal for the frequency mixer respectively;
the intermediate frequency filter is used for filtering out intermediate frequency GNSS satellite signals meeting the preset requirement from the GNSS satellite signals after frequency conversion according to the preset filter bandwidth, and outputting the intermediate frequency GNSS satellite signals to the automatic gain control circuit;
the programmable gain amplifier is used for amplifying the received intermediate frequency GNSS satellite signals, stabilizing the analog intermediate frequency GNSS satellite signals output by the automatic gain control circuit within a preset amplitude range, and outputting the analog intermediate frequency GNSS satellite signals to the analog-to-digital conversion circuit;
and the analog-to-digital conversion circuit is used for carrying out digital quantization on the received analog intermediate frequency GNSS satellite signals, buffering and outputting the signals to the baseband chip for resolving.
3. The satellite receiver chip of claim 1, wherein the if filter is a five-order chebyshev filter with a bandwidth of 10MHz to 40MHz, and comprises RC and OP modules.
4. The satellite receiver chip of claim 1, wherein in the second set of parallel radio frequency receive channels:
each path of parallel radio frequency receiving channel comprises a low noise amplifier, a frequency mixer, a first-stage programmable gain amplifier, an intermediate frequency band-pass filter, a second-stage programmable gain amplifier, an automatic gain control circuit, an analog-to-digital conversion circuit and a phase-locked loop circuit; wherein the content of the first and second substances,
the input end of the low noise amplifier is used for receiving the SBAS satellite correction signal;
the phase-locked input end of the phase-locked loop circuit is connected with the reference frequency, the first local oscillation frequency output end of the phase-locked loop circuit is connected with the first local oscillation frequency input end of the frequency mixer, and the second local oscillation frequency output end of the phase-locked loop circuit is connected with the second local oscillation frequency input end of the frequency mixer;
a first input end and a second input end of the frequency mixer are both connected with an output end of the low noise amplifier, a first output end of the frequency mixer is connected with a first input end of the first-stage programmable gain amplifier, and a second output end of the frequency mixer is connected with a second input end of the first-stage programmable gain amplifier;
a first input end of the intermediate frequency band-pass filter is connected with a first output end of the first-stage programmable gain amplifier, and a second input end of the intermediate frequency band-pass filter is connected with a second output end of the first-stage programmable gain amplifier;
the input end of the second-stage programmable gain amplifier is connected with the output end of the intermediate frequency band-pass filter, and the output end of the second-stage programmable gain amplifier is connected with the input end of the analog-to-digital conversion circuit;
the phase-locked end of the analog-to-digital conversion circuit is connected with the clock phase-locked loop, and the output end of the analog-to-digital conversion circuit is connected with the baseband chip;
the first gain output end of the automatic gain control circuit is connected with the first amplification input end of the first-stage programmable gain amplifier, the second gain output end of the automatic gain control circuit is connected with the second amplification input end of the first-stage programmable gain amplifier, and the third gain output end of the automatic gain control circuit is connected with the amplification input end of the second-stage programmable gain amplifier.
5. The satellite receiver chip of claim 4, wherein for any of the second set of parallel radio frequency receive channels:
the low noise amplifier is used for amplifying the SBAS satellite correction signal and outputting the signal to the mixer;
the mixer performs down-conversion processing on the amplified SBAS satellite correction signal by using a first local oscillation signal and a second local oscillation signal respectively, and the frequency-converted SBAS satellite correction signal is output to the first-stage programmable gain amplifier, wherein the phase-locked loop circuit provides local oscillation frequencies corresponding to the first local oscillation signal and the second local oscillation signal for the mixer respectively;
the first-stage programmable gain amplifier is used for amplifying the SBAS satellite correction signal after frequency conversion, stabilizing the SBAS satellite correction signal output by the automatic gain control circuit within a preset amplitude range, and outputting the SBAS satellite correction signal to the intermediate-frequency band-pass filter;
the intermediate frequency band-pass filter is used for filtering an intermediate frequency SBAS satellite correction signal meeting the requirement from the SBAS satellite correction signal according to the preset filter bandwidth and outputting the intermediate frequency SBAS satellite correction signal to the second-stage programmable gain amplifier;
the second-stage programmable gain amplifier is used for amplifying the intermediate frequency SBAS satellite correction signal, stabilizing the analog intermediate frequency SBAS satellite correction signal output by the automatic gain control circuit within a preset amplitude range, and outputting the analog intermediate frequency SBAS satellite correction signal to the analog-to-digital conversion circuit;
and the analog-to-digital conversion circuit is used for carrying out digital quantization on the analog intermediate frequency SBAS satellite correction signal, buffering and outputting the signal to the baseband chip for resolving.
6. The satellite receiver chip of claim 4, wherein the if band-pass filter is a complex band-pass filter of five-order Chebyshev structure, has a bandwidth of 2MHz, and comprises an RC module, an if shift module, a gain control module, and an OP module.
7. The satellite receiver chip according to any one of claims 1 to 6, wherein the low noise amplifier is a broadband low noise amplifier having a bandwidth of 1.1GHz to 1.7 GHz; the mixer is a passive quadrature mixer structure and consists of a Gm level passive switch driven by current and a transimpedance amplifier; the phase-locked frequency synthesizer of the phase-locked loop circuit is based on a phase-locked loop structure and comprises a voltage-controlled oscillator, a high-speed frequency divider, a dual-mode prescaler, a programmable counter, a phase frequency detector, a charge pump and a loop filter; the programmable counter comprises a P counter, an S counter and an R counter; and/or the presence of a gas in the gas,
the analog-to-digital conversion circuit is a 4-bit ADC with a successive approximation type structure.
8. The satellite receiver chip according to any one of claims 1 to 6, wherein the satellite receiver chip has an SPI serial peripheral bus interface through which internal registers of the satellite receiver chip are configured, the SPI serial peripheral bus interface comprising: serial clock line, chip select signal line, data line.
9. A satellite receiver system comprising a satellite receiver and a satellite receiver chip, wherein the satellite receiver chip employs the satellite receiver chip of any one of claims 1 to 8.
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