CN102881781B - Light emitting diode and forming method thereof - Google Patents
Light emitting diode and forming method thereof Download PDFInfo
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- CN102881781B CN102881781B CN201110273185.XA CN201110273185A CN102881781B CN 102881781 B CN102881781 B CN 102881781B CN 201110273185 A CN201110273185 A CN 201110273185A CN 102881781 B CN102881781 B CN 102881781B
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- semiconductor layer
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- emitting diode
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 108
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 239000004744 fabric Substances 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 3
- 239000002002 slurry Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 7
- 238000000605 extraction Methods 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- -1 argon ion Chemical class 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- AKJVMGQSGCSQBU-UHFFFAOYSA-N zinc azanidylidenezinc Chemical compound [Zn++].[N-]=[Zn].[N-]=[Zn] AKJVMGQSGCSQBU-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- Led Devices (AREA)
Abstract
The invention provides a light emitting diode and a forming method thereof. The method comprises the steps of firstly, sequentially forming a first semiconductor layer, an active layer and a second semiconductor layer on a substrate, wherein the electrical property of the first semiconductor layer is opposite to that of the second semiconductor layer. Then, a trench is formed through the second semiconductor layer, the active layer and a portion of the first semiconductor layer to define a stacked structure between the trenches. And forming a planarization layer on the first semiconductor layer and the second semiconductor layer to fill the trench, and forming a hard mask pattern on the planarization layer. The hard shielding pattern is provided with a shielding area and an opening area, and the opening area corresponds to the groove. And performing oblique ion implantation to pass through the opening region, so that the side wall of the first semiconductor layer is provided with a doped region, and then removing the hard shielding pattern and the planarization layer. After removing the doped region, a cavity is formed.
Description
Technical field
The present invention relates to a kind of light-emitting diode and its formation method, particularly relate to its side wall construction.
Background technology
As shown in Figure 1, common LED chip is by substrate 10, semiconductor layer 11, active layers 13, forms with semiconductor layer 15 storehouse, and has smooth sidewall surfaces.Above-mentioned semiconductor layer 11 with 15 electrical contrary.Semiconductor layer 11 and 15 has weld pad 17 respectively to be electrically connected to external circuit.The light that smooth sidewall surfaces can allow active layers 13 send produces total reflection phenomenon, and then reduces the light extraction efficiency of LED chip.For solving the problem, dry ecthing or wet etch method can be adopted to form the LED chip of undercut shape, as shown in Figure 2.Though undercut construction wide at the top and narrow at the bottom can increase the light extraction efficiency of LED chip, part active layers 13 can be destroyed and deteriorated components performance.
In sum, need new LED chip structure and corresponding formation method at present badly, solve the total reflection problem that smooth sidewall surfaces causes.
Summary of the invention
One embodiment of the invention provides a kind of formation method of light-emitting diode, comprising: sequentially formed the first semiconductor layer, active layers, with the second semiconductor layer on substrate, and the first semiconductor layer and the second semiconductor layer is electrical contrary; Formed groove through the second semiconductor layer, active layers, with part first semiconductor layer, to define stack architecture between groove; Form planarization layer and fill up groove on the first semiconductor layer and the second semiconductor layer; Form hard shielding pattern on planarization layer, hard shielding pattern has blind zone and open region, and open region respective grooves; Carrying out oblique ion cloth plants through open region, makes the sidewall of the first semiconductor layer have doped region; Remove hard shielding pattern and planarization layer; And remove doped region, to form pothole.
One embodiment of the invention provides a kind of light-emitting diode, comprising: substrate; First semiconductor layer is positioned on substrate, and the first semiconductor layer has first area and second area, and the thickness of first area is greater than the thickness of second area; Pothole, is positioned at the sidewall of the first area of the first semiconductor layer; Luminescent layer, is positioned on the first area of this first semiconductor layer; And second semiconductor layer, be positioned on luminescent layer, and the first semiconductor layer and the second semiconductor layer is electrical contrary.
Accompanying drawing explanation
Fig. 1-2 is in prior art, the cutaway view of light-emitting diode;
Fig. 3 A, 4A, 5A, 6A, 7A, 8A, 9A, 10A and Figure 11 are in embodiments of the invention, the processing procedure cutaway view of light-emitting diode; And
Fig. 3 B, 4B, 5B, 6B, 7B, 8B, 9B, 10B are the top view of the structure of Fig. 3 A, 4A, 5A, 6A, 7A, 8A, 9A, 10A respectively.
Reference numeral:
10: substrate;
11,15: semiconductor layer;
11A: the Part I of semiconductor layer 11;
11B: the Part II of semiconductor layer 11;
13: active layers;
17: weld pad;
41: groove;
51: planarization layer;
61: firmly shield pattern;
61A: blind zone;
61B: open region;
81: doped region;
91: protective layer;
100: pothole;
110: light-emitting diode.
Embodiment
As shown in Figure 3A, substrate 10 is first provided.Substrate 10 can be sapphire substrate, silicon substrate or silicon carbide substrate.Then sequentially form semiconductor layer 11, active layers 13 and semiconductor layer 15 on substrate 10, generation type can be epitaxy.Semiconductor layer 11 with 15 electrical contrary, when semiconductor layer 11 is N-shaped, semiconductor layer 15 is p-type, and vice versa.In an embodiment of the present invention, semiconductor layer 11 is the gallium nitride layer of N-shaped, and semiconductor layer 15 is the gallium nitride layer of p-type, and active layers 13 is the multiple quantum trap (MQW) of InGaN/gallium nitride composition.In other embodiments, semiconductor layer 11 and 15 and active layers 13 can be other known composition, are not limited to above-mentioned composition.The thickness of semiconductor layer 11 can be greater than, equals or be less than the thickness of semiconductor layer 15.In an embodiment of the present invention, its thickness of semiconductor layer 11 of N-shaped is less than the thickness of the semiconductor layer 15 of p-type.Its top view of structure shown in Fig. 3 A as shown in Figure 3 B.
Then as shown in Figure 4 A, the semiconductor layer 11 of groove 41 through semiconductor layer 15, active layers 13 and part is formed, to define stack architecture between groove 41.The method forming groove 41 can be common micro-photographing process collocation etch process.For example, first can form screen (not shown) on semiconductor layer 15, then form photoresistance pattern on screen with micro-photographing process.Then remove not by the screen that photoresistance pattern is protected, then remove non-conductively-closed layer protection semiconductor layer 15, active layers 13, with part semiconductor layer 11.Above-mentioned etch process is preferably anisotropic etch process, such as adopts the dry ecthing of electricity slurry.Thus, stack architecture will have smooth sidewall, and avoid undercutting to damage active layers 13.Its top view of structure shown in Fig. 4 A as shown in Figure 4 B.As shown in 4A and 4B figure, semiconductor layer 11 is divided into the Part I 11A in stack architecture, with the Part II 11B exposed by groove 41.Be understandable that, although its top view of Part I 11A in diagram is rectangle, can be other figure as square, rhombus or other shape, end depends on the needs.
Then as shown in Figure 5A, planarization layer 51 is formed to the smooth property covered in the structure of Fig. 4 A.Planarization layer 51, and there is smooth upper surface.In an embodiment of the present invention, planarization layer 51 can be benzocyclobutene (BCB) as non-photosensitivity BCB resin, and its formation method can be method of spin coating.Its top view of structure shown in Fig. 5 A as shown in Figure 5 B.
Then as shown in Figure 6A, hard shielding pattern 61 is formed on planarization layer 51.Hard shielding pattern 61 is divided into blind zone 61A and open region 61B, and open region 61B respective grooves 41.The formation method of hard shielding pattern 61 can be the hard screen (not shown) that first forms flood such as metallic shield, photoresistance, oxide and if silica or zinc oxide or nitride are as after silicon nitride, then forms photoresistance pattern on hard screen with micro-photographing process.Remove afterwards not by the hard screen of photoresistance pattern covers, namely complete hard shielding pattern 61.Its top view of structure shown in Fig. 6 A as shown in Figure 6B.
Then as shown in Figure 7 A, carry out oblique ion cloth to plant.Oblique ion cloth is planted through open region 61B, makes the semiconductor layer 11 near bottom groove 41 form the doped region 81 shown in Fig. 8 A.Active layers 13 is affected, the better width being less than groove 41 of the width of open region 61B for avoiding oblique ion cloth to plant.In an embodiment of the present invention, the admixture that oblique ion disposing process adopts can be argon ion or oxonium ion etc., and oblique angle can between 5 ° to 40 °.If the oblique angle that cloth is planted is excessive, then active region 13 may be made to have doped region.If the oblique angle too small that cloth is planted, doped region 81 will be formed at the upper surface of the Part II 11B of semiconductor layer 11, but not is formed at the sidewall sections of Part I 11A near groove 41 of semiconductor layer 11.Its top view of structure shown in Fig. 7 A as shown in Figure 7 B.
Then as shown in Figure 8 A, hard shielding pattern 61 and planarization layer 51 is removed.The method removing hard shielding pattern 61 can be and uses acid or aqueous slkali wet etching.The method removing planarization layer 51 can be and uses acid or aqueous slkali wet etching.Its top view of structure shown in Fig. 8 A as shown in Figure 8 B.
Then as shown in Figure 9 A, protective layer 91 is formed on the upper surface of semiconductor layer 15.The composition of protective layer 91 can be silica (SiO
2), silicon nitride (Si
3n
4) or aluminium oxide (Al
2o
3) etc., its formation method can be plasma enhanced chemical vapor deposition, sputter as electron gun sputter (E-Gun/Sputter) or evaporation.Its top view of structure shown in Fig. 9 A as shown in Figure 9 B.
Then as shown in Figure 10 A, doped region 81 is removed.In an embodiment of the present invention, the method removing doped region 81 can be inductively electricity slurry, reactive ion etching, wet etching or above-mentioned combination.Due to semiconductor layer 15 being coated with protective layer 91, the step therefore removing doped region 81 can not have influence on the upper surface of semiconductor layer 15.It should be noted that aforementioned oblique ion cloth is planted can the lattice of deteriorated doped region 81, and the therefore identical condition that removes, when affecting the sidewall of semiconductor layer 15 with active layers 13 not significantly, can remove doped region 81 completely to form pothole 100.Be understandable that, although the pothole 100 in Figure 10 A has curved edge, also can have flattened edge, look closely the parameter that oblique ion cloth is planted.Its top view of structure shown in Figure 10 A as shown in Figure 10 B.As previously mentioned, the top view of the Part I 11A of semiconductor layer 11 can be rectangle, as shown in Figure 10 B.In an embodiment of the present invention, above-mentioned pothole 100 is on four limits of the Part I 11A being formed at rectangle.In an alternative embodiment of the invention, above-mentioned pothole 100 is only formed on the long limit of the Part I 11A of rectangle, and is not formed on the minor face of Part I 11A of rectangle, to save the cost forming pothole 100 on rectangle minor face.When the ratio of its long limit of the Part I 11A of rectangle and minor face is larger, above-mentioned forms the technology of pothole in the long limit of rectangle and more saves cost, and more can not lose light extraction efficiency.
Then as shown in figure 11, weld pad 17 is formed after removing protective layer 91 respectively in semiconductor layer 15 with on the surface of the Part II 11B of semiconductor layer 11.Then carry out cutting processing procedure, form other light-emitting diode 110.The method removing protective layer 91 can be and uses acid or aqueous slkali wet etching.The composition of weld pad 17 can be gold, silver, copper, titanium, aluminium, nickel or above-mentioned combination, and its formation method can be and uses electron gun sputter.So far completed so-called light-emitting diode, the sidewall of its semiconductor layer 11 has pothole 100 to avoid total reflection phenomenon, and then increases light extraction efficiency.On the other hand, the step forming pothole 100 can't destroy active layers 13, therefore has better components performance than existing undercut construction.
Although the present invention discloses as above with several preferred embodiment, so itself and be not used to limit the present invention, any those of ordinary skill in the field, when doing to change arbitrarily and retouching, and do not depart from the spirit and scope of the present invention.
Claims (7)
1. a formation method for light-emitting diode, comprising:
Sequentially formed one first semiconductor layer, an active layers, with one second semiconductor layer on a substrate, and this first semiconductor layer and this second semiconductor layer is electrical contrary;
Formed a groove through this second semiconductor layer, this active layers, with part this first semiconductor layer, to define a stack architecture between this groove;
Forming a planarization layer on this first semiconductor layer and this second semiconductor layer fills up this groove;
Firmly shielding pattern is on this planarization layer to form one, and this firmly shields pattern and has a blind zone and an open region, and this open region is to should groove;
Carry out an oblique ion cloth to plant through this open region, make a doped region only be formed at the sidewall of this first semiconductor layer near this channel bottom;
Remove this shielding pattern and this planarization layer firmly; And
Remove this doped region, to form a pothole.
2. the formation method of light-emitting diode according to claim 1, wherein the width of this open region is less than the width of this groove.
3. the formation method of light-emitting diode according to claim 1, the method wherein removing this doped region comprises inductively electricity slurry, reactive ion etching, wet etching or above-mentioned combination.
4. the formation method of light-emitting diode according to claim 1, after being wherein also included in the step removing this hard shielding pattern and this planarization layer, and before the step removing this doped region, forms a protective layer on this second semiconductor layer.
5. the formation method of light-emitting diode according to claim 1, wherein the top view of this stack architecture is a rectangle, and this rectangle has a long limit and a minor face, and this pothole is only positioned at this long limit.
6. a light-emitting diode, comprising:
One substrate;
One first semiconductor layer is positioned on this substrate, and this first semiconductor layer has a first area and a second area, and the thickness of this first area is greater than the thickness of this second area;
One pothole, is only positioned at the sidewall of this first area of this first semiconductor layer;
One luminescent layer, is positioned on this first area of this first semiconductor layer; And
One second semiconductor layer, is positioned on this luminescent layer, and this first semiconductor layer and this second semiconductor layer is electrical contrary.
7. light-emitting diode according to claim 6, wherein the top view of this first area of this first semiconductor layer is a rectangle, and this rectangle has a long limit and a minor face, and this pothole is only positioned at this long limit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100124881 | 2011-07-14 | ||
| TW100124881A TWI447950B (en) | 2011-07-14 | 2011-07-14 | Leds and methods for manufacturing the same |
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| Publication Number | Publication Date |
|---|---|
| CN102881781A CN102881781A (en) | 2013-01-16 |
| CN102881781B true CN102881781B (en) | 2015-02-18 |
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| CN201110273185.XA Active CN102881781B (en) | 2011-07-14 | 2011-09-15 | Light emitting diode and forming method thereof |
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| TW (1) | TWI447950B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI501419B (en) * | 2011-08-23 | 2015-09-21 | Lextar Electronics Corp | Leds and methods for manufacturing the same |
| JP7573812B2 (en) | 2021-01-13 | 2024-10-28 | 日亜化学工業株式会社 | Light emitting element |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060197094A1 (en) * | 2005-03-04 | 2006-09-07 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device, semiconductor light emitting apparatus, and method of manufacturing semiconductor light emitting device |
| TW200735398A (en) * | 2006-03-09 | 2007-09-16 | Univ Tsing Hua | Light emitting diode and the method for manufacturing the same |
| JP2009188240A (en) * | 2008-02-07 | 2009-08-20 | Sharp Corp | Method of manufacturing semiconductor light-emitting element, and semiconductor light-emitting element |
| TW201015752A (en) * | 2008-10-14 | 2010-04-16 | Ind Tech Res Inst | Light emitting diode chip and fabricating method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5256580A (en) * | 1992-04-06 | 1993-10-26 | Motorola, Inc. | Method of forming a light emitting diode |
| KR100523484B1 (en) * | 2002-11-11 | 2005-10-24 | 한국전자통신연구원 | Method for fabricating semiconductor optical devices having current-confined structure |
| US7550395B2 (en) * | 2004-11-02 | 2009-06-23 | The Regents Of The University Of California | Control of photoelectrochemical (PEC) etching by modification of the local electrochemical potential of the semiconductor structure relative to the electrolyte |
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2011
- 2011-07-14 TW TW100124881A patent/TWI447950B/en active
- 2011-09-15 CN CN201110273185.XA patent/CN102881781B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060197094A1 (en) * | 2005-03-04 | 2006-09-07 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device, semiconductor light emitting apparatus, and method of manufacturing semiconductor light emitting device |
| TW200735398A (en) * | 2006-03-09 | 2007-09-16 | Univ Tsing Hua | Light emitting diode and the method for manufacturing the same |
| JP2009188240A (en) * | 2008-02-07 | 2009-08-20 | Sharp Corp | Method of manufacturing semiconductor light-emitting element, and semiconductor light-emitting element |
| TW201015752A (en) * | 2008-10-14 | 2010-04-16 | Ind Tech Res Inst | Light emitting diode chip and fabricating method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201304182A (en) | 2013-01-16 |
| TWI447950B (en) | 2014-08-01 |
| CN102881781A (en) | 2013-01-16 |
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