CN102881781B - Light emitting diode and forming method thereof - Google Patents
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- CN102881781B CN102881781B CN201110273185.XA CN201110273185A CN102881781B CN 102881781 B CN102881781 B CN 102881781B CN 201110273185 A CN201110273185 A CN 201110273185A CN 102881781 B CN102881781 B CN 102881781B
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Abstract
本发明提供一种发光二极管与其形成方法。该方法首先依序形成第一半导体层、主动层、与第二半导体层于基板上，且第一半导体层与第二半导体层的电性相反。接着形成沟槽穿过第二半导体层、主动层、与部分第一半导体层，以定义堆栈结构于沟槽之间。之后形成平坦化层于第一半导体层与第二半导体层上并填满沟槽，再形成硬屏蔽图案于平坦化层上。硬屏蔽图案具有屏蔽区与开口区，且开口区对应沟槽。进行斜向离子布植穿过开口区，使第一半导体层的侧壁具有掺杂区后，移除硬屏蔽图案与平坦化层。在移除掺杂区后，即形成凹洞。
The present invention provides a light emitting diode and a method for forming the same. The method first sequentially forms a first semiconductor layer, an active layer, and a second semiconductor layer on a substrate, and the first semiconductor layer and the second semiconductor layer have opposite electrical properties. A trench is then formed through the second semiconductor layer, the active layer, and a portion of the first semiconductor layer to define a stack structure between the trenches. Then a planarization layer is formed on the first semiconductor layer and the second semiconductor layer to fill the trenches, and then a hard shield pattern is formed on the planarization layer. The hard shielding pattern has a shielding area and an opening area, and the opening area corresponds to the trench. After performing oblique ion implantation through the opening area so that the sidewall of the first semiconductor layer has a doping area, the hard shielding pattern and the planarization layer are removed. After the doped region is removed, a cavity is formed.
Description
技术领域technical field
本发明涉及一种发光二极管与其形成方法，尤其涉及其侧壁结构。The invention relates to a light emitting diode and its forming method, in particular to its side wall structure.
背景技术Background technique
如图1所示，常见的LED芯片是由基板10、半导体层11、主动层13、与半导体层15堆栈而成，且具有平整的侧壁表面。上述半导体层11与15的电性相反。在半导体层11及15上分别具有焊垫17以电性连接至外部电路。平整的侧壁表面会让主动层13发出的光产生全反射现象，进而降低LED芯片的光取出效率。为解决上述问题，可采用干蚀刻或湿蚀刻法形成底切形状的LED芯片，如图2所示。上宽下窄的底切结构虽可增加LED芯片的光取出效率，但会破坏部分主动层13而劣化组件效能。As shown in FIG. 1 , a common LED chip is formed by stacking a substrate 10 , a semiconductor layer 11 , an active layer 13 , and a semiconductor layer 15 , and has a flat sidewall surface. The electrical properties of the semiconductor layers 11 and 15 are opposite. There are pads 17 on the semiconductor layers 11 and 15 respectively to be electrically connected to external circuits. The flat sidewall surface will cause total reflection of the light emitted by the active layer 13, thereby reducing the light extraction efficiency of the LED chip. To solve the above problems, dry etching or wet etching can be used to form undercut LED chips, as shown in FIG. 2 . Although the undercut structure with a wide top and a narrow bottom can increase the light extraction efficiency of the LED chip, it will destroy part of the active layer 13 and degrade the performance of the component.
综上所述，目前亟需新的LED芯片结构与对应的形成方法，解决平整的侧壁表面造成的全反射问题。To sum up, there is an urgent need for new LED chip structures and corresponding forming methods to solve the problem of total reflection caused by flat sidewall surfaces.
发明内容Contents of the invention
本发明一实施例提供一种发光二极管的形成方法，包括：依序形成第一半导体层、主动层、与第二半导体层于基板上，且第一半导体层与第二半导体层的电性相反；形成沟槽穿过第二半导体层、主动层、与部分第一半导体层，以定义堆栈结构于沟槽之间；形成平坦化层于第一半导体层与第二半导体层上并填满沟槽；形成硬屏蔽图案于平坦化层上，硬屏蔽图案具有屏蔽区与开口区，且开口区对应沟槽；进行斜向离子布植穿过开口区，使第一半导体层的侧壁具有掺杂区；移除硬屏蔽图案与平坦化层；以及移除掺杂区，以形成凹洞。An embodiment of the present invention provides a method for forming a light-emitting diode, including: sequentially forming a first semiconductor layer, an active layer, and a second semiconductor layer on a substrate, and the electrical properties of the first semiconductor layer and the second semiconductor layer are opposite ; forming a trench through the second semiconductor layer, the active layer, and part of the first semiconductor layer to define a stack structure between the trenches; forming a planarization layer on the first semiconductor layer and the second semiconductor layer and filling the trench groove; forming a hard masking pattern on the planarization layer, the hard masking pattern has a shielding area and an opening area, and the opening area corresponds to the groove; performing oblique ion implantation through the opening area, so that the sidewall of the first semiconductor layer has a doped the impurity region; remove the hard mask pattern and the planarization layer; and remove the impurity region to form the cavity.
本发明一实施例提供一种发光二极管，包括：基板；第一半导体层位于基板上，第一半导体层具有第一区域与第二区域，且第一区域的厚度大于第二区域的厚度；凹洞，位于第一半导体层的第一区域的侧壁；发光层，位于该第一半导体层的第一区域上；以及第二半导体层，位于发光层上，且第一半导体层与第二半导体层的电性相反。An embodiment of the present invention provides a light emitting diode, comprising: a substrate; a first semiconductor layer located on the substrate, the first semiconductor layer has a first region and a second region, and the thickness of the first region is greater than the thickness of the second region; The hole is located on the sidewall of the first region of the first semiconductor layer; the light emitting layer is located on the first region of the first semiconductor layer; and the second semiconductor layer is located on the light emitting layer, and the first semiconductor layer and the second semiconductor layer The layers are electrically opposite.
附图说明Description of drawings
图1-2是现有技术中，发光二极管的剖视图；Figure 1-2 is a cross-sectional view of a light emitting diode in the prior art;
图3A、4A、5A、6A、7A、8A、9A、10A与图11是本发明的实施例中，发光二极管的制程剖视图；以及3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A and FIG. 11 are cross-sectional views of the process of the light emitting diode in the embodiment of the present invention; and
图3B、4B、5B、6B、7B、8B、9B、10B分别是图3A、4A、5A、6A、7A、8A、9A、10A的结构的上视图。Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are top views of the structures in Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A, respectively.
附图标记：Reference signs:
10：基板；10: Substrate;
11、15：半导体层；11, 15: semiconductor layer;
11A：半导体层11的第一部分；11A: the first part of the semiconductor layer 11;
11B：半导体层11的第二部分；11B: the second part of the semiconductor layer 11;
13：主动层；13: active layer;
17：焊垫；17: welding pad;
41：沟槽；41: Groove;
51：平坦化层；51: planarization layer;
61：硬屏蔽图案；61: hard mask pattern;
61A：屏蔽区；61A: shielded area;
61B：开口区；61B: opening area;
81：掺杂区；81: doped area;
91：保护层；91: protective layer;
100：凹洞；100: pit;
110：发光二极管。110: light emitting diode.
具体实施方式Detailed ways
如图3A所示，先提供基板10。基板10可为蓝宝石基板、硅基板、或碳化硅基板。接着依序形成半导体层11、主动层13、及半导体层15于基板10上，形成方式可为外延法。半导体层11与15的电性相反，当半导体层11为n型时，半导体层15为p型，反之亦然。在本发明一实施例中，半导体层11为n型的氮化镓层，半导体层15为p型的氮化镓层，且主动层13为氮化铟镓/氮化镓组成的多重量子井(MQW)。在其它实施例中，半导体层11与15及主动层13可为其它已知组成，并不限于上述组成。半导体层11的厚度可大于、等于、或小于半导体层15的厚度。在本发明一实施例中，n型的半导体层11其厚度小于p型的半导体层15的厚度。图3A所示的结构其上视图如图3B所示。As shown in FIG. 3A , the substrate 10 is provided first. The substrate 10 can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate. Next, the semiconductor layer 11 , the active layer 13 , and the semiconductor layer 15 are sequentially formed on the substrate 10 , and the formation method can be epitaxy. The electrical properties of the semiconductor layers 11 and 15 are opposite. When the semiconductor layer 11 is n-type, the semiconductor layer 15 is p-type, and vice versa. In an embodiment of the present invention, the semiconductor layer 11 is an n-type GaN layer, the semiconductor layer 15 is a p-type GaN layer, and the active layer 13 is a multiple quantum well composed of InGaN/GaN (MQW). In other embodiments, the semiconductor layers 11 and 15 and the active layer 13 can be other known compositions, and are not limited to the above compositions. The thickness of the semiconductor layer 11 may be greater than, equal to, or less than the thickness of the semiconductor layer 15 . In an embodiment of the present invention, the thickness of the n-type semiconductor layer 11 is smaller than that of the p-type semiconductor layer 15 . The top view of the structure shown in Figure 3A is shown in Figure 3B.
接着如图4A所示，形成沟槽41穿过半导体层15、主动层13、及部分的半导体层11，以定义堆栈结构于沟槽41之间。形成沟槽41的方法可为常见的微影制程搭配蚀刻制程。举例来说，可先形成屏蔽层(未图示)于半导体层15上，再以微影制程形成光阻图案于屏蔽层上。接着移除未被光阻图案保护的屏蔽层，再移除未被屏蔽层保护的半导体层15、主动层13、与部分的半导体层11。上述蚀刻制程较佳为非等向蚀刻制程，比如采用电浆的干蚀刻。如此一来，堆栈结构将具有平整侧壁，并避免底切损伤主动层13。图4A所示的结构其上视图如图4B所示。如第4A及4B图所示，半导体层11分为堆栈结构中的第一部分11A，与被沟槽41露出的第二部分11B。可以理解的是，虽然图示中的第一部分11A其上视图为矩形，但可为其它图形如方形、菱形、或其它形状，端视需要而定。Next, as shown in FIG. 4A , trenches 41 are formed through the semiconductor layer 15 , the active layer 13 , and part of the semiconductor layer 11 to define a stack structure between the trenches 41 . The method of forming the trench 41 can be a common lithography process combined with an etching process. For example, a shielding layer (not shown) may be formed on the semiconductor layer 15 first, and then a photoresist pattern is formed on the shielding layer by a lithography process. Then remove the shielding layer not protected by the photoresist pattern, and then remove the semiconductor layer 15 , the active layer 13 , and part of the semiconductor layer 11 not protected by the shielding layer. The above etching process is preferably an anisotropic etching process, such as dry etching using plasma. In this way, the stack structure will have flat sidewalls, and the active layer 13 will be prevented from being damaged by the undercut. The top view of the structure shown in Fig. 4A is shown in Fig. 4B. As shown in FIGS. 4A and 4B , the semiconductor layer 11 is divided into a first portion 11A in a stack structure and a second portion 11B exposed by the trench 41 . It can be understood that although the top view of the first part 11A in the figure is a rectangle, it can be in other shapes such as a square, a rhombus, or other shapes, depending on requirements.
接着如图5A所示，坦覆性地形成平坦化层51于图4A的结构上。平坦化层51，并具有平整的上表面。在本发明一实施例中，平坦化层51可为苯并环丁烯(BCB)如非光敏BCB树脂，其形成方法可为旋转涂布法。图5A所示的结构其上视图如图5B所示。Next, as shown in FIG. 5A , a planarization layer 51 is formed on the structure in FIG. 4A . The planarization layer 51 has a flat upper surface. In an embodiment of the present invention, the planarization layer 51 can be benzocyclobutene (BCB) such as non-photosensitive BCB resin, and its formation method can be a spin coating method. The top view of the structure shown in Fig. 5A is shown in Fig. 5B.
接着如图6A所示，形成硬屏蔽图案61于平坦化层51上。硬屏蔽图案61分为屏蔽区61A与开口区61B，且开口区61B对应沟槽41。硬屏蔽图案61的形成方法可为先形成整层的硬屏蔽层(未图示)如金属屏蔽、光阻、氧化物如氧化硅或氧化锌、或氮化物如氮化硅后，再以微影制程形成光阻图案于硬屏蔽层上。之后移除未被光阻图案覆盖的硬屏蔽层，即完成硬屏蔽图案61。图6A所示的结构其上视图如图6B所示。Next, as shown in FIG. 6A , a hard mask pattern 61 is formed on the planarization layer 51 . The hard masking pattern 61 is divided into a shielding area 61A and an opening area 61B, and the opening area 61B corresponds to the trench 41 . The hard mask pattern 61 can be formed by first forming a whole layer of hard mask layer (not shown) such as metal mask, photoresist, oxide such as silicon oxide or zinc oxide, or nitride such as silicon nitride, and then micro The photoresist pattern is formed on the hard mask layer by photolithography process. Afterwards, the hard mask layer not covered by the photoresist pattern is removed, that is, the hard mask pattern 61 is completed. The top view of the structure shown in Fig. 6A is shown in Fig. 6B.
接着如图7A所示，进行斜向离子布植。斜向离子布植将穿过开口区61B，使沟槽41底部附近的半导体层11形成图8A所示的掺杂区81。为避免斜向离子布植影响主动层13，开口区61B的宽度较佳小于沟槽41的宽度。在本发明一实施例中，斜向离子布植制程采用的掺质可为氩离子或氧离子等，斜向角度可介于5°至40°之间。若布植的斜向角度过大，则可能会使主动区13具有掺杂区。若布植的斜向角度过小，掺杂区81将形成于半导体层11的第二部分11B的上表面，而非形成于半导体层11的第一部分11A靠近沟槽41的侧壁部分。图7A所示的结构其上视图如图7B所示。Next, as shown in FIG. 7A , oblique ion implantation is performed. The oblique ion implantation will pass through the opening region 61B, so that the semiconductor layer 11 near the bottom of the trench 41 forms a doped region 81 as shown in FIG. 8A . In order to prevent the oblique ion implantation from affecting the active layer 13 , the width of the opening region 61B is preferably smaller than the width of the trench 41 . In an embodiment of the present invention, dopants used in the oblique ion implantation process may be argon ions or oxygen ions, etc., and the oblique angle may be between 5° and 40°. If the implanting oblique angle is too large, the active region 13 may have a doped region. If the implanting oblique angle is too small, the doped region 81 will be formed on the upper surface of the second portion 11B of the semiconductor layer 11 instead of the sidewall portion of the first portion 11A of the semiconductor layer 11 near the trench 41 . The top view of the structure shown in Fig. 7A is shown in Fig. 7B.
接着如图8A所示，移除硬屏蔽图案61与平坦化层51。移除硬屏蔽图案61的方法可为使用酸或碱溶液湿蚀刻。移除平坦化层51的方法可为使用酸或碱溶液湿蚀刻。图8A所示的结构其上视图如图8B所示。Next, as shown in FIG. 8A , the hard mask pattern 61 and the planarization layer 51 are removed. A method of removing the hard mask pattern 61 may be wet etching using an acid or alkali solution. A method of removing the planarization layer 51 may be wet etching using an acid or alkali solution. The top view of the structure shown in Fig. 8A is shown in Fig. 8B.
接着如图9A所示，形成保护层91于半导体层15的上表面上。保护层91的组成可为氧化硅(SiO2)、氮化硅(Si3N4)、或氧化铝(Al2O3)等，其形成方法可为电浆辅助化学气相沉积、溅镀如电子枪溅镀(E-Gun/Sputter)、或蒸镀。图9A所示的结构其上视图如图9B所示。Next, as shown in FIG. 9A , a protection layer 91 is formed on the upper surface of the semiconductor layer 15 . The composition of the protective layer 91 can be silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or aluminum oxide (Al 2 O 3 ), etc., and its formation method can be plasma-assisted chemical vapor deposition, sputtering such as Electron gun sputtering (E-Gun/Sputter), or evaporation. The top view of the structure shown in Fig. 9A is shown in Fig. 9B.
接着如图10A所示，移除掺杂区81。在本发明一实施例中，移除掺杂区81的方法可为感应耦合电浆、反应性离子蚀刻、湿蚀刻、或上述的组合。由于半导体层15上覆盖有保护层91，因此移除掺杂区81的步骤不会影响到半导体层15的上表面。值得注意的是，前述斜向离子布植会劣化掺杂区81的晶格，因此相同的移除条件在不大幅影响半导体层15与主动层13的侧壁的情况下，可完全移除掺杂区81以形成凹洞100。可以理解的是，虽然图10A中的凹洞100具有弧形边缘，但亦可具有平直边缘，端视斜向离子布植的参数。图10A所示的结构其上视图如图10B所示。如前所述，半导体层11的第一部分11A的上视图可为矩形，如图10B所示。在本发明一实施例中，上述凹洞100系形成于矩形的第一部分11A的四个边上。在本发明另一实施例中，上述凹洞100只形成于矩形的第一部分11A的长边上，而不形成矩形的第一部分11A的短边上，以节省在矩形短边上形成凹洞100的成本。当矩形的第一部分11A其长边与短边的比值越大时，上述只形成凹洞于矩形长边的技术越节省成本，且越不会损失光取出效率。Next, as shown in FIG. 10A , the doped region 81 is removed. In an embodiment of the invention, the method for removing the doped region 81 may be inductively coupled plasma, reactive ion etching, wet etching, or a combination thereof. Since the semiconductor layer 15 is covered with the passivation layer 91 , the step of removing the doped region 81 will not affect the upper surface of the semiconductor layer 15 . It is worth noting that the aforementioned oblique ion implantation will degrade the crystal lattice of the doped region 81, so the same removal conditions can completely remove the doped region 81 without greatly affecting the sidewalls of the semiconductor layer 15 and the active layer 13. impurity region 81 to form cavity 100 . It can be understood that although the cavity 100 in FIG. 10A has curved edges, it can also have straight edges, depending on the parameters of oblique ion implantation. The top view of the structure shown in Fig. 10A is shown in Fig. 10B. As mentioned above, the top view of the first portion 11A of the semiconductor layer 11 may be a rectangle, as shown in FIG. 10B . In an embodiment of the present invention, the above-mentioned cavity 100 is formed on four sides of the rectangular first part 11A. In another embodiment of the present invention, the above-mentioned concave hole 100 is only formed on the long side of the rectangular first part 11A, not on the short side of the rectangular first part 11A, so as to save the formation of the concave hole 100 on the rectangular short side. the cost of. When the ratio of the long side to the short side of the first rectangular portion 11A is larger, the technique of forming only the cavity on the long side of the rectangle is more cost-effective, and the light extraction efficiency will not be lost.
接着如图11所示，移除保护层91后分别形成焊垫17于半导体层15与半导体层11的第二部分11B的表面上。接着进行切割制程，形成个别的发光二极管110。移除保护层91的方法可为使用酸或碱溶液湿蚀刻。焊垫17的组成可为金、银、铜、钛、铝、镍、或上述的组合，其形成方法可为使用电子枪溅镀。至此已完成所谓的发光二极管，其半导体层11的侧壁具有凹洞100以避免全反射现象，进而增加光取出效率。另一方面，形成凹洞100的步骤并不会破坏主动层13，因此比现有的底切结构具有更佳的组件效能。Next, as shown in FIG. 11 , after removing the protective layer 91 , solder pads 17 are respectively formed on the surface of the semiconductor layer 15 and the second portion 11B of the semiconductor layer 11 . Next, a cutting process is performed to form individual light emitting diodes 110 . A method for removing the protection layer 91 may be wet etching using an acid or alkali solution. The composition of the pad 17 may be gold, silver, copper, titanium, aluminum, nickel, or a combination thereof, and its formation method may be sputtering using an electron gun. So far, the so-called light-emitting diodes have been completed. The sidewall of the semiconductor layer 11 has the cavity 100 to avoid the total reflection phenomenon, thereby increasing the light extraction efficiency. On the other hand, the step of forming the cavity 100 will not damage the active layer 13 , so it has better device performance than the existing undercut structure.
虽然本发明已以数个较佳实施例揭示如上，然其并非用以限定本发明，任何所属领域的普通技术人员，当可作任意更动与润饰，而不脱离本发明的精神和范围。Although the present invention has been disclosed above with several preferred embodiments, they are not intended to limit the present invention, and those skilled in the art can make any changes and modifications without departing from the spirit and scope of the present invention.
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| TW200735398A (en) * | 2006-03-09 | 2007-09-16 | Univ Tsing Hua | Light emitting diode and the method for manufacturing the same |
| JP2009188240A (en) * | 2008-02-07 | 2009-08-20 | Sharp Corp | Semiconductor light emitting device manufacturing method and semiconductor light emitting device |
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| TW200735398A (en) * | 2006-03-09 | 2007-09-16 | Univ Tsing Hua | Light emitting diode and the method for manufacturing the same |
| JP2009188240A (en) * | 2008-02-07 | 2009-08-20 | Sharp Corp | Semiconductor light emitting device manufacturing method and semiconductor light emitting device |
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