CN102880564A

CN102880564A - Method for supporting double 10-gigabit POS (point-of-sale) interface by FPGA (field programmable gate array)

Info

Publication number: CN102880564A
Application number: CN2012102503824A
Authority: CN
Inventors: 姚文浩; 柳胜杰; 张克功; 袁海滨; 刘小亮; 夏嵩
Original assignee: Dawning Information Industry Beijing Co Ltd
Current assignee: Dawning Information Industry Beijing Co Ltd; Dawning Information Industry Co Ltd
Priority date: 2012-07-19
Filing date: 2012-07-19
Publication date: 2013-01-16
Anticipated expiration: 2032-07-19
Also published as: CN102880564B

Abstract

The invention provides a method for supporting a double 10-gigabit POS (point-of-sale) interface by an FPGA (field programmable gate array), which is based on a PM5422 chip. The method comprises the following steps: S1) after the PM5422 chip is electrified, searching a driving program, initializing a PCIE (peripheral component interface express) interface, an ILA (integrated logic analyzer) interface and a gigabit network interface according to the driving program, and waiting for a mainboard command; S2) after the starting of the mainboard is finished, enabling a processor on the mainboard to access the PM5422 chip, and downloading a microcode to an internal processor of the PM5422 chip; S3) initializing a 10GPOS (general purpose operating system) internet access, carrying out step S4 if the initialization is correct to enter a normal working flow, and reporting a system error to a system if the initialization fails; and S4) sending the 10GPOS optical signal of a far-end router into the PM5422 to be processed by an optical module 1 or an optical module 2, and after a POS packet comprising the 10GPOS optical signal is processed into an Ethernet protocol packet by the PM5422 chip, sending the Ethernet protocol packet to FPGA through an ILA interface bus to process the data.

Description

A kind of FPGA that realizes supports the method for two 10,000,000,000 pos interfaces

Technical field

The present invention relates to the subcard of a kind of ATCA, be specifically related to the method that a kind of FPGA of realization supports two 10,000,000,000 pos interfaces.

Background technology

In the data disposable plates based on the ATCA standard, the first order of data is processed and is finished with FPGA.But the FPGA that selects can't support reception and the transmission of 10G serial signal, although can support the 10G serial signal in the FPGA of follow-up upgraded version, can't reach the linear speed of 10GPOS agreement.Therefore the invention provides the method that a kind of FPGA of realization supports two 10,000,000,000 pos interfaces, the method can be supported the linear speed of two-way 10GPOS agreement based on the PM5422 chip, can conveniently be extended for to support the non-linear speed interface of 4 road 10GPOS.

Summary of the invention

A kind of FPGA that realizes provided by the invention supports the method for two 10,000,000,000 pos interfaces, it is characterized in that, the ILA interface of FPGA on the described mainboard connects described PM5422 chip, optical module 1, optical module 2 and IIC storer are connected described PM5422 chip, mainboard is connected with described PM5422 chip by the PCIE interface, and power module connects and provides power supply to described optical module 1, optical module 2 and PM5422 chip; Described method comprises:

Step S1 transfers driver behind the described PM5422 chip power, according to the described PCIE interface of described driver initialization, described ILA interface and gigabit networking interface, waits for the mainboard order;

Step S2, after described mainboard startup was finished, the described PM5422 chip of the processor access on the mainboard was downloaded microcode in the internal processor of described PM5422 chip;

Step S3, initialization 10GPOS network interface, initialization is correct, and then execution in step S4 enters normal workflow; The initialization failure, report custom system mistake;

Step S4, the 10GPOS light signal of far-end router is sent into described PM5422 chip after by described optical module 1 or optical module 2 and is processed, the POS bag that described PM5422 chip will comprise the light signal of described 10GPOS is processed into after the Ether protocoll bag, sends to described FPGA by the ILA interface bus data are processed.

In the first preferred embodiment provided by the invention: among the described step S1, transfer driver by automatic access IIC storer behind the described PM5422 chip power.

In the second preferred embodiment provided by the invention: among the described step S2, the processor on the described mainboard is by described PCIE interface or the described PM5422 chip of gigabit networking interface accessing.

In the 3rd preferred embodiment provided by the invention: the described microcode among the described step S2 is processed the dispersion compensation, pre-/as to postemphasis and balanced problem of 10,000,000,000 network interface signals.

In the 4th preferred embodiment provided by the invention: among the described step S3, described PM5422 chip consults to determine that with the FPGA on the described mainboard width and the speed of described ILA interface, the CPU on the mainboard monitor the described 10GPOS network interface of initialization that says the word after ILA bus training between described PM5422 chip and the described FPGA is finished.

In the 5th preferred embodiment provided by the invention: described optical module 1 and optical module 2 are the XFP optical module, and light signal described in the described step S4 converts to by described optical module 1 or optical module 2 and sends into described PM5422 chip behind the XFI electric signal and process.

A kind of FPGA of realization provided by the invention supports the beneficial effect of the method for two 10,000,000,000 pos interfaces to comprise:

1, adopts the PM5422 chip to process and comprise ten thousand mbit ethernets, 10GPOS etc., and become the lower slightly ILA interface of speed to process for FPGA these interface conversion.

2, use the optical module box, make things convenient for the expansion of optical-path interface.

Description of drawings

Fig. 1 is a kind of structural drawing of realizing two 10,000,000,000 pos interfaces of FPGA support based on the PM5422 chip provided by the invention;

Fig. 2 is a kind of method flow diagram of realizing two 10,000,000,000 pos interfaces of FPGA support based on the PM5422 chip provided by the invention.

Embodiment

A kind of FPGA that realizes provided by the invention supports the method for two 10,000,000,000 pos interfaces, this implementation method is based on the PM5422 chip, its concrete structure figure as shown in Figure 1, it is characterized in that, the ILA interface of FPGA on the mainboard connects the PM5422 chip, optical module 1, optical module 2 and IIC storer are connected the PM5422 chip, and mainboard is connected with the PM5422 chip by the PCIE interface, and power module connects and provides power supply to optical module 1, optical module 2 and PM5422 chip; The PM5422 chip is double-channel multifunctional 10,000,000,000 PHY devices, he can process and comprise ten thousand mbit ethernets, 10GPOS etc., and become the lower slightly ILA interface of speed to process for FPGA these interface conversion, data communication device is crossed the XFP optical module and is entered PM5422, and section resolves, issues the FPGA processing by the ILA interface after the series of steps such as bag parsings by signal recovery, string and conversion, frame within it.

Concrete, the steps flow chart of the method comprises as shown in Figure 2:

Step S1 transfers driver behind the PM5422 chip power, according to driver initialization PCIE interface, ILA interface and gigabit networking interface, waits for the mainboard order.

Concrete, by automatic access IIC storer, the Firmware program that it is the most basic is called in inside behind this PM5422 chip power.

Step S2, after the mainboard startup was finished, the processor access PM5422 chip on the mainboard was downloaded microcode in the internal processor of PM5422 chip;

Processor on the mainboard is by PCIE interface or gigabit networking interface accessing PM5422 chip.

Microcode is processed some algorithms of 10,000,000,000 network interface problems of Signal Integrity, and integrity issue comprises dispersion compensation, pre-/as to postemphasis and balanced etc.

Step S3, initialization 10GPOS network interface, initialization is correct, and then execution in step S4 enters normal workflow; The initialization failure, report custom system mistake.

The connection of ILA interface does not need the intervention of mainboard program, and the wire jumper on the plate can arrange the mode of operation of ILA interface, and PM5422 can hold consultation with the FPGA on the mainboard automatically, determines width and the speed of ILA interface.

The PM5422 chip consults to determine that with the FPGA on the mainboard width and the speed of ILA interface, the CPU on the mainboard monitor the initialization 10GPOS network interface that says the word after ILA bus training between PM5422 chip and the FPGA is finished.The ILA bus surpasses 1S does not also have training to finish or the failure of initialization 10GPOS interface, then can report the custom system mistake.

Step S4, the 10GPOS light signal of far-end router is sent into the PM5422 chip after by optical module 1 or optical module 2 and is processed, the POS bag that the PM5422 chip will comprise the light signal of 10GPOS is processed into after the Ether protocoll bag, sends to FPGA by the ILA interface bus data are processed.

Optical module 1 and optical module 2 are the XFP optical module, and light signal converts to by optical module 1 or optical module 2 and sends into the PM5422 chip behind the XFI electric signal and process among the step S4.

Should be noted that at last: above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit, although with reference to above-described embodiment the present invention is had been described in detail, those of ordinary skill in the field are to be understood that: still can make amendment or be equal to replacement the specific embodiment of the present invention, and do not break away from any modification of spirit and scope of the invention or be equal to replacement, it all should be encompassed in the middle of the claim scope of the present invention.

Claims

1. realize that based on the PM5422 chip FPGA supports the method for two 10,000,000,000 pos interfaces for one kind, it is characterized in that, the ILA interface of FPGA on the described mainboard connects described PM5422 chip, optical module 1, optical module 2 and IIC storer are connected described PM5422 chip, mainboard is connected with described PM5422 chip by the PCIE interface, and power module connects and provides power supply to described optical module 1, optical module 2 and PM5422 chip; Described method comprises:

2. the method for claim 1 is characterized in that, among the described step S1, transfers driver by automatic access IIC storer behind the described PM5422 chip power.

3. the method for claim 1 is characterized in that, among the described step S2, the processor on the described mainboard is by described PCIE interface or the described PM5422 chip of gigabit networking interface accessing.

4. the method for claim 1 is characterized in that, the described microcode among the described step S2 is processed the dispersion compensation, pre-/as to postemphasis and balanced problem of 10,000,000,000 network interface signals.

5. the method for claim 1, it is characterized in that, among the described step S3, described PM5422 chip consults to determine that with the FPGA on the described mainboard width and the speed of described ILA interface, the CPU on the mainboard monitor the described 10GPOS network interface of initialization that says the word after ILA bus training between described PM5422 chip and the described FPGA is finished.

6. the method for claim 1 is characterized in that, described optical module 1 and optical module 2 are the XFP optical module, and light signal described in the described step S4 converts to by described optical module 1 or optical module 2 and sends into described PM5422 chip behind the XFI electric signal and process.