CN102880564B

CN102880564B - A kind of method realizing double 10,000,000,000 pos interfaces of FPGA support

Info

Publication number: CN102880564B
Application number: CN201210250382.4A
Authority: CN
Inventors: 姚文浩; 柳胜杰; 张克功; 袁海滨; 刘小亮; 夏嵩
Original assignee: Dawning Information Industry Beijing Co Ltd
Current assignee: Dawning Information Industry Beijing Co Ltd; Dawning Information Industry Co Ltd
Priority date: 2012-07-19
Filing date: 2012-07-19
Publication date: 2016-12-21
Anticipated expiration: 2032-07-19
Also published as: CN102880564A

Abstract

The present invention provides a kind of and realizes the method that FPGA supports double 10,000,000,000 pos interfaces, and described implementation method is based on PM5422 chip；Including: step S1, described PM5422 chip is transferred driver after powering on, is initialized described PCIE interface, described ILA interface and gigabit networking interface according to described driver, waits mainboard order；Step S2, after described mainboard has started, the processor on mainboard accesses described PM5422 chip, in download microcode to the internal processor of described PM5422 chip；Step S3, initializes 10GPOS network interface, initializes correct, then perform step S4, enter normal workflow；Initialize unsuccessfully, report custom system mistake；Step S4, the 10GPOS optical signal of far-end router processes by sending into described PM5422 chip after described optical module 1 or optical module 2, after the POS bag of the optical signal comprising described 10GPOS is processed into Ether protocoll bag by described PM5422 chip, it is sent to described FPGA by ILA interface bus and data are processed.

Description

A kind of method realizing double 10,000,000,000 pos interfaces of FPGA support

Technical field

The present invention relates to the subcard of a kind of ATCA, be specifically related to a kind of method realizing double 10,000,000,000 pos interfaces of FPGA support.

Background technology

Data based on ATCA standard process in plate, and the first order of data processes and uses FPGA to complete.But select FPGA cannot support reception and the transmission of 10G serial signal, although can support 10G in the FPGA of follow-up upgraded version Serial signal, but it is unable to reach the linear speed of 10GPOS agreement.Therefore the present invention provides one to realize FPGA and supports double 10,000,000,000 The method of pos interface, the method based on PM5422 chip, can be supported the linear speed of two-way 10GPOS agreement, can facilitate It is extended for supporting 4 road 10GPOS non-linear speed interface.

Summary of the invention

A kind of method realizing double 10,000,000,000 pos interfaces of FPGA support that the present invention provides, it is characterised in that on described mainboard The ILA interface of FPGA connects described PM5422 chip, and optical module 1, optical module 2 and IIC memorizer connect described PM5422 Chip, mainboard is connected with described PM5422 chip by PCIE interface, and power module connects and provides power to described optical module 1, optical module 2 and PM5422 chip；Described method includes:

Step S1, described PM5422 chip is transferred driver after powering on, is initialized described PCIE according to described driver Interface, described ILA interface and gigabit networking interface, wait mainboard order；

Step S2, after described mainboard has started, the processor on mainboard accesses described PM5422 chip, downloads microcode and arrives In the internal processor of described PM5422 chip；

Step S3, initializes 10GPOS network interface, initializes correct, then perform step S4, enter normal workflow；Just Beginningization failure, reports custom system mistake；

Step S4, the 10GPOS optical signal of far-end router is by sending into described PM5422 after described optical module 1 or optical module 2 Chip processes, described PM5422 chip the POS bag of the optical signal comprising described 10GPOS is processed into Ether protocoll bag with After, it is sent to described FPGA by ILA interface bus and data are processed.

In the first preferred embodiment that the present invention provides: in described step S1, described PM5422 chip is visited by automatic after powering on Ask IIC that driver transferred by memorizer.

In the second preferred embodiment that the present invention provides: in described step S2, the processor on described mainboard passes through described PCIE PM5422 chip described in interface or gigabit networking interface accessing.

In the third preferred embodiment that the present invention provides: the described microcode in described step S2 processes 10,000,000,000 network interface signals Dispersion compensation, pre-/problem of postemphasising and equalizing.

In the 4th preferred embodiment that the present invention provides: in described step S3, described PM5422 chip is with on described mainboard FPGA consults to determine that width and the speed of described ILA interface, the CPU on mainboard monitor described PM5422 chip and described ILA bus between FPGA says the word after having trained and initializes described 10GPOS network interface.

In the 5th preferred embodiment that the present invention provides: described optical module 1 and optical module 2 are XFP optical module, described step S4 Described in optical signal be converted into the XFI signal of telecommunication by described optical module 1 or optical module 2 after send into described PM5422 chip and carry out Process.

A kind of FPGA of realization that the present invention provides supports that the beneficial effect of the method for double 10,000,000,000 pos interfaces includes:

1, use PM5422 chip to process and include ten thousand mbit ethernets, 10GPOS etc., and become speed lower slightly these interface conversion ILA interface for FPGA process.

2, use optical module box, facilitate the expansion of optical-path interface.

Accompanying drawing explanation

A kind of structure chart realizing double 10,000,000,000 pos interfaces of FPGA support based on PM5422 chip that Fig. 1 provides for the present invention；

A kind of method flow realizing double 10,000,000,000 pos interfaces of FPGA support based on PM5422 chip that Fig. 2 provides for the present invention Figure.

Detailed description of the invention

A kind of method realizing double 10,000,000,000 pos interfaces of FPGA support that the present invention provides, this implementation method is based on PM5422 core Sheet, its concrete structure figure is as shown in Figure 1, it is characterised in that, the ILA interface of the FPGA on mainboard connects PM5422 chip, Optical module 1, optical module 2 and IIC memorizer connect PM5422 chip, and mainboard is by PCIE interface with PM5422 chip even Connecing, power module connects and provides power to optical module 1, optical module 2 and PM5422 chip；PM5422 chip is the dual pathways Multifunctional multi million PHY device, he can process and include ten thousand mbit ethernets, 10GPOS etc., and these interface conversion are become speed Lower slightly ILA interface is for FPGA process, and data enter PM5422 by XFP optical module, extensive by signal therein FPGA process is issued by ILA interface after the series of steps such as again, serioparallel exchange, frame parsing, Packet analyzing.

Concrete, the steps flow chart of the method is as in figure 2 it is shown, include:

Step S1, PM5422 chip is transferred driver after powering on, is initialized PCIE interface, ILA interface according to driver With gigabit networking interface, wait mainboard order.

Concrete, this PM5422 chip accesses IIC memorizer, the Firmware program most basic by it by automatic after powering on Call in inside.

Step S2, after mainboard has started, the processor on mainboard accesses PM5422 chip, download microcode to PM5422 In the internal processor of chip；

Processor on mainboard passes through PCIE interface or gigabit networking interface accessing PM5422 chip.

Microcode processes some algorithms of 10,000,000,000 network interface problems of Signal Integrity, integrity issue include dispersion compensation, pre-/ Postemphasis and equilibrium etc..

Step S3, initializes 10GPOS network interface, initializes correct, then perform step S4, enter normal workflow；Just Beginningization failure, reports custom system mistake.

The connection of ILA interface need not mainboard program intervention, and the wire jumper on plate can arrange the mode of operation of ILA interface, PM5422 Automatically can hold consultation with the FPGA on mainboard, determine width and the speed of ILA interface.

PM5422 chip consults to determine width and the speed of ILA interface with the FPGA on mainboard, and the CPU on mainboard monitors ILA bus between PM5422 chip and FPGA says the word after having trained and initializes 10GPOS network interface.ILA bus surpasses Cross 1S and the most do not trained or initialized the failure of 10GPOS interface, then can report custom system mistake.

Step S4, the 10GPOS optical signal of far-end router is carried out by sending into PM5422 chip after optical module 1 or optical module 2 Process, after the POS bag of the optical signal comprising 10GPOS is processed into Ether protocoll bag by PM5422 chip, by ILA interface Bus is sent to FPGA and processes data.

Optical module 1 and optical module 2 are XFP optical module, and in step S4, optical signal is converted into by optical module 1 or optical module 2 Send into PM5422 chip after the XFI signal of telecommunication to process.

Finally should be noted that: above example is only in order to illustrate that technical scheme is not intended to limit, although reference The present invention has been described in detail by above-described embodiment, those of ordinary skill in the field it is understood that still can to this Invention detailed description of the invention modify or equivalent, and without departing from spirit and scope of the invention any amendment or etc. With replacing, it all should be contained in the middle of scope of the presently claimed invention.

Claims

1. one kind realizes the method that FPGA supports double 10,000,000,000 pos interfaces, it is characterised in that described method base In PM5422 chip；The ILA interface described PM5422 chip of connection of the FPGA on mainboard, optical module 1, Optical module 2 and IIC memorizer connects described PM5422 chip, and mainboard is by PCIE interface and described PM5422 Chip connects, and power module connects and provide power to described optical module 1, optical module 2 and PM5422 chip； Described method includes:

Step S1, described PM5422 chip transfers driver after powering on, initial according to described driver Change described PCIE interface, described ILA interface and gigabit networking interface, wait mainboard order；

Step S2, after described mainboard has started, the processor on mainboard accesses described PM5422 chip, Download microcode in the internal processor of described PM5422 chip；

Step S3, initializes 10GPOS network interface, initializes correct, then perform step S4, enter normal work Make flow process；Initialize unsuccessfully, report custom system mistake；

Step S4, the 10GPOS optical signal of far-end router is by sending into after described optical module 1 or optical module 2 Described PM5422 chip processes, and described PM5422 chip will comprise the POS of the optical signal of described 10GPOS After bag is processed into Ether protocoll bag, it is sent to described FPGA by ILA interface bus and data are processed.

2. the method for claim 1, it is characterised in that in described step S1, described PM5422 Chip transfers driver by access IIC memorizer automatically after powering on.

3. the method for claim 1, it is characterised in that in described step S2, on described mainboard Processor is by PM5422 chip described in described PCIE interface or gigabit networking interface accessing.

4. the method for claim 1, it is characterised in that at the described microcode in described step S2 Manage the dispersion compensation of 10,000,000,000 network interface signals, pre-/problem of postemphasising and equalizing.

5. the method for claim 1, it is characterised in that in described step S3, described PM5422 Chip consults to determine width and the speed of described ILA interface, the CPU on mainboard with the FPGA on described mainboard Monitor the initialization that says the word after the ILA bus between described PM5422 chip and described FPGA has been trained Described 10GPOS network interface.

6. the method for claim 1, it is characterised in that described optical module 1 and optical module 2 are XFP Optical module, optical signal described in described step S4 is converted into XFI electricity by described optical module 1 or optical module 2 Send into described PM5422 chip after signal to process.