CN102868646B - Asynchronous transfer mode (ATM) logic design simulation method, and platform, and equipment - Google Patents

Abstract

The invention discloses an asynchronous transfer mode (ATM) logic design simulation method, an ATM logic design simulation platform, and equipment. The platform comprises a path generating module, a path scheduling module and a verification module, wherein the path generating module is used for forming a downlink ATM cell corresponding to incentive data according to an incentive data configuration file and a downlink permanent virtual circuit (PVC) path information configuration file; the path scheduling module is used for transmitting the downlink ATM cell corresponding to the incentive data to a module to be tested for the module to be tested to receive and process according to the scheduling time in a scheduling configuration file; and the verification module is used for acquiring downlink result data which are processed by the module to be tested and correspond to the incentive data, and comparing the incentive data with the downlink result data to verify receiving logic of the module to be tested. By the technical scheme, the efficiency of simulation and verification on an ATM logic design is improved.

Description

Asynchronous transfer mode logical design emulation mode, platform and equipment

Technical field

The present invention relates to logical simulation technology, particularly relate to a kind of asynchronous transfer mode (Asynchronous Transfer Mode, referred to as ATM) logical design emulation mode, platform and equipment.

Background technology

ATM is one is packet switching and the multiplex technique of unit with cell (English for cell), general connection-oriented transmission mode can be provided for multiple business, be applicable to local area network (LAN) and wide area network, there is high-speed data transmission rate and can support that polytype such as sound, data, fax, real-time video communicate with image.Current ATM logic can be passed through field programmable gate array (Field Programmable Gate Array, referred to as FPGA) and realize.FPGA is the novel high-performance programmable chip that a kind of integrated level is very high, its internal circuit function is programmable (English is Programmable), hardware description language (Hardware Description Language can be passed through, referred to as HDL) and special designs instrument, realize extremely complicated circuit function therein flexibly.

FPGA simulating, verifying technology is the important component part that FPGA develops link, and the function realized mainly for FPGA carries out logic checking.At present to the emulation of the ATM logical design that FPGA realizes mainly: the designer of ATM logic writes test case respectively according to each test point, compiling is carried out to test case and generates verification environment, then verify the logic of design in the verification environment generated, simulating, verifying efficiency is lower.

Summary of the invention

The invention provides a kind of asynchronous transfer mode logical design emulation mode, platform and equipment, in order to improve the efficiency of ATM logical design being carried out to simulating, verifying.

One aspect of the present invention provides a kind of asynchronous transfer mode logical design emulation mode, comprising:

Passage generation module, for according to the data configuration item in excited data configuration file, excited data in generating test use case, according to PVC header information corresponding with described excited data in descending fixing virtual circuit PVC channel information configuration file, burst process is carried out to described excited data, form the descending ATM cell that described excited data is corresponding, described data configuration item comprises data length, data content and data amount check;

Channel scheduling module, is connected with described passage generation module, for according to the scheduling time in scheduling configuration file, descending ATM cell corresponding for described excited data is sent to module to be tested, carries out reception process for described module to be tested;

Authentication module, for descending result data corresponding with described excited data after obtaining described resume module to be tested, compares described excited data and described descending result data, to verify the receive logic of described module to be tested.

The present invention provides a kind of asynchronous transfer mode logical design emulation platform on the other hand, comprising:

According to the data configuration item in excited data configuration file, excited data in generating test use case, according to PVC header information corresponding with described excited data in descending fixing virtual circuit PVC channel information configuration file, burst process is carried out to described excited data, form the descending ATM cell that described excited data is corresponding, described data configuration item comprises data length, data content and data amount check;

According to the scheduling time in scheduling configuration file, descending ATM cell corresponding for described excited data is sent to module to be tested, carry out reception process for described module to be tested;

Descending result data corresponding with described excited data after obtaining described resume module to be tested, compares described excited data and described descending result data, to verify the receive logic of described module to be tested.

Another aspect of the invention provides a kind of equipment, comprises asynchronous transfer mode logical design emulation platform provided by the invention.

Asynchronous transfer mode logical design emulation mode provided by the invention, platform and equipment, according to the excited data in excited data configuration file generating test use case, next carrying out burst process according to PVC channel information configuration file to excited data forms descending ATM cell, according to the scheduling time in scheduling configuration file, descending ATM cell is sent to module to be tested, reception process is carried out for module to be tested, by being compared by the excited data of the result data after resume module to be tested and generation, realize the checking treating the receive logic of test module.Technical solution of the present invention is mainly based on various configuration file, based on the excited data in configuration file generating test use case and configuration file also provides control logic needed for simulation process, therefore test case directly can be run and emulate in translation and compiling environment, realize the checking treating the receive logic of test module, need not emulate at every turn all test case be compiled, improve and treat the efficiency that test module carries out logical simulation.

Accompanying drawing explanation

The structural representation of the ATM logical design emulation platform that Fig. 1 provides for one embodiment of the invention;

Mapping relations between the content that the data flow that Fig. 2 provides for one embodiment of the invention, data configuration item and data configuration item comprise;

Mapping relations between the PVC header information that the data flow that Fig. 3 provides for one embodiment of the invention, every bar data flow are corresponding and the content that PVC header information comprises;

The structural representation of the ATM logical design emulation platform that Fig. 4 provides for another embodiment of the present invention;

A kind of form schematic diagram of the abnormal configuration file of mistake that Fig. 5 provides for one embodiment of the invention;

The form of the excited data that Fig. 6 provides for one embodiment of the invention;

The ATM cell storage inside mode schematic diagram that Fig. 7 provides for one embodiment of the invention;

The HEC synchronized state transition diagram that Fig. 8 provides for one embodiment of the invention;

The flow chart of the ATM logical design emulation mode that Fig. 9 provides for one embodiment of the invention;

The flow chart of the ATM logical design emulation mode that Figure 10 provides for another embodiment of the present invention.

Embodiment

The structural representation of the ATM logical design emulation platform that Fig. 1 provides for one embodiment of the invention.As shown in Figure 1, the platform of the present embodiment comprises: passage generation module 11, channel scheduling module 12 and authentication module 13.

Wherein, passage generation module 11, for according to the data configuration item in excited data configuration file, excited data in generating test use case, according to descending fixing virtual circuit (Permanent Virtual Circuit, referred to as PVC) PVC header information corresponding with excited data in channel information configuration file, carries out burst process to excited data, forms the descending ATM cell that excited data is corresponding.Wherein, data configuration item comprises data length, data content and data amount check.

Excited data configuration file in the present embodiment is mainly used in controlling the length of excited data in every bar data flow, content and number, every bar data flow can support at most 32 data configuration items, can be implemented in the combination for same data flow configuration several data length, content etc. in same emulation cycle.

Data flow described in various embodiments of the present invention corresponds to PVC passage, forms a data flow by the excited data of a PVC channel transfer.In the present embodiment, the excited data that passage generation module generates can be the excited data in single PVC passage, and which kind of situation no matter also can be the excited data in many PVC passage, wherein, be, identical to the processing procedure of each excited data.

Fig. 2 gives the mapping relations between content that a kind of data flow, data configuration item and data configuration item comprise.Comprise altogether 512 data flow in fig. 2, for stream 0-flows 511,512 configuration files that data flow is corresponding, configure 0-PVC_DT configuration 511 referred to as PVC_DT; Every bar data flow comprises 32 data configuration items, referred to as configuration 0-configuration 31; Each data configuration item includes but not limited to following information:

FLOW_ID: No. ID, data flow;

NUM: the number of the excited data that corresponding data stream sends;

LEN_MODE: the long patterns of excited data in configuration data stream, has fixing (FIX), increases progressively (INC), random (RDM) Three models;

LEN_MAX: the maximum of excited data length in configuration data stream;

LEN_MIN: the minimum value of excited data length in configuration data stream;

DT_MOD: the content model of excited data in configuration data stream, has FIX, INC, RDM Three models;

DT_MAX: the maximum of excited data content in configuration data stream;

DT_MIN: the minimum value of excited data content in configuration data stream.

Descending PVC channel information configuration file in the present embodiment is mainly used in the PVC header information storing PVC passage corresponding to every bar data flow, there is provided head (header) information that sending direction every bar data flow is corresponding, for the encapsulation of cell (cells) data.PVC header information mainly comprises generic flow control (the Generic Flow Control of No. ID, data flow and its correspondence, referred to as GFC), Virtual Path Identifier (Virtual Path Identifier, referred to as VPI), virtual path identifiers (Virtual Connection Identifier, referred to as VCI), cell abandons the information such as priority (Cell Loss Priority, referred to as CLP).As shown in Figure 3, PVC header information corresponding to every bar data flow is the PVC configuration in Fig. 3 to mapping relations between the PVC header information that data flow, every bar data flow are corresponding and the content that PVC header information comprises.VPI and VCI that every bar data flow is corresponding unique, VPI and VCI can unique identification PVC passages, and every bar PVC passage has a channel number.

Channel scheduling module 12, is connected with passage generation module 11, for according to the scheduling time in scheduling configuration file, descending ATM cell corresponding for excited data is sent to module to be tested, carries out reception process for module to be tested.

What the scheduling configuration file in the present embodiment was mainly used in the ATM cell controlling each PVC passage sends speed, i.e. scheduling time inter.The present embodiment can provide service (the Constant Bit Rate of fixed rate to adopt, referred to as CBR) scheduling mode is example, scheduling configuration file can be described as CBR_SLOT configuration file, channel scheduling module 12 is according to CBR_SLOT configuration file, strict is indicated to higher level's module (i.e. passage generation module 11) according to fixing scheduling time inter release scheduling, obtain descending ATM cell, realize the object of pressing the descending ATM cell speed of PVC channel management.Here scheduling time inter is relevant with sending the total bandwidth of excited data, and physical relationship is: scheduling the time interval=cell size/outlet bandwidth.Such as, based on SDH (Synchronous Digital Hierarchy) (Synchronous Digital Hierarchy, referred to as SDH) ATM(should be ATM over SDH) effective outlet bandwidth is 149.76Mbps, ATM cell size is 53*8bit, then scheduling time inter is 53*8bit/149.76Mbps=2.8us.Further, in scheduling configuration file, the storage width of memory scheduling time needs to determine according to final transmission rate, and the larger storage width of final transmission rate just will be deepened accordingly.Relation is between the two as follows: storage width=outlet bandwidth/minimum scheduling granularity.Such as, the effective outlet bandwidth of ATM over SDH is 149.76Mbps, and minimum scheduling granularity is 64k, then storage width is 149.76Mbps/64K=2340.

Concrete, descending ATM cell corresponding for excited data, by corresponding PVC passage, is sent to module to be tested by channel scheduling module 12.

Authentication module 13, for descending result data corresponding with above-mentioned excited data after obtaining resume module to be tested, compares above-mentioned excited data and descending result data, to verify the receive logic of module to be tested.

After module to be tested receives descending ATM cell, can carry out reception process, such as header error controls the process such as (Header Error Correction, referred to as HEC) is synchronous, alarm, restructuring, verification, result after last output processing, i.e. descending result data.This descending result data is corresponding with the excited data that passage generation module 11 generates.If the processing logic of module to be tested is correct, then descending result data or satisfied certain relation identical with excited data, otherwise, then not identical or do not meet described relation.Based on this, above-mentioned excited data and descending result data, by descending result data corresponding with above-mentioned excited data after acquisition resume module to be tested, compare, can realize the object of the receive logic verifying module to be tested by authentication module 13.

As shown in Figure 1, module to be tested is connected with channel scheduling module 12 and authentication module 13 respectively.Wherein, channel scheduling module 12 can be described as data stream interface with the interface of model calling to be tested, the ATM logical design emulation platform that the present embodiment provides is by providing simple data stream interface, can dock with different modules to be tested easily, complete different phase, the test assignment of such as integration testing, module testing etc.

Optionally, due to the agreement that ATM is transport layer, so the ATM logical design emulation platform that the present embodiment provides is except can the logical design (i.e. to be tested module) relevant to ATM carry out except independent test, can also to connecting relevant PHY layer technology, such as SDH, Ethernet (Ethernet, referred to as ETH) model etc., integration testing is carried out to module to be measured.

The ATM logical design emulation platform that the present embodiment provides, mainly based on various configuration file, based on the excited data in configuration file generating test use case and configuration file also provides control logic needed for simulation process, therefore make test case directly can run in translation and compiling environment to emulate, realize the checking treating the receive logic of test module, need not emulate at every turn all test case be compiled, improve and treat the efficiency that test module carries out logical simulation.Wherein, the ATM logical design emulation platform of the present embodiment provides one translation and compiling environment.

The structural representation of the ATM logical design emulation platform that Fig. 4 provides for another embodiment of the present invention.The present embodiment is based on realization embodiment illustrated in fig. 1, and as shown in Figure 4, the emulation platform of the present embodiment also comprises: passage generation module 11, channel scheduling module 12 and authentication module 13, and each module also has the function of description embodiment illustrated in fig. 1.

In the present embodiment, channel scheduling module 12 is also for before sending to module to be tested in the descending ATM cell that excited data is corresponding, controlling descending ATM cell corresponding to excited data according to the abnormal configuration file of mistake occurs abnormal, to realize the checking of the exception handling ability treating test module.Wherein, the abnormal configuration file of mistake comprises exception control time and Exception Type.

The abnormal configuration file of mistake in the present embodiment is mainly used in providing ATM cell in control imitation process that abnormal required information occurs, such as, various exception control on exception control time and ATM cell aspect, 32 configuration items can be supported at most, the combination of multiple abnormal behaviour in same emulation cycle can be supported in.Wherein, the abnormal configuration file of mistake can referred to as CTL configuration file.A kind of form of the abnormal configuration file of mistake as shown in Figure 5, this wrong abnormal configuration file comprises 32 configuration items, be respectively configuration 0-configuration 31,512 data flow and correspond to these 32 configuration items, specifically which bar data flow which kind of configuration item corresponding is depending on emulation demand.As shown in Figure 5, in the abnormal configuration file of mistake, every bar configuration item includes but not limited to following information:

Time_s: effect time started, in units of clock;

Time_e: effect end time, in units of clock; Wherein, the time from time_s to time_e forms the above-mentioned exception control time, and namely during this period of time, channel scheduling module 12 controls descending ATM cell corresponding to excited data and occurs abnormal.

Mod: set the abnormal operation pattern in above-mentioned time_s and the time_e time, concrete pattern includes but not limited to following several:

S_ERR: force header (English is cells header) to verify single-bit (bit) mistake;

M_ERR: force cells header to verify many bit mistake;

CRC_ERR: force ATM AAL_5 frame cyclic redundancy check (CRC) code (Cyclic Redundancy Check, referred to as CRC) check errors;

LEN_ERR: force ATM AAL_5 frame length (Length, referred to as LEN) mistake;

Configuration file imports module 16.

Optionally, a kind of implementation structure of passage generation module 11 as shown in Figure 4, comprising: data configuration file acquiring unit 111, group bag unit 112, sharding unit 113, header acquiring unit 114 and data capture unit 115.

Wherein, data configuration file acquiring unit 111, is connected with group bag unit 112, for obtaining above-mentioned excited data configuration file from the first configuration array, excited data configuration file is sent to group bag unit 112.Optionally, the data configuration item in excited data configuration file can be sent to group bag unit 112 by data configuration file acquiring unit 111 one by one, to realize object excited data configuration file being sent to group bag unit 112.Based on this, whether the data configuration file acquiring unit 111 also data configuration item that can constantly detect in excited data configuration file is finished, if be finished, then group of notifications bag unit 112, to inform that the excited data of this PVC passage of group bag unit 112 is disposed, do not need to obtain data configuration item again.Optionally, whole excited data configuration file also directly can be sent to group bag unit 112 by data configuration file acquiring unit 111, such group of bag unit 112 can receive the excited data configuration file of data configuration file acquiring unit 111 transmission, excited data configuration file is resolved, obtains data configuration item.

Group bag unit 112, also be connected with sharding unit 113 and authentication module 13, for generating downlink data according to the data configuration item in excited data configuration file, according to ATM Adaptation Layer (ATM Adaptation Layer, referred to as ALL) agreement packages to downlink data, generate excited data, excited data is sent to sharding unit 113 and authentication module 13.Concrete, group bag unit 112 generates the downlink data that length, content and number all meet the regulation of data configuration item, then packages according to the corresponding agreement of ATM AAL, generates the excited data in the present embodiment.A kind of form of excited data as shown in Figure 6, comprising: LLC field, OUI field, ethernet type (EtherType) field and PDU field, and wherein, front 8BYTE adds for fixing, and PDU field fills the above-mentioned downlink data generated according to data configuration item.Group bag unit 112 excited data is sent to the object of authentication module 13 be in order to using excited data as expectation data, compare for the descending result data exported with module to be tested.Optionally, excited data can print in daily record (English is log) file by authentication module 13.

Sharding unit 113, also be connected with header acquiring unit 114, for excited data is filled into preset length integral multiple after burst carried out to excited data obtain fragment data corresponding to excited data, fragment data corresponding for excited data is stored into respectively in array of data corresponding to excited data, from the beginning PVC header information corresponding to excited data is obtained in information acquisition unit 114, PVC header information corresponding for excited data is stored in header information array corresponding to excited data, form descending ATM cell, and the announcement information of data whether is also had to the array of data that channel scheduling module 12 provides excited data corresponding.

Above-mentioned preset length is generally 48 bytes (byte).

The header information array one_to_one corresponding that the array of data that above-mentioned excited data is corresponding is corresponding with excited data is the preferred storage inside mode of one.This preferred storage inside mode is concrete as shown in Figure 7, and each fragment data comprises 48 bytes; Excited data after filling comprises n fragment data; The corresponding PVC header information of each fragment data, and form ATM cell with corresponding PVC header information, the PVC header information that the fragment data corresponding to same PVC passage is corresponding is identical.

Due to ATM agreement regulation, each scheduling all will obtain ATM cell, if there is no effective ATM cell (effective ATM cell refers to descending ATM cell) here, then obtain invalid (English is idle) ATM cell, so whether sharding unit 113 also has the announcement information of data to the array of data that channel scheduling module 12 provides excited data corresponding, be conducive to channel scheduling module 12 and dispatch.

Header acquiring unit 114, for obtaining descending PVC channel information configuration file from the second configuration array, and is supplied to sharding unit 113 by the PVC header information corresponding with excited data in descending PVC channel information configuration file.

Data capture unit 115, be connected with channel scheduling module 12, for the dispatch command that receive path scheduler module 12 sends, according to dispatch command, obtain descending ATM cell or from preset group, obtain invalid ATM cell the array of data corresponding from excited data and header information array, and descending ATM cell or invalid ATM cell are supplied to channel scheduling module 12.

Based on above-mentioned, a kind of implementation structure of channel scheduling module 12 as shown in Figure 4, comprising: scheduling unit 121, exception control unit 122, data processing unit 123 and outlet port unit 124.

Scheduling unit 121, for obtaining scheduling configuration file from the 3rd configuration array, receives the announcement information that sharding unit 113 sends, and according to the scheduling time of dispatching in configuration file and the announcement information received, sends dispatch command to data capture unit 115.Wherein, sharding unit 113 is specifically connected with the scheduling unit 121 in channel scheduling module 12, and data capture unit 115 is also specifically connected with the scheduling unit 121 in channel scheduling module 12.

Exception control unit 122, be connected with data processing unit 123, for obtaining wrong abnormal configuration file from the 4th configuration array, and generate the Wrong control instruction corresponding with the Exception Type in mistake exception configuration file in exception control time in the abnormal configuration file of mistake, Wrong control instruction is sent to data processing unit 123.

Data processing unit 123, for receiving the descending ATM cell or invalid ATM cell that data capture unit 115 provides, according to Wrong control instruction, abnormality processing is carried out to the descending ATM cell received or invalid ATM cell, the descending ATM cell after abnormality processing or invalid ATM cell are sent to outlet port unit 124.Data processing unit 123 is connected with exception control unit 122, data capture unit 115 and outlet port unit 124 simultaneously.

Outlet port unit 124, for receiving the descending ATM cell after abnormality processing of data processing unit 123 transmission or invalid ATM cell, according to the stream interface sequential corresponding with module to be tested, the descending ATM cell after abnormality processing or invalid ATM cell are sent to module to be tested.The bit wide (i.e. the width of interface) of outlet port unit 124 here can be arranged, so that be connected with different modules to be tested, improves flexibility ratio and the versatility of the emulation platform that the present embodiment provides.Such as, a kind of definition of outlet port unit 124 is as shown in table 1.

Table 1

Signal name	Attribute	Bit wide	Describe
				DT	Out	Configurable	ATM CELLS data
EN	In	1bit	ATM CELLS data enable

In above-mentioned table 1, " DT " represents ATM cell data, such as, descending ATM cell after above-mentioned abnormality processing or invalid ATM cell, " EN " represents the enable signal of ATM cell data, " In " and " Out " represents sense, " In " represents the direction flowing into interface, and " Out " represents the direction of flowing out interface.

Illustrate at this, first, second, third, fourth grade related in various embodiments of the present invention is only to distinguish, and does not have restriction numerically.Such as, first, second, third, fourth configuration array can be same configuration array, also can be different configuration array.

The ATM logical design emulation platform that the embodiment of the present invention provides, only need once compile formation simulated environment with the program code in module to be tested, then based on this simulated environment, test case can be controlled directly run by various configuration file generating test use case, realize the checking treating the receive logic of test module, all need not compile test case at every turn, improve and treat the efficiency that test module carries out logical simulation.

Further, as shown in Figure 4, the emulation platform of the present embodiment also comprises: channel reception module 14 and passage group bag module 15.

Channel reception module 14, be connected with module to be tested and passage group bag module 15, for the up ATM cell that the upstream data receiving module to be tested transmission is corresponding, carry out HEC to up ATM cell synchronously to process, and search up PVC channel information configuration file, obtain the PVC channel number that up ATM cell is corresponding, the valid data in up ATM cell and PVC channel number corresponding to up ATM cell are sent to passage group bag module 15.

Up PVC channel information configuration file in the present embodiment is mainly used in storing PVC header information corresponding to every bar data flow, comprises the information such as GFC, VPI, VCI and CLP and PVC channel number of No. ID, data flow and correspondence thereof.Wherein, ATM cell recipient can according to PVC header information correct inquire PVC passage corresponding to data flow.The form that realizes of up PVC channel information configuration file can be shown in Figure 3.

Passage group bag module 15, for the PVC channel number corresponding according to the up ATM cell received, data recombination is carried out to the valid data in the up ATM cell received, obtain the AAL data that each PVC channel number is corresponding, and AAL data are verified, output verification result.

Optionally, channel reception module 14 comprises: lock unit 141, data sorting unit 142 and lookup unit 143.

Wherein, lock unit 141, for the up ATM cell that the upstream data receiving module to be tested transmission is corresponding, carry out HEC to up ATM cell synchronously to process, when the synchronous success of HEC, up ATM cell is sent to data sorting unit, the HEC head of the output error when HEC synchronization failure and wrong time of origin.HEC synchronous state machine as shown in Figure 8.Synchronous state machine shown in Fig. 8 is briefly described, before not synchronous, be in trapped state, synchronizing process connects correctly to have come, once find than the HEC in specially null hypothesis letter header field by bit, just enter presynchronization state, under presynchronization state, constantly can check that whether the HEC of cell is one by one correct, continuous 6 HEC correctly so just enter synchronous regime, continuous when being checked through incorrect HEC 7 times under synchronous regime, can trapped state be reentered.

Lock unit 141 is mainly used in carrying out HEC synchronously to the up ATM cell received, and according to ATM agreement, only has synchronously and just can enter normal receiving course.A kind of embodiment is: after successful synchronization, lock unit 141 is by the data on real real-time inspection line, once there is HEC check errors, lock unit 141 will stop emulation after 200us, wait for user's subsequent operation, and the time that the HEC head of mistake and mistake occur is outputted in log file, facilitate tester to debug.The Log of HEC head mistake is with reference to as follows:

Data sorting unit 142, be connected with lock unit 141, for receiving the up ATM cell that lock unit 141 sends, up ATM cell is classified, statistics obtains the number of invalid up ATM cell and effective up ATM cell in upstream data, to know whether the speed of module to be tested reaches linear speed, and effective up ATM cell is sent to lookup unit 143.

The up ATM cell that data sorting unit 142 is mainly used in being sent here by lock unit 141 carries out the classification of invalid up ATM cell and effective up ATM cell, lookup unit 143 is given by effective up ATM cell, add up the quantity of invalid up ATM cell simultaneously, and the statistical function to the total number of up ATM cell and Mean Speed is provided, effectively can test out module to be tested like this and whether can reach linear speed in speed.Such as, module to be tested is that a certain bar data are banishd and put whole threads, and when inputting overload, data sorting unit 142 should receive invalid up ATM cell, so just illustrates that module to be tested reaches linear speed; Otherwise illustrate that module to be tested fails to reach linear speed, if module to be tested fails to reach linear speed, checking personnel also can by the statistical log to invalid up ATM cell, orientation problem fast.The parameter format of a kind of file log is as follows:

Lookup unit 143, for obtaining up PVC channel information configuration file from the 5th configuration array, according to the PVC header information in effective up ATM cell, search up PVC channel information configuration file to obtain PVC channel number corresponding to effective up ATM cell, if get the PVC channel number that effective up ATM cell is corresponding, valid data in effective up ATM cell and PVC channel number corresponding to effective up ATM cell are sent to passage group bag module 15, if do not get the PVC channel number that effective up ATM cell is corresponding, export configuration error information and terminate simulation operations.

Wherein, if do not find corresponding PVC channel number, what illustrate up PVC and channel number relation is improperly-configured, directly stops emulation, and configuration error (ERROR) prompting can be exported, so that tester carries out problem discover in time and takes respective handling measure.

In addition, lookup unit 143 can also carry out number statistics to effective up ATM cell, to obtain scheduling rates and the QoS performance of module to be tested.Concrete, lookup unit 143 carries out the statistics of effective up ATM cell number according to PVC passage, obtains the speed receiving effective up ATM cell, effectively can test out the efficiency of module schedules to be tested like this, and the function etc. of relevant QOS.Such as, as follows according to the log reference of PVC passage to effective up ATM cell Statistical Rate:

Explain in conjunction with above-mentioned log.At aspect of performance, such as suppose that the rate configuration of a certain PVC passage of module to be tested becomes 128kbps, then can see in above-mentioned log that corresponding cell rate should be about 301 ~ 302 (namely 128000/8/53).For QOS be also, such as suppose in module to be tested, there is the transmission carrying out data according to the priority of passage, if two PVC passages of module so to be tested have the data flow of linear speed, so can see in above-mentioned log that the cell rate of the data flow of the PVC passage that priority is high should higher than the cell rate of the data flow of the low PVC passage of priority.

Based on above-mentioned, a kind of implementation structure of passage group bag module 15 as shown in Figure 4, comprising: group detects unit 151 and frame processing unit 152.

Framing unit 151, be connected with lookup unit 143 and frame processing unit 152, for receiving valid data in effective up ATM cell that lookup unit 143 sends and PVC channel number corresponding to effective up ATM cell, and the PVC channel number corresponding according to effective up ATM cell is recombinated to the valid data in the effective up ATM cell received, obtain the AAL data that upstream data is corresponding, AAL data are stored in array of data corresponding to upstream data, and complete indication information to frame processing unit 152 transmission and reception.

Frame processing unit 152, for according to finishing receiving indication information, from the array of data that upstream data is corresponding, obtain AAL data, head verification, CRC check and/or length check are fixed to AAL data, when there is check errors, output verification result and the AAL data made a mistake.

From above-mentioned, the emulation platform of the present embodiment is by channel reception module 14 and passage group bag module 15, effectively can treat the cell data that test module sends here and carry out counting rate, can test the correctness of the interrelated logic such as schedule speed and QOS of module to be tested reliably, carrying out test for the performance treating test module provides effective foundation.

In this explanation, above-mentioned channel reception module 14 and passage group bag module 15 can form the up phantom channel that the descending performance treating test module carries out testing, and aforementioned channels generation module 11, channel scheduling module 12 and authentication module 13 can form the descending phantom channel that the uplink receiving logic treating test module carries out testing.

In an Alternate embodiments of the present embodiment, as shown in Figure 4, the emulation platform of the present embodiment also comprises: configuration file imports module 16.

Configuration file imports module 16, before starting in emulation, by all configuration files, such as, in advance excited data configuration file, descending PVC channel information configuration file, scheduling configuration file, up PVC channel information configuration file, the abnormal configuration file of mistake etc. are imported in corresponding configuration array.Configuration file imports module 16 and specifically can excited data configuration file, descending PVC channel information configuration file and scheduling configuration file be imported respectively in first, second, and third configuration array in advance.Configuration array in various embodiments of the present invention refers to the memory space in the ATM logical design emulation platform of the present embodiment, such as RAM etc., in the ATM logical design emulation platform of the present embodiment, each module can directly read each configuration array, in addition, different configuration files can be stored in independently in configuration array respectively, also can be stored in identical configuration array.

Optionally, configuration file imports module 16 and is connected with the data configuration file acquiring unit 111 in passage generation module 11 and header acquiring unit 114, configuration file imports module 16 and is also connected with the scheduling unit 121 in channel scheduling module 12 and exception control unit 122, and configuration file imports module 16 and is also connected with the lookup unit 143 in channel reception module 14.

The ATM logical design emulation platform that the present embodiment provides imports module 16 by configuration file, and what decrease in simulation process between each module and configuration file is mutual, effectively raises simulation efficiency, is conducive to improving the quality that module to be tested exports.

In an Alternate embodiments of the present embodiment, as shown in Figure 4, the ATM logical design emulation platform that the present embodiment provides also comprises: configuration file generation module 17.

Configuration file generation module 17, for being generated the various configuration files of text formatting by Excel instrument, such as excited data configuration file, descending PVC channel information configuration file and scheduling configuration file etc.Except excited data configuration file, descending PVC channel information configuration file and scheduling configuration file, configuration file generation module 17 also can generate by Excel instrument other configuration files used in simulation process, and these configuration files are also text formattings.Configuration file generation module 17 and configuration file import module 16 and are connected, and provide various configuration file for importing module 16 to configuration file.

The emulation platform that the present embodiment provides, the basis of above-mentioned each module introduces Excel instrument, provide more friendly configuration file design interface, be conducive to the generation of test case, greatly tester is freed from uninteresting and loaded down with trivial details writing the test case of txt form, make it more to pay close attention to checking itself, be conducive to improving simulated mass.

The flow chart of the ATM logical design emulation mode that Fig. 9 provides for one embodiment of the invention.As shown in Figure 9, the method for the present embodiment comprises:

Step 901, according to the data configuration item in excited data configuration file, excited data in generating test use case, according to PVC header information corresponding with excited data in descending PVC channel information configuration file, burst process is carried out to excited data, form the descending ATM cell that excited data is corresponding, data configuration item comprises data length, data content and data amount check.

Step 902, according to scheduling configuration file in scheduling time, descending ATM cell corresponding for excited data is sent to module to be tested, for module to be tested carry out receptions process.

Step 903, obtain resume module to be tested after the descending result data corresponding with excited data, excited data and descending result data are compared, to verify the receive logic of module to be tested.

The executive agent of the present embodiment can be the ATM logic design_and_verification platform that above-described embodiment provides, but is not limited thereto.

The detailed process of the ATM logic design_and_verification method that the present embodiment provides see the description in above-mentioned ATM logic design_and_verification platform embodiment, can be not described in detail in this.

The ATM logic design_and_verification method of the present embodiment is mainly carried out based on various configuration file, not only can excited data in generating test use case based on configuration file, and configuration file additionally provides the control logic needed for simulation process, the method of the present embodiment can directly be carried out in the environment compiled, and do not need each emulation or each test case to recompilate, improve and treat the efficiency that test module carries out logical simulation.

The flow chart of the ATM logic design_and_verification method that Figure 10 provides for another embodiment of the present invention.The present embodiment is based on realization embodiment illustrated in fig. 9, and as shown in Figure 10, the method for the present embodiment also comprises:

Step 904, receive up ATM cell corresponding to upstream data that module to be tested sends, HEC is carried out to up ATM cell and synchronously processes, and search up PVC channel information configuration file, obtain the PVC channel number that up ATM cell is corresponding.

Step 905, the PVC channel number corresponding according to up ATM cell carry out data recombination to the valid data in up ATM cell, obtain the AAL data that each PVC channel number is corresponding, and verify AAL data, output verification result.

What above-mentioned steps 901-step 903 described is the process verified the receive logic of ATM logical design, and what step 904 and step 905 described is the process verified transmission logic and the performance of ATM logical design.These two processes can be separate, then the sequencing of the process that the process of step 901-step 903 description and step 904-step 905 describe does not limit.In addition, these two processes also can form a winding process, namely the up ATM cell that the upstream data that sends in step 904 of module to be tested is corresponding can be descending result data corresponding with above-mentioned excited data after module to be tested processes in step 902, so just can form loopback test process, based on this, step 904 and step 905 perform after the process that step 901-step 903 describes.

In an Alternate embodiments, the above-mentioned scheduling time according to dispatching in configuration file, descending ATM cell corresponding for excited data being sent to module to be tested, can comprise before carrying out reception process for module to be tested:

Controlling descending ATM cell corresponding to excited data according to the abnormal configuration file of mistake occurs abnormal, and to realize the checking of the exception handling ability treating test module, wherein, the abnormal configuration file of mistake comprises exception control time and Exception Type.

In an Alternate embodiments, above-mentioned according to the data configuration item in excited data configuration file, excited data in generating test use case, according to PVC header information corresponding with excited data in descending PVC channel information configuration file, carry out burst process to excited data, the descending ATM cell forming excited data corresponding comprises:

From the first configuration array, obtain excited data configuration file, from the second configuration array, obtain descending PVC channel information configuration file; Generate downlink data according to the data configuration item in excited data configuration file, according to ATM ALL agreement, downlink data is packaged, generate excited data; After excited data being filled into the integral multiple of preset length, burst is carried out to excited data and obtain fragment data corresponding to excited data, fragment data corresponding for excited data is stored into respectively in array of data corresponding to excited data, PVC header information corresponding to excited data is obtained from descending PVC channel information configuration file, PVC header information corresponding for excited data is stored in header information array corresponding to excited data, forms above-mentioned descending ATM cell.Wherein, the header information array one_to_one corresponding that the array of data that excited data is corresponding is corresponding with excited data.

In an Alternate embodiments, above-mentioned according to the scheduling time in scheduling configuration file, descending ATM cell corresponding for excited data is sent to module to be tested, carries out reception process for module to be tested and comprise:

From the 3rd configuration array, obtain scheduling configuration file, send dispatch command according to the scheduling time in scheduling configuration file; According to dispatch command, when also having data in the array of data that excited data is corresponding, obtain descending ATM cell the array of data corresponding from excited data and header information array, when there is no data in the array of data that excited data is corresponding, from preset group, obtain invalid ATM cell; From the 4th configuration array, obtain wrong abnormal configuration file, and generate the Wrong control instruction corresponding with the Exception Type in mistake exception configuration file in exception control time in the abnormal configuration file of mistake; According to Wrong control instruction, abnormality processing is carried out to descending ATM cell or invalid ATM cell; According to the stream interface sequential corresponding with module to be tested, the descending ATM cell after abnormality processing or invalid ATM cell are sent to module to be tested.

In an Alternate embodiments, the up ATM cell that the upstream data that above-mentioned reception module to be tested sends is corresponding, carry out HEC to up ATM cell synchronously to process, and search up PVC channel information configuration file, the PVC channel number obtaining up ATM cell corresponding comprises:

Receive the up ATM cell that the upstream data of module to be tested transmission is corresponding, HEC is carried out to up ATM cell and synchronously processes, when HEC synchronization failure, the HEC head of output error and wrong time of origin; When the synchronous success of HEC, classify to up ATM cell, statistics obtains the number of invalid up ATM cell and effective up ATM cell in upstream data, to know whether the speed of module to be tested reaches linear speed; Up PVC channel information configuration file is obtained from the 5th configuration array, according to the PVC header information in effective up ATM cell, search up PVC channel information configuration file to obtain PVC channel number corresponding to effective up ATM cell, if do not get the PVC channel number that effective up ATM cell is corresponding, export configuration error information and terminate simulation operations.

Based on above-mentioned, the method for the present embodiment also comprises: carry out number statistics to effective up ATM cell, to obtain scheduling rates and the QoS performance of module to be tested.The present embodiment effectively can be treated the cell data that test module sends here and carry out counting rate, and can test the correctness of the interrelated logic such as schedule speed and QOS of module to be tested reliably, carrying out test for the performance treating test module provides effective foundation.

In an Alternate embodiments, the above-mentioned PVC channel number corresponding according to up ATM cell carries out data recombination to the valid data in up ATM cell, obtain the AAL data that each PVC channel number is corresponding, and verify AAL data, output verification result comprises:

The PVC channel number corresponding according to effective up ATM cell is recombinated to the valid data in effective up ATM cell, obtain the AAL data that upstream data is corresponding, AAL data are stored in array of data corresponding to upstream data, and send and finish receiving indication information; According to finishing receiving indication information, from the array of data that upstream data is corresponding, obtain AAL data, head verification, CRC check and/or length check are fixed to AAL data, when there is check errors, output error check results and the AAL data made a mistake.

In an Alternate embodiments, above-mentioned according to the data configuration item in excited data configuration file, excited data in generating test use case, according to PVC header information corresponding with excited data in descending fixing virtual circuit PVC channel information configuration file, burst process is carried out to excited data, comprises before forming descending ATM cell corresponding to excited data:

Before emulation starts, excited data configuration file, descending PVC channel information configuration file and scheduling configuration file are imported in corresponding configuration array.What which reduce in simulation process between each module and configuration file is mutual, effectively raises simulation efficiency, is conducive to improving the quality that module to be tested exports.

In an Alternate embodiments, above-mentioned excited data configuration file, descending PVC channel information configuration file and scheduling configuration file importings in corresponding configuration array comprises before:

The excited data configuration file of text formatting, descending PVC channel information configuration file and scheduling configuration file is generated by Excel instrument.The present embodiment is by introducing Excel instrument, provide more friendly configuration file design interface, be conducive to the generation of test case, greatly tester is freed from uninteresting and loaded down with trivial details writing the test case of txt form, make it more to pay close attention to checking itself, be conducive to improving simulated mass.

The executive agent of the present embodiment and each execution mode thereof can be the ATM logic design_and_verification platform that previous embodiment provides, and the detailed process of each step repeats no more, and refers to the description in aforementioned ATM logic design_and_verification platform embodiment.

To sum up, the concrete following beneficial effect of ATM logic design_and_verification method that the present embodiment provides: 1, can independently be configured each excited data of PVC data channel and the transmission rate of excited data, improve the flexibility of emulation, and all configuration files all read in storage in the moment unification that emulation starts, which reduce the file interaction in simulation process, effectively raise simulation efficiency.2, provide model interface easily, can be connected with various different physical layer model, carry out integration testing and also can carry out individual module test separately, there is good versatility.3, for the various generation forcing mistake, such as, during HEC delimits contingent single bit mistake, the pressure of many bit mistake occurs, and the crc of AAL data forces mistake, and LEN forces mistake, effectively can carry out various abnormality test.4, effectively can carry out counting rate to the cell of data burst that module to be measured is sent here, scheduling and the QOS interrelated logic correctness of module to be measured can be tested reliably.5, introduce excel, provide more friendly incentives interface, greatly tester is freed from uninteresting and loaded down with trivial details writing the test case of txt form, more pay close attention to and checking itself.

One embodiment of the invention provides a kind of equipment, comprises ATM logical design emulation platform.Wherein, ATM logical design emulation platform can be arbitrary ATM logical design emulation platform that previous embodiment of the present invention provides, and its operation principle and implementation structure see the description of previous embodiment, can not repeat them here.

The equipment that the present embodiment provides can be the various equipment with certain computing ability, such as, can be server, computer etc.

The equipment that the present embodiment provides comprises the ATM logical design emulation platform that the embodiment of the present invention provides, the flow process of the ATM logical design emulation mode that the embodiment of the present invention provides can be performed equally, therefore, have equally improve treat test module carry out logical simulation efficiency, there is the beneficial effects such as stronger versatility.

One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that program command is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.

Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims (15)

1. an asynchronous transfer mode ATM logical design emulation platform, is characterized in that, comprising:

Passage generation module, for according to the data configuration item in excited data configuration file, excited data in generating test use case, according to PVC header information corresponding with described excited data in descending fixing virtual circuit PVC channel information configuration file, burst process is carried out to described excited data, form the descending ATM cell that described excited data is corresponding, described data configuration item comprises data length, data content and data amount check;

Channel scheduling module, is connected with described passage generation module, for according to the scheduling time in scheduling configuration file, descending ATM cell corresponding for described excited data is sent to module to be tested, carries out reception process for described module to be tested;

Authentication module, for descending result data corresponding with described excited data after obtaining described resume module to be tested, compares described excited data and described descending result data, to verify the receive logic of described module to be tested;

Described passage generation module comprises:

Data configuration file acquiring unit, for obtaining described excited data configuration file from the first configuration array, sends to group bag unit by described excited data configuration file;

Described group of bag unit, for generating downlink data according to the data configuration item in described excited data configuration file, according to ATM Adaptation Layer ALL agreement, described downlink data is packaged, generate described excited data, described excited data is sent to sharding unit and described authentication module;

Described sharding unit, for described excited data is filled into preset length integral multiple after burst carried out to described excited data obtain fragment data corresponding to described excited data, fragment data corresponding for described excited data is stored into respectively in array of data corresponding to described excited data, from the beginning the PVC header information that described excited data is corresponding is obtained in information acquisition unit, PVC header information corresponding for described excited data is stored in header information array corresponding to described excited data, forms described descending ATM cell; Wherein, the header information array one_to_one corresponding that the array of data that described excited data is corresponding is corresponding with described excited data;

Header acquiring unit, for obtaining described descending PVC channel information configuration file from the second configuration array, and is supplied to described sharding unit by the PVC header information corresponding with described excited data in described descending PVC channel information configuration file;

Data capture unit, for receiving the dispatch command that described channel scheduling module sends, according to described dispatch command, obtain described descending ATM cell or from preset group, obtain invalid ATM cell the array of data corresponding from described excited data and header information array, and described descending ATM cell or invalid ATM cell are supplied to described channel scheduling module.

2. ATM logical design emulation platform according to claim 1, it is characterized in that, described channel scheduling module is also for before sending to described module to be tested by descending ATM cell corresponding for described excited data, controlling descending ATM cell corresponding to described excited data according to the abnormal configuration file of mistake occurs abnormal, to realize the checking to the exception handling ability of described module to be tested, the abnormal configuration file of described mistake comprises exception control time and Exception Type.

3. ATM logical design emulation platform according to claim 2, is characterized in that, the announcement information of described sharding unit also for providing array of data that described excited data is corresponding whether to also have data to described channel scheduling module;

Described channel scheduling module comprises:

Scheduling unit, for obtaining described scheduling configuration file from the 3rd configuration array, receive the described announcement information that described sharding unit sends, and according to the scheduling time in described scheduling configuration file and described announcement information, send described dispatch command to described data capture unit;

Exception control unit, for obtaining the abnormal configuration file of described mistake from the 4th configuration array, and generate the Wrong control instruction corresponding with the Exception Type in the abnormal configuration file of described mistake in exception control time in the abnormal configuration file of described mistake, described Wrong control instruction is sent to data processing unit;

Described data processing unit, for receiving the described descending ATM cell or invalid ATM cell that described data capture unit provides, according to described Wrong control instruction, abnormality processing is carried out to the described descending ATM cell received or invalid ATM cell, the descending ATM cell after abnormality processing or invalid ATM cell are sent to outlet port unit;

Described outlet port unit, for according to the stream interface sequential corresponding with described module to be tested, sends to described module to be tested by the descending ATM cell after abnormality processing or invalid ATM cell.

4. the ATM logical design emulation platform according to any one of claim 1-3, is characterized in that, also comprise:

Channel reception module, for the up ATM cell that the upstream data receiving described module transmission to be tested is corresponding, carry out HEC to described up ATM cell synchronously to process, and search up PVC channel information configuration file, obtain the PVC channel number that described up ATM cell is corresponding, the valid data in described up ATM cell and PVC channel number corresponding to described up ATM cell are sent to passage group bag module;

Described passage group bag module, for the PVC channel number corresponding according to the described up ATM cell received, data recombination is carried out to the valid data in the described up ATM cell received, obtain the AAL data that each PVC channel number is corresponding, and described AAL data are verified, output verification result.

5. ATM logical design emulation platform according to claim 4, is characterized in that, described channel reception module comprises:

Lock unit, for the up ATM cell that the upstream data receiving described module transmission to be tested is corresponding, carry out header error control HEC to described up ATM cell synchronously to process, when the synchronous success of HEC, described up ATM cell is sent to data sorting unit, the HEC head of the output error when HEC synchronization failure and wrong time of origin;

Data sorting unit, for receiving the described up ATM cell that described lock unit sends, described up ATM cell is classified, statistics obtains the number of invalid up ATM cell and effective up ATM cell in described upstream data, to know whether the speed of described module to be tested reaches linear speed, and described effective up ATM cell is sent to lookup unit;

Described lookup unit, for obtaining described up PVC channel information configuration file from the 5th configuration array, according to the PVC header information in described effective up ATM cell, search described up PVC channel information configuration file to obtain PVC channel number corresponding to described effective up ATM cell, if get the PVC channel number that described effective up ATM cell is corresponding, valid data in described effective up ATM cell and PVC channel number corresponding to described effective up ATM cell are sent to described passage group bag module, if do not get the PVC channel number that described effective up ATM cell is corresponding, export configuration error information and terminate simulation operations.

6. ATM logical design emulation platform according to claim 5, is characterized in that,

Described lookup unit also for carrying out number statistics to described effective up ATM cell, to obtain scheduling rates and the service quality QoS performance of described module to be tested.

7. the ATM logical design emulation platform according to claim 5 or 6, is characterized in that, described passage group bag module comprises:

Framing unit, for receiving valid data in described effective up ATM cell that described lookup unit sends and PVC channel number corresponding to described effective up ATM cell, and the PVC channel number corresponding according to described effective up ATM cell is recombinated to the valid data in the described effective up ATM cell received, obtain the AAL data that described upstream data is corresponding, described AAL data are stored in array of data corresponding to described upstream data, and complete indication information to frame processing unit transmission and reception;

Described frame processing unit, indication information is finished receiving for described in basis, described AAL data are obtained from the array of data that described upstream data is corresponding, head verification, CRC check and/or length check are fixed to described AAL data, when there is check errors, output error check results and the described AAL data made a mistake.

8. an asynchronous transfer mode ATM logical design emulation mode, is characterized in that, comprising:

According to the data configuration item in excited data configuration file, excited data in generating test use case, according to PVC header information corresponding with described excited data in descending fixing virtual circuit PVC channel information configuration file, burst process is carried out to described excited data, form the descending ATM cell that described excited data is corresponding, described data configuration item comprises data length, data content and data amount check;

According to the scheduling time in scheduling configuration file, descending ATM cell corresponding for described excited data is sent to module to be tested, carry out reception process for described module to be tested;

Descending result data corresponding with described excited data after obtaining described resume module to be tested, compares described excited data and described descending result data, to verify the receive logic of described module to be tested;

Described according to the data configuration item in excited data configuration file, excited data in generating test use case, according to PVC header information corresponding with described excited data in descending fixing virtual circuit PVC channel information configuration file, carry out burst process to described excited data, the descending ATM cell forming described excited data corresponding comprises:

From the first configuration array, obtain described excited data configuration file, from the second configuration array, obtain described descending PVC channel information configuration file;

Generate downlink data according to the data configuration item in described excited data configuration file, according to ATM Adaptation Layer ALL agreement, described downlink data is packaged, generate described excited data;

After described excited data being filled into the integral multiple of preset length, burst is carried out to described excited data and obtain fragment data corresponding to described excited data, fragment data corresponding for described excited data is stored into respectively in array of data corresponding to described excited data, PVC header information corresponding to described excited data is obtained from described descending PVC channel information configuration file, PVC header information corresponding for described excited data is stored in header information array corresponding to described excited data, forms described descending ATM cell; Wherein, the header information array one_to_one corresponding that the array of data that described excited data is corresponding is corresponding with described excited data.

9. ATM logical design emulation mode according to claim 8, it is characterized in that, the described scheduling time according to dispatching in configuration file, descending ATM cell corresponding for described excited data being sent to module to be tested, comprising before carrying out reception process for described module to be tested:

Controlling descending ATM cell corresponding to described excited data according to the abnormal configuration file of mistake occurs abnormal, and to realize the checking of the exception handling ability to described module to be tested, the abnormal configuration file of described mistake comprises exception control time and Exception Type.

10. ATM logical design emulation mode according to claim 9, it is characterized in that, described according to the scheduling time in scheduling configuration file, descending ATM cell corresponding for described excited data is sent to module to be tested, carries out reception process for described module to be tested and comprise:

From the 3rd configuration array, obtain described scheduling configuration file, send dispatch command according to the scheduling time in described scheduling configuration file;

According to described dispatch command, when also having data in the array of data that described excited data is corresponding, described descending ATM cell is obtained the array of data corresponding from described excited data and header information array, when there is no data in the array of data that described excited data is corresponding, from preset group, obtain invalid ATM cell;

From the 4th configuration array, obtain the abnormal configuration file of described mistake, and generate the Wrong control instruction corresponding with the Exception Type in the abnormal configuration file of described mistake in exception control time in the abnormal configuration file of described mistake;

According to described Wrong control instruction, abnormality processing is carried out to described descending ATM cell or invalid ATM cell;

According to the stream interface sequential corresponding with described module to be tested, the descending ATM cell after abnormality processing or invalid ATM cell are sent to described module to be tested.

11. ATM logical design emulation modes according to Claim 8 described in-10 any one, is characterized in that, also comprise:

Receive the up ATM cell that the upstream data of described module transmission to be tested is corresponding, carry out header error control HEC to described up ATM cell synchronously to process, and search up PVC channel information configuration file, obtain the PVC channel number that described up ATM cell is corresponding;

The PVC channel number corresponding according to described up ATM cell carries out data recombination to the valid data in described up ATM cell, obtains the AAL data that each PVC channel number is corresponding, and verifies described AAL data, output verification result.

12. ATM logical design emulation modes according to claim 11, it is characterized in that, the up ATM cell that the upstream data that the described module to be tested of described reception sends is corresponding, carry out header error control HEC to described up ATM cell synchronously to process, and search up PVC channel information configuration file, the PVC channel number obtaining described up ATM cell corresponding comprises:

Receive the up ATM cell that the upstream data of described module transmission to be tested is corresponding, HEC is carried out to described up ATM cell and synchronously processes, when HEC synchronization failure, the HEC head of output error and wrong time of origin;

When the synchronous success of HEC, classify to described up ATM cell, statistics obtains the number of invalid up ATM cell and effective up ATM cell in described upstream data, to know whether the speed of described module to be tested reaches linear speed;

Described up PVC channel information configuration file is obtained from the 5th configuration array, according to the PVC header information in described effective up ATM cell, search described up PVC channel information configuration file to obtain PVC channel number corresponding to described effective up ATM cell, if do not get the PVC channel number that described effective up ATM cell is corresponding, export configuration error information and terminate simulation operations.

13. ATM logical design emulation modes according to claim 12, is characterized in that, also comprise:

Number statistics is carried out to described effective up ATM cell, to obtain scheduling rates and the service quality QoS performance of described module to be tested.

14. ATM logical design emulation modes according to claim 12 or 13, it is characterized in that, the described PVC channel number corresponding according to described up ATM cell carries out data recombination to the valid data in described up ATM cell, obtain the AAL data that each PVC channel number is corresponding, and described AAL data are verified, output verification result comprises:

The PVC channel number corresponding according to described effective up ATM cell is recombinated to the valid data in described effective up ATM cell, obtain the AAL data that described upstream data is corresponding, described AAL data are stored in array of data corresponding to described upstream data, and send and finish receiving indication information;

Indication information is finished receiving according to described, described AAL data are obtained from the array of data that described upstream data is corresponding, head verification, CRC check and/or length check are fixed to described AAL data, when there is check errors, output error check results and the described AAL data made a mistake.

15. 1 kinds of emulators, is characterized in that, comprising: the asynchronous transfer mode ATM logical design emulation platform described in any one of claim 1-7.