CN102868646A - Asynchronous transfer mode (ATM) logic design simulation method and platform, and equipment - Google Patents
Asynchronous transfer mode (ATM) logic design simulation method and platform, and equipment Download PDFInfo
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Abstract
The invention discloses an asynchronous transfer mode (ATM) logic design simulation method, an ATM logic design simulation platform, and equipment. The platform comprises a path generating module, a path scheduling module and a verification module, wherein the path generating module is used for forming a downlink ATM cell corresponding to incentive data according to an incentive data configuration file and a downlink permanent virtual circuit (PVC) path information configuration file; the path scheduling module is used for transmitting the downlink ATM cell corresponding to the incentive data to a module to be tested for the module to be tested to receive and process according to the scheduling time in a scheduling configuration file; and the verification module is used for acquiring downlink result data which are processed by the module to be tested and correspond to the incentive data, and comparing the incentive data with the downlink result data to verify receiving logic of the module to be tested. By the technical scheme, the efficiency of simulation and verification on an ATM logic design is improved.
Description
Technical field
The present invention relates to the logical simulation technology, relate in particular to a kind of asynchronous transfer mode (Asynchronous Transfer Mode is referred to as ATM) logical design emulation mode, platform and equipment.
Background technology
ATM is a kind of packet switching and multiplex technique take cell (English as cell) as unit, can provide general connection-oriented transmission mode for multiple business, be applicable to local area network (LAN) and wide area network, have high-speed data transmission rate and can support polytype such as the communicating by letter of sound, data, fax, real-time video and image.The ATM logic can be passed through field programmable gate array (Field Programmable Gate Array is referred to as FPGA) realization at present.FPGA is the very high novel high-performance programmable chip of a kind of integrated level, the its internal circuit function is programmable (the English Programmable of being), can pass through hardware description language (Hardware Description Language, referred to as HDL) and the special designs instrument, section realizes extremely complicated circuit function flexibly within it.
FPGA simulating, verifying technology is the important component part of FPGA exploitation link, carries out logic checking mainly for the function that FPGA realizes.The emulation of the ATM logical design that at present FPGA is realized mainly is: the designer of ATM logic writes respectively test case according to each test point, test case is compiled the generation verification environment, then in the verification environment that generates, the logic of design is verified that simulating, verifying efficient is lower.
Summary of the invention
The invention provides a kind of asynchronous transfer mode logical design emulation mode, platform and equipment, in order to improve the efficient of the ATM logical design being carried out simulating, verifying.
One aspect of the present invention provides a kind of asynchronous transfer mode logical design emulation mode, comprising:
The passage generation module, be used for the data configuration item according to the excited data configuration file, excited data in the generating test use case, according to the PVC header information corresponding with described excited data in the descending fixedly virtual circuit PVC channel information configuration file, described excited data is carried out burst to be processed, form descending ATM cell corresponding to described excited data, described data configuration item comprises data length, data content and data amount check;
The channel scheduling module is connected with described passage generation module, is used for the scheduling time according to the scheduling configuration file, and the descending ATM cell that described excited data is corresponding sends to module to be tested, carries out reception ﹠ disposal for described module to be tested;
Authentication module is used for obtaining the descending result data corresponding with described excited data after the described resume module to be tested, described excited data and described descending result data is compared, to verify the receive logic of described module to be tested.
The present invention provides a kind of asynchronous transfer mode logical design emulation platform on the other hand, comprising:
According to the data configuration item in the excited data configuration file, excited data in the generating test use case, according to the PVC header information corresponding with described excited data in the descending fixedly virtual circuit PVC channel information configuration file, described excited data is carried out burst to be processed, form descending ATM cell corresponding to described excited data, described data configuration item comprises data length, data content and data amount check;
According to the scheduling time in the scheduling configuration file, the descending ATM cell that described excited data is corresponding sends to module to be tested, carries out reception ﹠ disposal for described module to be tested;
Obtain the descending result data corresponding with described excited data after the described resume module to be tested, described excited data and described descending result data are compared, to verify the receive logic of described module to be tested.
Another aspect of the invention provides a kind of equipment, comprises asynchronous transfer mode logical design emulation platform provided by the invention.
Asynchronous transfer mode logical design emulation mode provided by the invention, platform and equipment, according to the excited data in the excited data configuration file generating test use case, next according to PVC channel information configuration file excited data is carried out burst and process the descending ATM cell of formation, according to the scheduling time in the scheduling configuration file, descending ATM cell is sent to module to be tested, carry out reception ﹠ disposal for module to be tested, compare by the excited data with the result data after the resume module to be tested and generation, the checking of the receive logic of test module is treated in realization.Technical solution of the present invention is mainly based on various configuration files, also provide simulation process required control logic based on the excited data in the configuration file generating test use case and configuration file, therefore test case can be in translation and compiling environment directly operation carry out emulation, the checking of the receive logic of test module is treated in realization, emulation all compiles test case at every turn, has improved and has treated the efficient that test module carries out logical simulation.
Description of drawings
The structural representation of the ATM logical design emulation platform that Fig. 1 provides for one embodiment of the invention;
Mapping relations between the content that the data flow that Fig. 2 provides for one embodiment of the invention, data configuration item and data configuration item comprise;
Mapping relations between the content that the PVC header information that the data flow that Fig. 3 provides for one embodiment of the invention, every data flow are corresponding and PVC header information comprise;
The structural representation of the ATM logical design emulation platform that Fig. 4 provides for another embodiment of the present invention;
Wrong unusually a kind of form schematic diagram of configuration file that Fig. 5 provides for one embodiment of the invention;
The form of the excited data that Fig. 6 provides for one embodiment of the invention;
The ATM cell storage inside mode schematic diagram that Fig. 7 provides for one embodiment of the invention;
The HEC synchronized state conversion schematic diagram that Fig. 8 provides for one embodiment of the invention;
The flow chart of the ATM logical design emulation mode that Fig. 9 provides for one embodiment of the invention;
The flow chart of the ATM logical design emulation mode that Figure 10 provides for another embodiment of the present invention.
Embodiment
The structural representation of the ATM logical design emulation platform that Fig. 1 provides for one embodiment of the invention.As shown in Figure 1, the platform of present embodiment comprises: passage generation module 11, channel scheduling module 12 and authentication module 13.
Wherein, passage generation module 11, be used for the data configuration item according to the excited data configuration file, excited data in the generating test use case, according to descending fixedly virtual circuit (Permanent Virtual Circuit, referred to as PVC) the PVC header information corresponding with excited data in the channel information configuration file, excited data is carried out burst process, form descending ATM cell corresponding to excited data.Wherein, the data configuration item comprises data length, data content and data amount check.
Excited data configuration file in the present embodiment is mainly used in controlling length, content and the number of excited data in every data flow, every data flow can be supported at most 32 data configuration items, can be implemented in the combination of disposing several data length, content etc. in the same emulation cycle for the same data flow.
The described data flow of various embodiments of the present invention is corresponding to the PVC passage, by data flow of excited data formation of a PVC channel transfer.In the present embodiment, the excited data that the passage generation module generates can be the excited data in single PVC passage, also can be the excited data in many PVC passage, wherein, no matter is which kind of situation, and is identical to the processing procedure of each excited data.
Fig. 2 has provided the mapping relations between the content that a kind of data flow, data configuration item and data configuration item comprise.Comprising altogether 512 data flow in Fig. 2, is 511,512 configuration files that data flow is corresponding of stream 0-stream, and noting by abridging is that PVC_DT configuration 0-PVC_DT disposes 511; Every data flow comprises 32 data configuration items, notes by abridging to be configuration 0-configuration 31; Each data configuration item includes but not limited to following information:
FLOW_ID: data flow ID number;
NUM: the number of the excited data that corresponding data stream sends;
LEN_MODE: the length pattern of excited data in the configuration data stream, fixing (FIX) arranged, increase progressively (INC), at random (RDM) three kinds of patterns;
LEN_MAX: the maximum of excited data length in the configuration data stream;
LEN_MIN: the minimum value of excited data length in the configuration data stream;
DT_MOD: the content model of excited data in the configuration data stream has FIX, INC, three kinds of patterns of RDM;
DT_MAX: the maximum of excited data content in the configuration data stream;
DT_MIN: the minimum value of excited data content in the configuration data stream.
Descending PVC channel information configuration file in the present embodiment is mainly used in storing the PVC header information of PVC passage corresponding to every data flow, head (header) information corresponding to every data flow of sending direction provide, be used for the encapsulation of cell (cells) data.The PVC header information mainly comprise data flow ID number with and corresponding generic flow control (Generic Flow Control, referred to as GFC), Virtual Path Identifier (Virtual Path Identifier, referred to as VPI), virtual path identifiers (Virtual Connection Identifier, referred to as VCI), cell abandons the information such as priority (Cell Loss Priority is referred to as CLP).Mapping relations between the content that the PVC header information that data flow, every data flow are corresponding and PVC header information comprise as shown in Figure 3, every PVC header information corresponding to data flow is the PVC configuration among Fig. 3.VPI and VCI that every data flow is corresponding unique, VPI and VCI can PVC passages of unique identification, and every PVC passage has a channel number.
Scheduling configuration file in the present embodiment be mainly used in controlling each PVC passage ATM cell send speed, namely scheduling time the interval.Present embodiment is to adopt service (the Constant Bit Rate that fixed rate can be provided, referred to as CBR) scheduling mode is example, the scheduling configuration file can be described as the CBR_SLOT configuration file, channel scheduling module 12 is according to the CBR_SLOT configuration file, the strict scheduling time interval according to fixing discharges the scheduling indication to higher level's module (being passage generation module 11), obtain descending ATM cell, realize pressing the purpose of the descending ATM cell speed of PVC channel management.The scheduling time interval here is relevant with the total bandwidth that sends excited data, and physical relationship is: the time interval=cell size of scheduling/outlet bandwidth.For example, based on SDH (Synchronous Digital Hierarchy) (Synchronous Digital Hierarchy, referred to as SDH) ATM(should be ATM over SDH) effectively outlet bandwidth be 149.76Mbps, the ATM cell size is 53*8bit, then scheduling time is spaced apart 53*8bit/149.76Mbps=2.8us.Further, the storage width of memory scheduling time needs to determine according to final transmission rate in the scheduling configuration file, and the final larger storage width of transmission rate just will be deepened accordingly.Relation between the two is as follows: storage width=outlet bandwidth/minimum scheduling granularity.For example, the effective outlet bandwidth of ATM over SDH is 149.76Mbps, and minimum scheduling granularity is 64k, and then storage width is 149.76Mbps/64K=2340.
Concrete, channel scheduling module 12 is by corresponding PVC passage, and the descending ATM cell that excited data is corresponding sends to module to be tested.
After module to be tested receives descending ATM cell, can carry out reception ﹠ disposal, the processing such as for example header error control (Header Error Correction is referred to as HEC) is synchronous, alarm, restructuring, verification, result after output is processed at last, i.e. descending result data.This descending result data is corresponding with the excited data that passage generation module 11 generates.If the processing logic of module to be tested is correct, identical with excited data or the satisfied certain relation of descending result data then, otherwise, then not identical or do not satisfy described relation.Based on this, authentication module 13 compares above-mentioned excited data and descending result data by obtaining the descending result data corresponding with above-mentioned excited data after the resume module to be tested, can realize verifying the purpose of the receive logic of module to be tested.
As shown in Figure 1, module to be tested is connected with authentication module with channel scheduling module 12 respectively and is connected.Wherein, the interface that is connected with module to be tested on the channel scheduling module 12 can be described as data stream interface, the ATM logical design emulation platform that present embodiment provides is by providing simple data stream interface, can dock with different modules to be tested easily, finish different phase, such as the test assignment of integration testing, module testing etc.
Optionally, because ATM is the agreement of transport layer, so the ATM logical design emulation platform that present embodiment provides is except carrying out the independent test the relevant logical design (being module to be tested) of ATM, can also be to connecting relevant PHY layer technology, for example SDH, Ethernet (Ethernet, referred to as ETH) model etc., module to be measured is carried out integration testing.
The ATM logical design emulation platform that present embodiment provides, mainly based on various configuration files, also provide simulation process required control logic based on the excited data in the configuration file generating test use case and configuration file, therefore so that test case can be in translation and compiling environment directly operation carry out emulation, the checking of the receive logic of test module is treated in realization, emulation all compiles test case at every turn, has improved and has treated the efficient that test module carries out logical simulation.Wherein, the ATM logical design emulation platform of present embodiment provides a kind of translation and compiling environment.
The structural representation of the ATM logical design emulation platform that Fig. 4 provides for another embodiment of the present invention.Present embodiment is based on realization embodiment illustrated in fig. 1, and as shown in Figure 4, the emulation platform of present embodiment also comprises: passage generation module 11, channel scheduling module 12 and authentication module 13, and each module also has the function of description embodiment illustrated in fig. 1.
In the present embodiment, channel scheduling module 12 also was used for before the descending ATM cell that excited data is corresponding sends to module to be tested, according to descending ATM cell abnormal corresponding to the unusual configuration file control excited data of mistake, treat the checking of the exception handling ability of test module with realization.Wherein, the unusual configuration file of mistake comprises unusual control time and Exception Type.
Wrong unusual configuration file in the present embodiment is mainly used in providing the required information of ATM cell abnormal in the control simulation process, the for example various unusual control on unusual control time and the ATM cell aspect, 32 configuration items can be supported at most, the combination of multiple abnormal behaviour in the same emulation cycle can be supported in.Wherein, the unusual configuration file of mistake can be referred to as the CTL configuration file.A kind of form of the unusual configuration file of mistake as shown in Figure 5, the unusual configuration file of this mistake comprises 32 configuration items, be respectively 31,512 data flow of configuration 0-configuration corresponding to these 32 configuration items, specifically corresponding which kind of configuration item of which bar data flow is decided on the emulation demand.As shown in Figure 5, every configuration item includes but not limited to following information in the unusual configuration file of mistake:
Time_s: the effect time started, take clock as unit;
Time_e: the effect concluding time, take clock as unit; Wherein, the time from time_s to time_e consists of the above-mentioned unusual control time, during this period of time namely, and descending ATM cell abnormal corresponding to channel scheduling module 12 control excited datas.
Mod: set the abnormal operation pattern in above-mentioned time_s and time_e time, concrete pattern includes but not limited to following several:
S_ERR: force header (English is cells header) verification single-bit (bit) mistake;
M_ERR: force many bit of cells header verification mistake;
CRC_ERR: force ATM AAL_5 frame cyclic redundancy check (CRC) code (Cyclic Redundancy Check is referred to as CRC) check errors;
LEN_ERR: force ATM AAL_5 frame length (Length is referred to as LEN) mistake;
Configuration file imports module 16.
Optionally, a kind of implementation structure of passage generation module 11 comprises as shown in Figure 4: data configuration file acquiring unit 111, group bag unit 112, sharding unit 113, header acquiring unit 114 and data capture unit 115.
Wherein, data configuration file acquiring unit 111 is connected with group bag unit 112, is used for obtaining above-mentioned excited data configuration file from the first configuration array, and the excited data configuration file is sent to group bag unit 112.Optionally, data configuration file acquiring unit 111 can send to the data configuration item in the excited data configuration file group bag unit 112 one by one, to realize the excited data configuration file is sent to the purpose of group bag unit 112.Based on this, whether the data configuration item that data configuration file acquiring unit 111 also can constantly detect in the excited data configuration file is finished, if be finished, group of notifications bag unit 112 then, be disposed with the excited data of informing group bag unit 112 these PVC passages, do not need to obtain again the data configuration item.Optionally, data configuration file acquiring unit 111 also can directly send to whole excited data configuration file group bag unit 112, the such excited data configuration file that can receive data configuration file acquiring unit 111 sends of group bag unit 112, the excited data configuration file is resolved, obtain the data configuration item.
Above-mentioned preset length is generally 48 bytes (byte).
The array of data that above-mentioned excited data the is corresponding header information array corresponding with excited data is corresponding one by one, is a kind of preferred storage inside mode.This preferred storage inside mode specifically as shown in Figure 7, each fragment data comprises 48 bytes; Excited data after the filling comprises n fragment data; The corresponding PVC header information of each fragment data, and form ATM cell with corresponding PVC header information, the PVC header information corresponding corresponding to the fragment data of same PVC passage is identical.
Because ATM agreement regulation, each scheduling all will be obtained ATM cell, if there is not effective ATM cell (effectively ATM cell refers to descending ATM cell) here, then obtain invalid (the English idle of being) ATM cell, so sharding unit 113 provides array of data corresponding to excited data whether to also have the announcement information of data to channel scheduling module 12, is conducive to channel scheduling module 12 and dispatches.
Based on above-mentioned, a kind of implementation structure of channel scheduling module 12 comprises as shown in Figure 4: scheduling unit 121, unusual control unit 122, data processing unit 123 and outlet port unit 124.
Outlet port unit 124, for descending ATM cell or the invalid ATM cell after the process abnormality processing of receive data processing unit 123 transmissions, stream interface sequential according to corresponding with module to be tested sends to module to be tested with the descending ATM cell after the abnormality processing or invalid ATM cell.The bit wide of the outlet port unit 124 here (being the width of interface) can arrange, so that connect flexibility ratio and the versatility of the emulation platform that the raising present embodiment provides with the module to be tested that is connected.For example, a kind of definition of outlet port unit 124 is as shown in table 1.
Table 1
| Signal name | Attribute | Bit wide | Describe |
| DT | Out | Configurable | ATM CELLS data |
| EN | In | 1bit | ATM CELLS data enable |
In the above-mentioned table 1, " DT " expression ATM cell data, the for example descending ATM cell after the above-mentioned abnormality processing or invalid ATM cell, the enable signal of " EN " expression ATM cell data, " In " and " Out " represents sense, " In " expression flows into the direction of interface, and the direction of interface is flowed out in " Out " expression.
In this explanation, first, second, third, fourth grade that relates in the various embodiments of the present invention only is in order to distinguish the not restriction on the numerical value.For example, first, second, third, fourth configuration array can be same configuration array, also can be different configuration array.
The ATM logical design emulation platform that the embodiment of the invention provides, only need with module to be tested in program code once compile the formation simulated environment, then based on this simulated environment, can and control test case and directly move by various configuration file generating test use cases, the checking of the receive logic of test module is treated in realization, need not all compile test case at every turn, improve and treated the efficient that test module carries out logical simulation.
Further, as shown in Figure 4, the emulation platform of present embodiment also comprises: passage receiver module 14 and passage group bag module 15.
Up PVC channel information configuration file in the present embodiment is mainly used in storing every PVC header information that data flow is corresponding, comprises data flow ID number and the information such as corresponding GFC, VPI, VCI and CLP and PVC channel number.Wherein, the ATM cell recipient can according to the PVC header information correct inquire PVC passage corresponding to data flow.The realization form of up PVC channel information configuration file can be referring to shown in Figure 3.
Passage group bag module 15, be used for according to PVC channel number corresponding to the up ATM cell that receives the valid data of the up ATM cell that receives being carried out data recombination, obtain AAL data corresponding to each PVC channel number, and the AAL data are carried out verification, the output verification result.
Optionally, passage receiver module 14 comprises: lock unit 141, Data classification unit 142 and lookup unit 143.
Wherein, lock unit 141, be used for receiving up ATM cell corresponding to upstream data that module to be tested sends, up ATM cell is carried out HEC to be processed synchronously, when synchronously success of HEC, up ATM cell is sent to the Data classification unit, the HEC head of output error and wrong time of origin when the HEC synchronization failure.The HEC synchronous state machine as shown in Figure 8.Synchronous state machine shown in Figure 8 is carried out simple declaration, before not synchronous, be in trapped state, synchronizing process is to connect than the HEC in the letter of the null hypothesis specially header field by bit correctly to finish, in case find, just enter presynchronization state, under presynchronization state, can check constantly whether the HEC of cell is correct one by one, continuous 6 HEC correctly so just enter synchronous regime, continuous when being checked through incorrect HEC 7 times under synchronous regime, can reenter trapped state.
It is synchronous that lock unit 141 is mainly used in that the up ATM cell that receives is carried out HEC, according to the ATM agreement, just can enter normal receiving course after only having synchronously.A kind of embodiment is: lock unit 141 is with the data on the real real-time inspection line after success synchronously, in case the HEC check errors occurs, lock unit 141 will stop emulation behind 200us, wait for user's subsequent operation, and the HEC head of mistake and the wrong time that occurs outputed in the log file, make things convenient for the tester to debug.The Log of HEC head mistake is with reference to as follows:
Wherein, if do not find corresponding PVC channel number, illustrate the improperly-configured of up PVC and channel number relation, directly stop emulation, and can export configuration error (ERROR) prompting, so that the tester in time carries out problem discover and takes the respective handling measure.
In addition, lookup unit 143 can also be carried out the number statistics to effective up ATM cell, with scheduling rates and the QoS performance of obtaining module to be tested.Concrete, lookup unit 143 is carried out the statistics of effective up ATM cell number according to the PVC passage, obtains the speed that receives effective up ATM cell, can effectively test out like this efficient of module schedules to be tested, and the function of relevant QOS etc.For example, as follows to the log reference of effective up ATM cell Statistical Rate according to the PVC passage:
In conjunction with the above-mentioned log explanation that makes an explanation.At aspect of performance, become 128kbps such as the rate configuration of hypothesis module to be tested a certain PVC passage, then in above-mentioned log, can see corresponding cell rate should be 301 ~ 302 about (namely 128000/8/53).For QOS also be, such as in the hypothesis module to be tested the transmission of carrying out data according to the priority of passage being arranged, if two PVC passages of module so to be tested have the data flow of linear speed, can see in above-mentioned log that so the cell rate of the data flow of the PVC passage that priority is high should be higher than the cell rate of the data flow of the low PVC passage of priority.
Based on above-mentioned, a kind of implementation structure of passage group bag module 15 comprises as shown in Figure 4: group is detectd unit 151 and frame processing unit 152.
By as seen above-mentioned, the emulation platform of present embodiment is by passage receiver module 14 and passage group bag module 15, can effectively treat the cell data that test module sends here and carry out counting rate, can test reliably the correctness of the interrelated logics such as the schedule speed of module to be tested and QOS, testing for the performance for the treatment of test module provides effective foundation.
In this explanation, above-mentioned passage receiver module 14 and passage group bag module 15 can consist of the up emulation passage that the descending performance for the treatment of test module is tested, and aforementioned channels generation module 11, channel scheduling module 12 and authentication module 13 can consist of the descending emulation passage that the uplink receiving logic for the treatment of test module is tested.
In an optional execution mode of present embodiment, as shown in Figure 4, the emulation platform of present embodiment also comprises: configuration file imports module 16.
Configuration file imports module 16, be used for before emulation begins, with all configuration files, such as in advance excited data configuration file, descending PVC channel information configuration file, scheduling configuration file, up PVC channel information configuration file, the unusual configuration file of mistake etc. being imported in the corresponding configuration array.Configuration file imports module 16 and specifically can in advance excited data configuration file, descending PVC channel information configuration file and scheduling configuration file be imported respectively in first, second, and third configuration array.Configuration array in the various embodiments of the present invention refers to the memory space in the ATM logical design emulation platform of present embodiment, such as RAM etc., each module can directly read each configuration array in the ATM logical design emulation platform of present embodiment, in addition, different configuration files can be stored in respectively independently in the configuration array, also can be stored in the identical configuration array.
Optionally, configuration file imports module 16 and is connected with the header acquiring unit with the data configuration file acquiring unit 111 in the passage generation module 11 and is connected, configuration file import module 16 also with channel scheduling module 12 in scheduling unit 121 be connected with the control unit of being connected 122, configuration file importing module 16 also is connected with lookup unit 143 in the passage receiver module 14.
The ATM logical design emulation platform that present embodiment provides imports module 16 by configuration file, has reduced in simulation process mutual between each module and configuration file, effectively raises simulation efficiency, is conducive to improve the quality of module output to be tested.
In an optional execution mode of present embodiment, as shown in Figure 4, the ATM logical design emulation platform that present embodiment provides also comprises: configuration file generation module 17.
Configuration file generation module 17 is used for the various configuration files by Excel instrument generation text formatting, such as excited data configuration file, descending PVC channel information configuration file and scheduling configuration file etc.Except excited data configuration file, descending PVC channel information configuration file and scheduling configuration file, configuration file generation module 17 also can generate other configuration files that use in the simulation process by the Excel instrument, and these configuration files also are text formattings.Configuration file generation module 17 imports module 16 with configuration file and is connected, and being used for importing module 16 to configuration file provides various configuration files.
The emulation platform that present embodiment provides, introduced the Excel instrument on the basis of above-mentioned each module, more friendly configuration file design interface is provided, be conducive to the generation of test case, greatly the tester is freed from the uninteresting and loaded down with trivial details test case of writing the txt form, make it more to pay close attention to checking itself, be conducive to improve simulated mass.
The flow chart of the ATM logical design emulation mode that Fig. 9 provides for one embodiment of the invention.As shown in Figure 9, the method for present embodiment comprises:
The executive agent of present embodiment can be the ATM logical design verification platform that above-described embodiment provides, but is not limited to this.
The detailed process of the ATM logical design verification method that present embodiment provides can referring to the description among the above-mentioned ATM logical design verification platform embodiment, be not described in detail in this.
The ATM logical design verification method of present embodiment mainly carries out based on various configuration files, based on the excited data of configuration file in not only can generating test use case, and configuration file also provides simulation process required control logic, so that the method for present embodiment can directly be carried out in the environment that has compiled, and do not need each emulation or each test case to recompilate, improved and treated the efficient that test module carries out logical simulation.
The flow chart of the ATM logical design verification method that Figure 10 provides for another embodiment of the present invention.Present embodiment is based on realization embodiment illustrated in fig. 9, and as shown in figure 10, the method for present embodiment also comprises:
Up ATM cell corresponding to upstream data that step 904, reception module to be tested send carried out HEC to up ATM cell and processed synchronously, and search up PVC channel information configuration file, obtains PVC channel number corresponding to up ATM cell.
What above-mentioned steps 901-step 903 was described is the process that the receive logic of ATM logical design is verified, what step 904 and step 905 were described is the process that transmission logic and the performance of ATM logical design are verified.These two processes can be separate, and then the sequencing of the process of the process of step 901-step 903 description and the description of step 904-step 905 is not done restriction.In addition, these two processes also can consist of a winding process, be that up ATM cell corresponding to upstream data that module to be tested sends in step 904 can be the descending result data corresponding with above-mentioned excited data after module to be tested is processed in step 902, so just can consist of the loopback test process, based on this, step 904 and step 905 are carried out after the process that step 901-step 903 is described.
In an optional execution mode, above-mentioned the descending ATM cell that excited data is corresponding sends to module to be tested according to the scheduling time in the scheduling configuration file, carries out can comprising before the reception ﹠ disposal for module to be tested:
According to descending ATM cell abnormal corresponding to the unusual configuration file of mistake control excited data, with the checking of the exception handling ability of realizing treating test module, wherein, the unusual configuration file of mistake comprises unusual control time and Exception Type.
In an optional execution mode, above-mentioned according to the data configuration item in the excited data configuration file, excited data in the generating test use case, according to the PVC header information corresponding with excited data in the descending PVC channel information configuration file, excited data is carried out burst processes, form descending ATM cell corresponding to excited data and comprise:
From the first configuration array, obtain the excited data configuration file, from the second configuration array, obtain descending PVC channel information configuration file; Generate downlink data according to the data configuration item in the excited data configuration file, according to ATM ALL agreement downlink data is packaged, generate excited data; Excited data is filled into excited data is carried out burst behind the integral multiple of preset length and obtain fragment data corresponding to excited data, the fragment data that excited data is corresponding stores into respectively in array of data corresponding to excited data, from descending PVC channel information configuration file, obtain PVC header information corresponding to excited data, the PVC header information that excited data is corresponding stores in header information array corresponding to excited data, forms above-mentioned descending ATM cell.Wherein, the array of data that excited data the is corresponding header information array corresponding with excited data is corresponding one by one.
In an optional execution mode, above-mentioned according to the scheduling time in the scheduling configuration file, the descending ATM cell that excited data is corresponding sends to module to be tested, carries out reception ﹠ disposal for module to be tested and comprises:
From the 3rd configuration array, obtain the scheduling configuration file, send dispatch command according to the scheduling time of scheduling in the configuration file; According to dispatch command, when in array of data corresponding to excited data, also having data, from array of data corresponding to excited data and header information array, obtain descending ATM cell, when in array of data corresponding to excited data, not having data, from preset group, obtain invalid ATM cell; From the 4th configuration array, obtain wrong unusual configuration file, and generate the wrong control command corresponding with Exception Type in the wrong unusually configuration file in the unusual control time in the unusual configuration file of mistake; According to wrong control command descending ATM cell or invalid ATM cell are carried out abnormality processing; Stream interface sequential according to corresponding with module to be tested sends to module to be tested with the descending ATM cell after the abnormality processing or invalid ATM cell.
In an optional execution mode, up ATM cell corresponding to upstream data that above-mentioned reception module to be tested sends, up ATM cell is carried out HEC processes synchronously, and search up PVC channel information configuration file, obtain PVC channel number corresponding to up ATM cell and comprise:
Receive up ATM cell corresponding to upstream data that module to be tested sends, up ATM cell is carried out HEC process synchronously, when the HEC synchronization failure, the HEC head of output error and wrong time of origin; When synchronously success of HEC, up ATM cell to be classified, statistics is obtained the number of invalid up ATM cell and effective up ATM cell in the upstream data, whether reaches linear speed with the speed of knowing module to be tested; From the 5th configuration array, obtain up PVC channel information configuration file, according to the PVC header information in effective up ATM cell, search up PVC channel information configuration file to obtain PVC channel number corresponding to effective up ATM cell, if do not get access to PVC channel number corresponding to effective up ATM cell, output configuration error information also finishes simulation operations.
Based on above-mentioned, the method for present embodiment also comprises: effective up ATM cell is carried out the number statistics, with scheduling rates and the QoS performance of obtaining module to be tested.Present embodiment can effectively be treated the cell data that test module sends here and carry out counting rate, can test reliably the correctness of the interrelated logics such as the schedule speed of module to be tested and QOS, and testing for the performance for the treatment of test module provides effective foundation.
In an optional execution mode, above-mentionedly according to PVC channel number corresponding to up ATM cell the valid data in the up ATM cell are carried out data recombination, obtain AAL data corresponding to each PVC channel number, and the AAL data are carried out verification, output verification is the result comprise:
According to the PVC channel number that effective up ATM cell is corresponding valid data in effective up ATM cell are recombinated, obtain AAL data corresponding to upstream data, the AAL data are stored in array of data corresponding to upstream data, and send and finish receiving indication information; According to finishing receiving indication information, from array of data corresponding to upstream data, obtain the AAL data, the AAL data are fixed a verification, CRC check and/or length check, when check errors occurring, output error check results and the AAL data that make a mistake.
In an optional execution mode, above-mentioned according to the data configuration item in the excited data configuration file, excited data in the generating test use case, according to the PVC header information corresponding with excited data in the descending fixedly virtual circuit PVC channel information configuration file, excited data is carried out burst processes, form descending ATM cell corresponding to excited data and comprise before:
Before emulation begins, excited data configuration file, descending PVC channel information configuration file and scheduling configuration file are imported in the corresponding configuration array.Reduce like this in simulation process mutual between each module and configuration file, effectively raised simulation efficiency, be conducive to improve the quality of module output to be tested.
In an optional execution mode, above-mentioned excited data configuration file, descending PVC channel information configuration file and scheduling configuration file are imported in the corresponding configuration array comprises before:
Generate the excited data configuration file of text formatting, descending PVC channel information configuration file and scheduling configuration file by the Excel instrument.Present embodiment is by introducing the Excel instrument, more friendly configuration file design interface is provided, be conducive to the generation of test case, greatly the tester is freed from the uninteresting and loaded down with trivial details test case of writing the txt form, make it more to pay close attention to checking itself, be conducive to improve simulated mass.
The executive agent of present embodiment and each execution mode thereof can be the ATM logical design verification platform that previous embodiment provides, and the detailed process of each step repeats no more, and sees the description among the aforementioned ATM logical design verification platform embodiment for details.
To sum up, the concrete following beneficial effect of the ATM logical design verification method that present embodiment provides: 1, can independently be configured the excited data of each PVC data channel and the transmission rate of excited data, improve the flexibility of emulation, and all configuration files all read in storage in the moment unification that emulation begins, reduce like this file interaction in simulation process, effectively raised simulation efficiency.2, provide easily model interface, can with are connected different physical layer model and connect, carry out integration testing and also can carry out separately the individual module test, have good versatility.3, for the various generations of forcing mistake, contingent single bit mistake during for example HEC delimits, the pressure of many bit mistake occurs, and the crc of AAL data forces mistake, and LEN forces mistake, can effectively carry out various abnormality tests.4, the cell of data burst that can effectively send here module to be measured carries out counting rate, can test reliably scheduling and the QOS interrelated logic correctness of module to be measured.5, introduced excel, more friendly incentives interface is provided, greatly the tester has been freed from the uninteresting and loaded down with trivial details test case of writing the txt form, more paid close attention to and checking itself.
One embodiment of the invention provides a kind of equipment, comprises ATM logical design emulation platform.Wherein, ATM logical design emulation platform can be arbitrary ATM logical design emulation platform that previous embodiment of the present invention provides, and its operation principle and implementation structure can referring to the description of previous embodiment, not repeat them here.
The equipment that present embodiment provides can be various equipment with certain computing ability, such as being server, computer etc.
The equipment that present embodiment provides comprises the ATM logical design emulation platform that the embodiment of the invention provides, can carry out equally the flow process of the ATM logical design emulation mode that the embodiment of the invention provides, therefore, have equally and improved the efficient treating test module and carry out logical simulation, have the stronger beneficial effects such as versatility.
One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each embodiment of the method can be finished by the relevant hardware of program command.Aforesaid program can be stored in the computer read/write memory medium.This program is carried out the step that comprises above-mentioned each embodiment of the method when carrying out; And aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above each embodiment is not intended to limit only in order to technical scheme of the present invention to be described; Although with reference to aforementioned each embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps some or all of technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the scope of various embodiments of the present invention technical scheme.
Claims (17)
1. an asynchronous transfer mode ATM logical design emulation platform is characterized in that, comprising:
The passage generation module, be used for the data configuration item according to the excited data configuration file, excited data in the generating test use case, according to the PVC header information corresponding with described excited data in the descending fixedly virtual circuit PVC channel information configuration file, described excited data is carried out burst to be processed, form descending ATM cell corresponding to described excited data, described data configuration item comprises data length, data content and data amount check;
The channel scheduling module is connected with described passage generation module, is used for the scheduling time according to the scheduling configuration file, and the descending ATM cell that described excited data is corresponding sends to module to be tested, carries out reception ﹠ disposal for described module to be tested;
Authentication module is used for obtaining the descending result data corresponding with described excited data after the described resume module to be tested, described excited data and described descending result data is compared, to verify the receive logic of described module to be tested.
2. ATM logical design emulation platform according to claim 1, it is characterized in that, described channel scheduling module also was used for before the descending ATM cell that described excited data is corresponding sends to described module to be tested, control descending ATM cell abnormal corresponding to described excited data according to the unusual configuration file of mistake, to realize that the unusual configuration file of described mistake comprises unusual control time and Exception Type to the checking of the exception handling ability of described module to be tested.
3. ATM logical design emulation platform according to claim 2 is characterized in that, described passage generation module comprises:
The data configuration file acquiring unit is used for obtaining described excited data configuration file from the first configuration array, and described excited data configuration file is sent to group bag unit;
Described group of bag unit, be used for generating downlink data according to the data configuration item of described excited data configuration file, according to ATM Adaptation Layer ALL agreement described downlink data is packaged, generate described excited data, described excited data is sent to sharding unit and described authentication module;
Described sharding unit, obtain fragment data corresponding to described excited data for behind the integral multiple that described excited data is filled into preset length described excited data being carried out burst, the fragment data that described excited data is corresponding stores into respectively in array of data corresponding to described excited data, from the beginning obtain PVC header information corresponding to described excited data in the information acquisition unit, the PVC header information that described excited data is corresponding stores in header information array corresponding to described excited data, forms described descending ATM cell; Wherein, the array of data that described excited data the is corresponding header information array corresponding with described excited data is corresponding one by one;
The header acquiring unit is used for obtaining described descending PVC channel information configuration file from the second configuration array, and the PVC header information corresponding with described excited data in the described descending PVC channel information configuration file is offered described sharding unit;
Data capture unit, be used for receiving the dispatch command that described channel scheduling module sends, according to described dispatch command, from array of data corresponding to described excited data and header information array, obtain described descending ATM cell or from preset group, obtain invalid ATM cell, and described descending ATM cell or invalid ATM cell are offered described channel scheduling module.
4. ATM logical design emulation platform according to claim 3 is characterized in that, described sharding unit also is used for providing array of data corresponding to described excited data whether to also have the announcement information of data to described channel scheduling module;
Described channel scheduling module comprises:
Scheduling unit, be used for obtaining described scheduling configuration file from the 3rd configuration array, receive the described announcement information that described sharding unit sends, and according to the scheduling time in the described scheduling configuration file and described announcement information, send described dispatch command to described data capture unit;
Unusual control unit, be used for obtaining the unusual configuration file of described mistake from the 4th configuration array, and generate the wrong control command corresponding with Exception Type in the unusual configuration file of described mistake in the unusual control time in the unusual configuration file of described mistake, described wrong control command is sent to data processing unit;
Described data processing unit, be used for receiving described descending ATM cell or the invalid ATM cell that described data capture unit provides, according to described wrong control command the described descending ATM cell or the invalid ATM cell that receive are carried out abnormality processing, the descending ATM cell after the abnormality processing or invalid ATM cell are sent to outlet port unit;
Described outlet port unit is used for according to the stream interface sequential corresponding with described module to be tested, and the descending ATM cell after the abnormality processing or invalid ATM cell are sent to described module to be tested.
5. each described ATM logical design emulation platform is characterized in that according to claim 1-4, also comprises:
The passage receiver module, be used for receiving up ATM cell corresponding to upstream data that described module to be tested sends, described up ATM cell is carried out HEC to be processed synchronously, and search up PVC channel information configuration file, obtain PVC channel number corresponding to described up ATM cell, the valid data in the described up ATM cell and PVC channel number corresponding to described up ATM cell are sent to passage group bag module;
Described passage group bag module, be used for according to PVC channel number corresponding to the described up ATM cell that receives the valid data of the described up ATM cell that receives being carried out data recombination, obtain AAL data corresponding to each PVC channel number, and described AAL data are carried out verification, the output verification result.
6. ATM logical design emulation platform according to claim 5 is characterized in that, described passage receiver module comprises:
Lock unit, be used for receiving up ATM cell corresponding to upstream data that described module to be tested sends, described up ATM cell is carried out header error control HEC to be processed synchronously, when synchronously success of HEC, described up ATM cell is sent to the Data classification unit, the HEC head of output error and wrong time of origin when the HEC synchronization failure;
The Data classification unit, be used for receiving the described up ATM cell that described lock unit sends, described up ATM cell is classified, statistics is obtained the number of invalid up ATM cell and effective up ATM cell in the described upstream data, whether reach linear speed with the speed of knowing described module to be tested, and described effective up ATM cell is sent to lookup unit;
Described lookup unit, be used for obtaining described up PVC channel information configuration file from the 5th configuration array, according to the PVC header information in described effective up ATM cell, search described up PVC channel information configuration file to obtain PVC channel number corresponding to described effective up ATM cell, if get access to PVC channel number corresponding to described effective up ATM cell, valid data in described effective up ATM cell and PVC channel number corresponding to described effective up ATM cell are sent to described passage group bag module, if do not get access to PVC channel number corresponding to described effective up ATM cell, output configuration error information also finishes simulation operations.
7. ATM logical design emulation platform according to claim 6 is characterized in that,
Described lookup unit also is used for described effective up ATM cell is carried out the number statistics, with scheduling rates and the service quality QoS performance of obtaining described module to be tested.
8. according to claim 6 or 7 described ATM logical design emulation platforms, it is characterized in that described passage group bag module comprises:
The framing unit, valid data and PVC channel number corresponding to described effective up ATM cell for the described effective up ATM cell that receives described lookup unit transmission, and according to PVC channel number corresponding to described effective up ATM cell the valid data in the described effective up ATM cell that receives are recombinated, obtain AAL data corresponding to described upstream data, described AAL data are stored in array of data corresponding to described upstream data, and send and receive to frame processing unit and to finish indication information;
Described frame processing unit, be used for according to the described indication information that finishes receiving, from array of data corresponding to described upstream data, obtain described AAL data, described AAL data are fixed a verification, CRC check and/or length check, when check errors occurring, output error check results and the described AAL data that make a mistake.
9. an asynchronous transfer mode ATM logical design emulation mode is characterized in that, comprising:
According to the data configuration item in the excited data configuration file, excited data in the generating test use case, according to the PVC header information corresponding with described excited data in the descending fixedly virtual circuit PVC channel information configuration file, described excited data is carried out burst to be processed, form descending ATM cell corresponding to described excited data, described data configuration item comprises data length, data content and data amount check;
According to the scheduling time in the scheduling configuration file, the descending ATM cell that described excited data is corresponding sends to module to be tested, carries out reception ﹠ disposal for described module to be tested;
Obtain the descending result data corresponding with described excited data after the described resume module to be tested, described excited data and described descending result data are compared, to verify the receive logic of described module to be tested.
10. ATM logical design emulation mode according to claim 9, it is characterized in that, described the descending ATM cell that described excited data is corresponding sends to module to be tested according to the scheduling time in the scheduling configuration file, carries out comprising before the reception ﹠ disposal for described module to be tested:
Control descending ATM cell abnormal corresponding to described excited data according to the unusual configuration file of mistake, to realize that the unusual configuration file of described mistake comprises unusual control time and Exception Type to the checking of the exception handling ability of described module to be tested.
11. ATM logical design emulation mode according to claim 10, it is characterized in that, described according to the data configuration item in the excited data configuration file, excited data in the generating test use case, according to the PVC header information corresponding with described excited data in the descending fixedly virtual circuit PVC channel information configuration file, described excited data is carried out burst processes, form descending ATM cell corresponding to described excited data and comprise:
From the first configuration array, obtain described excited data configuration file, from the second configuration array, obtain described descending PVC channel information configuration file;
Generate downlink data according to the data configuration item in the described excited data configuration file, according to ATM Adaptation Layer ALL agreement described downlink data is packaged, generate described excited data;
Described excited data is filled into described excited data is carried out burst behind the integral multiple of preset length and obtain fragment data corresponding to described excited data, the fragment data that described excited data is corresponding stores into respectively in array of data corresponding to described excited data, from described descending PVC channel information configuration file, obtain PVC header information corresponding to described excited data, the PVC header information that described excited data is corresponding stores in header information array corresponding to described excited data, forms described descending ATM cell; Wherein, the array of data that described excited data the is corresponding header information array corresponding with described excited data is corresponding one by one.
12. ATM logical design emulation mode according to claim 11, it is characterized in that, described according to the scheduling time in the scheduling configuration file, the descending ATM cell that described excited data is corresponding sends to module to be tested, carries out reception ﹠ disposal for described module to be tested and comprises:
From the 3rd configuration array, obtain described scheduling configuration file, send dispatch command according to the scheduling time in the described scheduling configuration file;
According to described dispatch command, when in array of data corresponding to described excited data, also having data, from array of data corresponding to described excited data and header information array, obtain described descending ATM cell, when in array of data corresponding to described excited data, not having data, from preset group, obtain invalid ATM cell;
From the 4th configuration array, obtain the unusual configuration file of described mistake, and generate the wrong control command corresponding with Exception Type in the unusual configuration file of described mistake in the unusual control time in the unusual configuration file of described mistake;
According to described wrong control command described descending ATM cell or invalid ATM cell are carried out abnormality processing;
According to the stream interface sequential corresponding with described module to be tested, the descending ATM cell after the abnormality processing or invalid ATM cell are sent to described module to be tested.
13. each described ATM logical design emulation mode is characterized in that according to claim 9-12, also comprises:
Receive up ATM cell corresponding to upstream data that described module to be tested sends, described up ATM cell is carried out header error control HEC to be processed synchronously, and search up PVC channel information configuration file, obtain PVC channel number corresponding to described up ATM cell;
The PVC channel number corresponding according to described up ATM cell carries out data recombination to the valid data in the described up ATM cell, obtains AAL data corresponding to each PVC channel number, and described AAL data are carried out verification, the output verification result.
14. ATM logical design emulation mode according to claim 13, it is characterized in that, up ATM cell corresponding to upstream data that the described module to be tested of described reception sends, described up ATM cell is carried out header error control HEC to be processed synchronously, and search up PVC channel information configuration file, obtain PVC channel number corresponding to described up ATM cell and comprise:
Receive up ATM cell corresponding to upstream data that described module to be tested sends, described up ATM cell is carried out HEC process synchronously, when the HEC synchronization failure, the HEC head of output error and wrong time of origin;
When synchronously success of HEC, described up ATM cell to be classified, statistics is obtained the number of invalid up ATM cell and effective up ATM cell in the described upstream data, whether reaches linear speed with the speed of knowing described module to be tested;
From the 5th configuration array, obtain described up PVC channel information configuration file, according to the PVC header information in described effective up ATM cell, search described up PVC channel information configuration file to obtain PVC channel number corresponding to described effective up ATM cell, if do not get access to PVC channel number corresponding to described effective up ATM cell, output configuration error information also finishes simulation operations.
15. ATM logical design emulation mode according to claim 14 is characterized in that, also comprises:
Described effective up ATM cell is carried out the number statistics, with scheduling rates and the service quality QoS performance of obtaining described module to be tested.
16. according to claim 14 or 15 described ATM logical design emulation modes, it is characterized in that, describedly according to PVC channel number corresponding to described up ATM cell the valid data in the described up ATM cell are carried out data recombination, obtain AAL data corresponding to each PVC channel number, and described AAL data are carried out verification, output verification is the result comprise:
According to the PVC channel number that described effective up ATM cell is corresponding valid data in described effective up ATM cell are recombinated, obtain AAL data corresponding to described upstream data, described AAL data are stored in array of data corresponding to described upstream data, and send and finish receiving indication information;
According to the described indication information that finishes receiving, from array of data corresponding to described upstream data, obtain described AAL data, described AAL data are fixed a verification, CRC check and/or length check, when check errors occurring, output error check results and the described AAL data that make a mistake.
17. an equipment is characterized in that, comprising: each described asynchronous transfer mode ATM logical design emulation platform of claim 1-8.
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