CN102868403B - A kind of test macro testing analog to digital converter salient features index - Google Patents

Abstract

The present invention discloses a kind of test macro testing analog to digital converter salient features index, with one have fabulous phase make an uproar characteristic the first signal source as sampling clock source, fabulous phase is had to make an uproar the second signal source of characteristic as mimic input signal with one, the input frequency of the first and second signal sources and amplitude are all adjustable, the mimic input signal amplified through prime amplifier together converts numerary signal to by analog to digital converter with the sampling clock input signal after clock circuit conversion, simulating signal converts the data acquisition module after data signal to, its digital collection module carried for logic analyzer or FPGA. by ADC salient features index in test digital receiver, can be the leading indicators such as the detection perform of whole receiver system, dynamicrange, sensitivity and bring reference value, for problem in the design of receiving apparatus complete machine is positioned useful effects such as providing important references by product design teacher fast and accurately.

Description

A kind of test macro testing analog to digital converter salient features index

Technical field

The present invention relates to digital if receiver and Software Radio Theory, in particular to a kind of test macro testing analog to digital converter salient features index.

Background technology

It is known that, in digital if receiver, analog to digital conversion is a very important link, ADC performance quality is related to the performance of whole receiving apparatus, so for numerary signal index (as without parasitic dynamicrange (SFDR), signal to noise ratio (SNR), signal and noise and distortion ratio (SINAD), conversion figure place, conversion speed) test be significantly. By ADC salient features index in test digital receiver, can be the detection perform of whole receiver system, dynamicrange, the leading indicators such as sensitivity bring reference value, by the test of ADC performance on digital receiver unit can be hardware circuit design teacher to the good and bad offer reference of the electromagnetism interference of printed board.

There is the inaccurate technical problem of test index in the test macro of existing test analog to digital converter performance index.

Summary of the invention

The object of the present invention is applied to digital receiver, it is proposed to a kind of test macro testing salient features index technology after ADC of simulating signal in digital receiver. The invention solves the problem of receiving apparatus overall performance test, for product design teacher is quick, in being designed by receiving apparatus complete machine accurately, problem positions useful effects such as providing important references. This technology realizes simple, and highly versatile, this testing method can be adapted to the analog to digital converter of any model.

In order to reach foregoing invention object, the present invention is achieved through the following technical solutions for solving its technical problem:

Test a test macro for analog to digital converter salient features index, for testing the performance index that simulating signal is carried out analog-to-digital analog to digital converter, comprising: sampling clock source, digital collection module, wherein:

Sampling clock source: characteristic of making an uproar mutually meets the first signal source of preset requirement as its sampling clock source, one has the mimic input signal of second signal source as analog to digital converter that characteristic of making an uproar mutually meets preset requirement, and the input frequency of the first and second signal sources and amplitude are all adjustable;

Analog to digital converter: the mimic input signal for amplifying through prime amplifier together converts numerary signal to by described analog to digital converter with the sampling clock input signal after clock circuit conversion;

Simulating signal converts the data acquisition module after data signal to, its digital collection module carried for logic analyzer or FPGA, if getting the useful data counted in the digital collection modules acquiring data carried by FPGA is stored in the RAM of FPGA, statistical conversion imports to after becoming dat file and draws test result in test procedure, numerary signal rear end after conversion does not arrange digital collection hardware, or reading useful point data by this type of data gathering testing tool of logic analyzer, statistical conversion imports to after becoming dat file and draws test result in test procedure.

According to the test macro of the test analog to digital converter salient features index described in the better embodiment of the present invention, described first signal source front end arranges a bandpass filter.

According to the test analog to digital converter salient features index described in the better embodiment of the present invention test macro, described first signal source is joined mutually with the source signal in second signal source.

According to the test analog to digital converter salient features index described in the better embodiment of the present invention test macro, described in enter analog to digital converter input signal maximum amplitude than full amplitude reduce 1dB.

According to the test analog to digital converter salient features index described in the better embodiment of the present invention test macro, after the described data collected preserve with dat file layout, it is carried out frequency domain FFT process, the limited data counted are done frequency domain process by the one piece of data intercepting numerary signal, and comprising the treating processes of window function, it may also be useful to Hanning window makes the cycle match of window function and input signal.

According to the test analog to digital converter salient features index described in the better embodiment of the present invention test macro, its constraint condition is:

For discrete digital signal, being the combination by discrete point one by one, also form signal frequency spectrum by N number of discrete point in frequency in time domain, its frequency is evenly distributed in [0,2 ��], thenShow that equivalence at discrete domain signal energy is:

$E=\underset{n=1}{\overset{N}{\Σ}}|f\left(n\right){|}^2=\underset{k=1}{\overset{N}{\Σ}}|F\left(k\right){|}^2*\frac{1}{N}.$

Compared with prior art, there is following technique effect in the present invention:

The present invention is a kind of technology that can be used for testing analog to digital converter performance index, owing to this technology is by above-mentioned hardware platform image data, then draws test result in data importing test software. Whole testing algorithm is all complete with the software test of computer, it is not necessary to extra hardware, and testing method highly versatile, reliability height, place on probation is many. The index that this invention can be supplied to these product performance of product design teacher with reference to and fast, in being designed by receiving apparatus complete machine accurately, problem positions.

Accompanying drawing explanation

The hardware platform that accompanying drawing is specific embodiment of the invention ADC performance test builds block diagram.

Embodiment

The present invention is described in further detail to lift a specific embodiment below in conjunction with accompanying drawing.

FIGS, a kind of test analog to digital converter salient features refers to calibration method, with one have fabulous phase make an uproar characteristic the first signal source as sampling clock source 1, fabulous phase is had to make an uproar the second signal source of characteristic as mimic input signal 2 with one, input frequency and the amplitude of described first and second signal sources are all adjustable, the mimic input signal amplified through prime amplifier 3 together converts numerary signal to by analog to digital converter (ADC) 5 with the sampling clock input signal after clock circuit 4 conversion, this numerary signal together carries out data gathering by logic analyzer 6 with another road sampling clock input signal after clock circuit 4 conversion, or it is transferred to the digital collection module 8 of digital if receiver 7. digital collection module 8 is transferred in computer 10 through USB cable 9 to carry out ADC performance analysis.

A universal method of assessment ADC performance is sine wave curve matching. If input signal is pure wave, and ADC is desirable, so that it may produce certain Ideal graph. In general, different from figure ideally by the actual output figure of ADC, owing to noise exists always, code level conversion also has some uncertain. In order to reduce this kind of uncertainty, it is necessary to a large amount of data points. Assume that noise has zero-mean and normal distribution, so that it may to calculate estimated accuracy. Data record be from the continuous wave with special parameter admission and make following provisions:

1, with the source having fabulous phase to make an uproar as the input of signal and clock

Test hardware platform is mainly based on the hardware circuit of the ADC device needing test, fabulous phase is had to make an uproar the crystal oscillator of characteristic or signal source as sampling clock source 1 with one, fabulous phase is had to make an uproar the signal source of characteristic as mimic input signal 2 with one, the input frequency in this source and amplitude are all adjustable, and the source signal as used two signal sources need to ensure that two signal sources produce is joined mutually. With two make an uproar mutually fabulous source as analog to digital converter 5 clock source input and signal source input, it is provided that need to through a bandpass filter to the source of the input signal of receiving apparatus. In the path of sampling clock, it should not have logic gates, if clock edge there being shake can cause deviation when adopting data, the level value of actual samples is made to also have phase jitter error except there is quantizing error between true value. Particularly, when clock signal frequency value is more high, when shake exists, the sampling true value of data deviation out is more big. Numerary signal after conversion as the useful numerary signal counted being stored in the RAM of FPGA with the data observation acquisition software that FPGA carries through FPGA, if gathering the numerary signal counted in a large number of equipment data available acquisition instrument collection without hardware and storing.

2, the maximum amplitude of input signal reduces 1dB input than full amplitude

The power gain G=Po/Pi of linear system when small-signal is constant, the big system to a certain extent of signal starts saturated (power P o starts compression), signal power can not be linear increase, namely power gain G'=Po/Pi start compression, there is a 1dB gain compression point. Therefore enter analog to digital converter 5 peak signal power input and should be less than 1dB test than full amplitude.

3, numerary signal is done the FFT windowing process of number of effective points

Data without point of accumulation can not carry out the analysis of data in a practical situation, and the length in its time domain must be retrained by input signal to some extent, and namely the limited data counted are done frequency domain process by the one piece of data of intercepting input signal. Owing to sampling effect becomes periodically, the frequency spectrum of output signal is also periodic. Input signal is periodic relative to N all the time, if the cycle of window function and signal unmatched words, so input signal will be no longer a continuous print sine wave, but be split into many discontinuous sections, and its result there is a lot of false spectrum string on frequency domain.

In order to reduce discontinuity or even elimination. Simple rectangular window is replaced herein with special window. The secondary lobe of special window is lower than rectangular window, has many different types of window functions can reduce discontinuity, and a kind of method of assessment window function performance measures main lobe width and sidelobe level exactly. For receiving apparatus, low sidelobe means that this can obtain high dynamicrange, and wide main lobe can make frequency resolving power be deteriorated. Consider so the selection of window function normally carries out compromise between frequency resolving power and dynamicrange. What test procedure was selected herein is Hanning window, it is possible to reach more satisfactory effect. After whole signal windowing process, by the smoothness at window function edge, can eliminate and not mate problem. Although the energy of master signal is decayed to some extent, but whole noise power also declines to some extent. The advantage processing input signal with FFT is that calculated amount is few, is beneficial to real-time process, practical, it is possible to be suitable for the collection with any data point.

4, the energy spectrum analysis of signal

The energy of energy spectrum and power spectrum expression signal and power density are in a frequency domain with the changing conditions of frequency, and it is to the distribution of the energy (or power) of research signal, it is resolved that the problems such as the frequency band that signal occupies have important effect. By the theory of the energy spectrum of continuous signal and power spectrum, this can also use and discrete digital signal simultaneously, can know that the energy equivalence of signal in time domain is in the energy of signal in frequency domain, namely signal is after discrete Fourier changes, its total energy remains unchanged, and this meets law of conservation of energy. Doing now following mathematical analysis, by the energy relationship of continuous signal f (t), the energy of signal is:

$E={\∫}_{-\mathrm{\∞}}^{\mathrm{\∞}}|f\left(t\right){|}^{2}dt=\frac{1}{2\mathrm{\π}}{\∫}_{-\mathrm{\∞}}^{\mathrm{\∞}}|F\left(\mathrm{\ω}\right){|}^{2}d\mathrm{\ω}---\left(1\right)$

In above-mentioned formula (1)For the total energy of signal in time domain,For the total energy of signal in frequency domain. Wherein f (t) is signal voltage or electric current, the spectral density that F (��) is f (t).

For discrete digital signal, time domain is the combination by discrete point one by one, frequency also forms signal frequency spectrum by N number of discrete point in fact. Its frequency is evenly distributed in [0,2 ��], then (1) formula of substitution, it is possible to show that equivalence at discrete domain signal energy is:

$E=\underset{n=1}{\overset{N}{\Σ}}|f\left(n\right){|}^2=\underset{k=1}{\overset{N}{\Σ}}|F\left(k\right){|}^2*\frac{1}{N}---\left(2\right)$

Wherein, N is that frequency domain sample is counted, and n is time variable, and k is frequency variable.

There is above-mentioned constraint, so that it may data are carried out dynamicrange (SFDR), signal to noise ratio (SNR), signal and noise and distortion ratio (SINAD) according to mathematical algorithm, conversion figure place, changes the test of speed.

In sum. The present invention has used specific algorithm and certain constraint condition, the testing performance index realizing any analog to digital converter that can be correct. This invention has that hardware platform is built simply, software test reliability height, easily realization feature, and there is certain versatility, can be widely used in similar receiver performance test macro.

That is, a kind of test macro testing analog to digital converter salient features index, for testing the performance index that simulating signal carries out analog-to-digital analog to digital converter, comprising: sampling clock source, digital collection module, wherein:

Sampling clock source: characteristic of making an uproar mutually meets the first signal source of preset requirement as its sampling clock source, one has the mimic input signal of second signal source as analog to digital converter that characteristic of making an uproar mutually meets preset requirement, and the input frequency of the first and second signal sources and amplitude are all adjustable;

Analog to digital converter: the mimic input signal for amplifying through prime amplifier together converts numerary signal to by described analog to digital converter with the sampling clock input signal after clock circuit conversion;

Simulating signal converts the data acquisition module after data signal to, and it is the digital collection module that logic analyzer or FPGA carry, if in the digital collection modules acquiring data carried by FPGA. Being stored in the RAM of FPGA if the data observation acquisition software carried by FPGA gets the useful data counted, statistical conversion imports to after becoming dat file and draws test result in test procedure, and the numerary signal rear end after conversion does not arrange digital collection hardware, or

Reading useful point data by this type of data gathering testing tool of logic analyzer, statistical conversion imports to after becoming dat file and draws test result in test procedure.

Wherein, the first signal source front end arranges a bandpass filter. Goodly, described first signal source is joined mutually with the source signal in second signal source.

Preferably, the maximum amplitude of the input signal entering analog to digital converter described in reduces 1dB than full amplitude.

In addition, after the data collected preserve with dat file layout, it carrying out frequency domain FFT process, the limited data counted are done frequency domain process by the one piece of data intercepting numerary signal, and comprising the treating processes of window function, it may also be useful to Hanning window makes the cycle match of window function and input signal.

Its constraint condition is:

For discrete digital signal, being the combination by discrete point one by one, also form signal frequency spectrum by N number of discrete point in frequency in time domain, its frequency is evenly distributed in [0,2 ��], thenShow that equivalence at discrete domain signal energy is:

$E=\underset{n=1}{\overset{N}{\Σ}}|f\left(n\right){|}^2=\underset{k=1}{\overset{N}{\Σ}}|F\left(k\right){|}^2*\frac{1}{N}$

Corresponding, a kind of testing method testing analog to digital converter salient features index, comprising:

Characteristic of making an uproar mutually meets the first signal source of preset requirement as its sampling clock source, one has the mimic input signal of second signal source as analog to digital converter that characteristic of making an uproar mutually meets preset requirement, and the input frequency of the first and second signal sources and amplitude are all adjustable;

The mimic input signal amplified through prime amplifier together converts numerary signal to by described analog to digital converter with the sampling clock input signal after clock circuit conversion;

This numerary signal and another road sampling clock input signal after clock circuit conversion are to logic analyzer; Reading useful point data by this type of data gathering testing tool of logic analyzer, statistical conversion imports to after becoming dat file and draws test result in test procedure.

Or the data observation acquisition software carried by FPGA got the useful data counted and be stored in the RAM of FPGA, statistical conversion imports to after becoming dat file and draws test result in test procedure, and the numerary signal rear end after conversion does not arrange digital collection hardware.

The signal source of the described input signal being supplied to receiving apparatus need to by a bandpass filter. Further, described first signal source is joined mutually with the source signal in second signal source.

After the data collected preserve with dat file layout, numerary signal is carried out frequency domain FFT process. The limited data counted are done frequency domain process by the one piece of data intercepting numerary signal.

Further, testing method also comprises the treating processes of window function, it may also be useful to Hanning window makes the cycle match of window function and input signal.

Further, continuous signal and/or discrete digital signal can be carried out energy spectrum analysis by described testing method.

Should be understood that method as described herein and system can realize in hardware in a variety of manners, software, firmware, dedicated processor or their combination. Especially, the application program that the part of at least the present invention comprises programmed instruction preferably realizes. By really being included in, one or more program storage device (includes but not limited to hard disk to these programmed instruction, magnetic floppy disc, RAM, ROM, CD, ROM etc.) inner, and can by any equipment or the machine that comprise appropriate configuration, such as a kind of universal digital computer with treater, internal memory and input/output interface performs. It should also be understood that the composition parts of some systems owing to describing in accompanying drawing and treatment step are preferably with software simulating, so, connection between system module (or logic flow process of method steps) may be different, and this depends on the programming mode of the present invention. According to guidance given here, those of ordinary skill in the related art can design these and the similar enforcement mode of the present invention.

The specific embodiment being only the present invention disclosed in above, but the present invention is not limited thereto, the changes that any person skilled in the art can think of, all should drop in protection scope of the present invention.

Claims (4)

1. test a test macro for analog to digital converter salient features index, for testing the performance index that simulating signal is carried out analog-to-digital analog to digital converter, it is characterised in that, comprising: sampling clock source, data acquisition module, wherein:

Sampling clock source: characteristic of making an uproar mutually meets the first signal source of preset requirement as its sampling clock source, one has the mimic input signal of second signal source as analog to digital converter that characteristic of making an uproar mutually meets preset requirement, and the input frequency of the first and second signal sources and amplitude are all adjustable;

Analog to digital converter: the mimic input signal for amplifying through prime amplifier together converts numerary signal to by described analog to digital converter with the sampling clock input signal after clock circuit conversion;

Simulating signal converts the data acquisition module after numerary signal to, its digital collection module carried for logic analyzer or FPGA, if the useful data counted are stored in the RAM of FPGA in the digital collection modules acquiring data carried by FPGA, statistical conversion imports to after becoming dat file and draws test result in test procedure, numerary signal rear end after conversion does not arrange digital collection hardware, or reading useful point data by logic analyzer, statistical conversion imports to after becoming dat file and draws test result in test procedure;

The maximum amplitude of the mimic input signal entering analog to digital converter reduces 1dB than full amplitude;

Its constraint condition is:

For discrete digital signal, being the combination by discrete point one by one, also form signal frequency spectrum by N number of discrete point in frequency in time domain, its frequency is evenly distributed in [0,2 ��], thenShow that equivalence at discrete domain signal energy is:

$E=\underset{n=1}{\overset{N}{\Σ}}|f\left(n\right){|}^2=\underset{k=1}{\overset{N}{\Σ}}|F\left(k\right){|}^2*\frac{1}{N}$

Wherein, N is that frequency domain sample is counted, and n is time variable, and k is frequency variable, and f (n) is signal voltage or electric current, the spectral density that F (k) is f (n);

Described salient features index comprises without parasitic dynamicrange (SFDR), signal to noise ratio (SNR), signal and noise and distortion ratio (SINAD), conversion figure place and conversion speed.

2. the test macro of test analog to digital converter salient features index as claimed in claim 1, it is characterised in that, the first signal source front end arranges a bandpass filter.

3. the test macro of test analog to digital converter salient features index as claimed in claim 1, it is characterised in that, described first signal source is joined mutually with the source signal in second signal source.

4. the test macro of test analog to digital converter salient features index as claimed in claim 1, it is characterized in that, after the data collected preserve with dat file layout, it is carried out frequency domain FFT process, the limited data counted are done frequency domain process by the one piece of data intercepting numerary signal, and comprising the treating processes of window function, it may also be useful to Hanning window makes the cycle match of window function and numerary signal.