CN102867845A - N type longitudinal high-voltage tolerance transverse double diffused metal oxide semiconductor transistor - Google Patents
N type longitudinal high-voltage tolerance transverse double diffused metal oxide semiconductor transistor Download PDFInfo
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- CN102867845A CN102867845A CN2012103661933A CN201210366193A CN102867845A CN 102867845 A CN102867845 A CN 102867845A CN 2012103661933 A CN2012103661933 A CN 2012103661933A CN 201210366193 A CN201210366193 A CN 201210366193A CN 102867845 A CN102867845 A CN 102867845A
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Abstract
The invention relates to an N type longitudinal high-voltage tolerance transverse double diffused metal oxide semiconductor transistor. The N type longitudinal high-voltage tolerance transverse double diffused metal oxide semiconductor transistor comprises a P type silicon substrate, wherein an N-drift region and a P type body region are arranged on the P type silicon substrate, the upper surface of the P type silicon substrate is covered by the N-drift region and the P type body region, an N type source region, a P type body contact region and a gate oxide layer are arranged above the P type body region, an N type buffer layer is arranged above the N-drift region, an N type drain region is arranged above the N type buffer layer, a polysilicon gate is arranged above the gate oxide layer, a field oxide layer is arranged above the N type source region, the P type body contact region, the polysilicon gate, the N-drift region and the N type drain region, a first metal leading wire penetrating through the field oxide layer is connected on the N type source region and the P type body contact region, the polysilicon gate is connected with a second metal leading wire penetrating through the field oxide layer, and the N type drain region is connected with a third metal leading wire penetrating through the field oxide layer. The N type longitudinal high-voltage tolerance transverse double diffused metal oxide semiconductor transistor is characterized in that a hyperconjugation structure is arranged on the P type silicon substrate, and the hyperconjugation structure is constituted by N type regions and P type regions, which are alternately distributed in the direction of connecting the drain region with the substrate.
Description
Technical field
The present invention relates to the power semiconductor technical field, in particular, is about improving vertically withstand voltage a kind of drain terminal with the lateral double-diffused metal-oxide-semiconductor transistor of vertical super-junction structure.
Background technology
Power semiconductor is the primary element that carries out energy control and conversion in the power electronic system, and the development of power electronic technology is that power semiconductor has been opened up widely application.Modern Power Electronic Devices and Related product take lateral double-diffused metal-oxide-semiconductor transistor with switching speed faster, wider safety operation area characteristics as representative play an important role in the 4C industry of representative at computer, communication, consumer electronics, automotive electronics.Nowadays, power device is just towards improving operating voltage, increase operating current, reducing conducting resistance and integrated future development.The invention of super knot is the technical milestone of power MOS transistor.
Power device is widely used in field of power electronics, and many application scenarios require it must bear higher voltage.And device withstand voltage by transversely withstand voltage and vertical on withstand voltage both jointly determine.Improving laterally, withstand voltage common employing RESURF(reduces surface field), floating empty field limiting ring, VLD(drift region varying doping) technology such as, at present can be with the horizontal withstand voltage very high level (more than the 1000V) of bringing up to, at this moment, the puncture of device many times occurs on the vertical structure, therefore, and the vertical withstand voltage key factor that determines device withstand voltage that becomes of power device.
Traditional raising vertically withstand voltage method is the epitaxy layer thickness that increases device, but thick epitaxial loayer certainly will increase the isolation difficulty on technique. the extension time is lengthened, increase cost, so in order to satisfy the needs of high and low pressure compatibility, become the trend of development in the horizontal technology of silica-based middle employing Ultra Thin Epitaxial.Therefore laterally withstand voltage when enough high, just be necessary the device vertical structure is optimized, thereby improve the vertically withstand voltage of device, and then improve the puncture voltage of whole power device.
Summary of the invention
The invention provides vertically high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor of a kind of N-type, the present invention can improve the vertically withstand voltage of device, thereby improves the puncture voltage of whole device.
The present invention adopts following technical scheme:
A kind of N-type is high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor vertically, comprise: P type silicon substrate, be provided with the N-drift region at P type silicon substrate, P type tagma and super-junction structure, super-junction structure is made of N-type district and the p type island region that connection drain region and substrate direction distribute alternately, and the upper surface of P type silicon substrate is the N-drift region, P type tagma and super-junction structure cover, above P type tagma, be provided with the N-type source region, P type body contact zone and gate oxide, above the N-drift region, be provided with the N-type resilient coating, above the N-type resilient coating, be provided with the N-type drain region, above gate oxide, be provided with polysilicon gate, in the N-type source region, P type body contact zone, polysilicon gate, the N-drift region, top, N-type drain region is provided with field oxide, in the N-type source region and P type body contact zone be connected to the first metal lead wire of break-through field oxide, polysilicon gate is connected to the second metal lead wire of break-through field oxide, and the N-type drain region is connected to the 3rd metal lead wire of break-through field oxide.
Compared with prior art, the present invention has following advantage:
1, the vertically high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor of the N-type with super-junction structure of the present invention has adopted new construction, namely adds the super-junction structure that N-type district and p type island region distribute alternately between N-type resilient coating 13 and P type substrate 1.With respect to traditional vertically lateral double-diffused metal-oxide-semiconductor transistor (Fig. 2) of super knot that do not have, the present invention has realized exhausting of three faces, be exhausting of N-type district 14 in the super-junction structure and the side between the p type island region 15, exhausting between p type island region 15 tops in the super-junction structure and drain terminal N-type resilient coating 13 bottoms, exhausting between 14 bottoms, N-type district in the super-junction structure and the P type substrate 1.The mechanism that exhausts like this makes between N-type district 14 in the super-junction structure and the p type island region 15 and exhausts fully, this is equivalent to add one deck dielectric layer between N-type resilient coating 13 and P type substrate 1, make N-type resilient coating 13 and P type substrate 1 form the diode structure of PIN, its electric field structure as shown in Figure 3, and Fig. 4 is the Electric Field Distribution of the traditional lateral double-diffused metal-oxide-semiconductor transistor that does not have super-junction structure, because the vertical withstand voltage of device carries out integration to Fig. 3 and electric field shown in Figure 4 just, from relatively can finding out of Fig. 3 and Fig. 4, the withstand voltage height that surpasses traditional lateral double-diffused metal-oxide-semiconductor transistor of tying with the withstand voltage ratio of new structure of the withstand voltage lateral double-diffused metal-oxide-semiconductor transistor of the vertical height of the N-type of super-junction structure, so employing has improved the withstand voltage of device with vertical new structure that surpasses the withstand voltage lateral double-diffused metal-oxide-semiconductor transistor of the vertical height of the N-type of tying.
2, the vertical high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor of the N-type with super-junction structure of the present invention, because the super-junction structure under the drain terminal exhausts fully, compare with traditional lateral double-diffused metal-oxide-semiconductor transistor that does not have vertical super-junction structure, have at identical withstand voltage lower epitaxial thickness less, or during the epitaxial loayer of same thickness, have higher withstand voltage.
3, the vertical high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor of the N-type with super-junction structure of the present invention fully based on the technique of the horizontal double-diffused transistor of existing preparation, has compatible preferably.
4, the vertical high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor thermal diffusivity of the N-type with super-junction structure of the present invention is good, and cost is low.
Description of drawings
Fig. 1 is that drain terminal of the present invention is with the vertical high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor of the N-type that vertically surpasses knot.
Fig. 2 is that traditional drain terminal of the present invention does not have the vertically N-type lateral double-diffused metal-oxide-semiconductor transistor of super knot.
Fig. 3 be drain terminal of the present invention with the N-type of vertical super knot vertically the super knot of high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor exhaust near principle and the super knot Electric Field Distribution.
Fig. 4 is that drain terminal band of the present invention does not have near the vertically Electric Field Distribution of P substrate N-drift region knot of the N-type lateral double-diffused metal-oxide-semiconductor transistor of super knot.
Fig. 5 is that drain terminal of the present invention does not have vertical breakdown voltage comparison diagram that surpasses the N-type lateral double-diffused metal-oxide-semiconductor transistor (original structure) of tying with vertically surpassing the vertical high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor (new structure) of the N-type of tying with drain terminal.
Embodiment
With reference to Fig. 1, a kind of N-type is high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor vertically, comprise: P type silicon substrate 1, be provided with N-drift region 2 at P type silicon substrate 1, P type tagma 3 and super-junction structure, super-junction structure is made of N-type district 14 and the p type island region 15 that connection drain region and substrate direction distribute alternately, and the upper surface of P type silicon substrate 1 is N-drift region 2, P type tagma 3 and super-junction structure cover, above P type tagma 3, be provided with N-type source region 4, P type body contact zone 5 and gate oxide 8, above N-drift region 2, be provided with N-type resilient coating 13, above N-type resilient coating 13, be provided with N-type drain region 12, above gate oxide 8, be provided with polysilicon gate 9, in N-type source region 4, P type body contact zone 5, polysilicon gate 9, N- drift region 2,12 tops, N-type drain region are provided with field oxide 6, in N-type source region 4 and P type body contact zone 5 be connected to the first metal lead wire 7 of break-through field oxide 6, polysilicon gate 9 is connected to the second metal lead wire 10 of break-through field oxide 6, and the N-type drain region is connected to the 3rd metal lead wire 11 of break-through field oxide 6.
Also adopt following technical measures further to improve performance of the present invention in this example:
The width in the Width N-type drain region of described super-junction structure is large.
Described super-junction structure can adopt repeatedly extension and ion implantation technology to form.
The present invention adopts following method to prepare:
1, selects a P type silicon substrate, it is cleaned, then carry out boron Implantation or phosphonium ion injection by the zone, carry out afterwards extension, carry out again Implantation, so carry out repeatedly Implantation and extension, can form super-junction structure through High temperature diffusion.
2, then Implantation forms N-drift region and N-type resilient coating, form P type tagma by Implantation and High temperature diffusion afterwards, then carry out the growth of an oxygen, and carry out the field and annotate, adjust channel threshold voltage, then carry out growth of gate oxide layer, the deposit etch polysilicon forms polysilicon gate and polysilicon field plate, the source is leaked to inject and is formed N-type source region, P type body contact zone and N-type drain region, then deposit field oxide.
3, etching field oxide, form the metal electrode fairlead in N-type source region, P type body contact zone, polysilicon gate and N-type drain region, deposited metal, etching sheet metal forms the N-type source region of N-type super-junction laterally dmost, the extraction electrode of P type body contact zone, the extraction electrode in the extraction electrode of polysilicon gate and N-type drain region.At last, carry out Passivation Treatment.
Claims (2)
1. the vertical high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor of a N-type, comprise: P type silicon substrate (1), be provided with N-drift region (2) and P type tagma (3) at P type silicon substrate (1), and the upper surface of P type silicon substrate (1) is that N-drift region (2) and P type tagma (3) cover, be provided with N-type source region (4) in top, P type tagma (3), P type body contact zone (5) and gate oxide (8), be provided with N-type resilient coating (13) in N-drift region (2) top, be provided with N-type drain region (12) in N-type resilient coating (13) top, be provided with polysilicon gate (9) in gate oxide (8) top, in N-type source region (4), P type body contact zone (5), polysilicon gate (9), N-drift region (2), top, N-type drain region (12) is provided with field oxide (6), be connected to first metal lead wire (7) of break-through field oxide (6) in N-type source region (4) and P type body contact zone (5), polysilicon gate (9) is connected to second metal lead wire (10) of break-through field oxide (6), the N-type drain region is connected to the 3rd metal lead wire (11) of break-through field oxide (6), it is characterized in that, be provided with super-junction structure at P type silicon substrate (1), super-junction structure is made of N-type district (14) and the p type island region (15) that connection drain region and substrate direction distribute alternately.
2. the vertical high withstand voltage lateral double-diffused metal-oxide-semiconductor transistor of N-type according to claim 1 is characterized in that, the super-junction structure width is larger than N-type drain region (12).
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070013008A1 (en) * | 2005-07-13 | 2007-01-18 | Shuming Xu | Power LDMOS transistor |
| CN101777581A (en) * | 2009-12-18 | 2010-07-14 | 东南大学 | P-type super-junction laterally double diffused metal oxide semiconductor |
| CN101916779A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | SOI super junction LDMOS structure capable of completely eliminating substrate-assisted depletion effect |
| CN101969074A (en) * | 2010-10-28 | 2011-02-09 | 电子科技大学 | High voltage lateral double diffused MOSFET element |
| CN102097480A (en) * | 2010-12-22 | 2011-06-15 | 东南大学 | N-type super-junction transverse double-diffusion metal oxide semiconductor tube |
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- 2012-09-27 CN CN2012103661933A patent/CN102867845A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070013008A1 (en) * | 2005-07-13 | 2007-01-18 | Shuming Xu | Power LDMOS transistor |
| CN101777581A (en) * | 2009-12-18 | 2010-07-14 | 东南大学 | P-type super-junction laterally double diffused metal oxide semiconductor |
| CN101916779A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | SOI super junction LDMOS structure capable of completely eliminating substrate-assisted depletion effect |
| CN101969074A (en) * | 2010-10-28 | 2011-02-09 | 电子科技大学 | High voltage lateral double diffused MOSFET element |
| CN102097480A (en) * | 2010-12-22 | 2011-06-15 | 东南大学 | N-type super-junction transverse double-diffusion metal oxide semiconductor tube |
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Application publication date: 20130109 |