CN102867803A - 用于晶粒安装的键合层厚度控制 - Google Patents
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- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 239000000853 adhesive Substances 0.000 claims abstract description 45
- 230000001070 adhesive effect Effects 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 239000013078 crystal Substances 0.000 claims description 78
- 238000006073 displacement reaction Methods 0.000 claims description 21
- 238000012545 processing Methods 0.000 claims description 20
- 238000005259 measurement Methods 0.000 claims description 15
- 238000009434 installation Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000001143 conditioned effect Effects 0.000 claims 4
- 239000011230 binding agent Substances 0.000 claims 2
- 238000012937 correction Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 230000008602 contraction Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- 208000034189 Sclerosis Diseases 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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Abstract
本发明公开了在半导体封装件的制造过程中,将半导体晶粒安装在位于处理平台的衬底上。滴涂器将粘合剂滴涂在衬底上;使用键合工具将半导体晶粒键合在已经滴涂于衬底的粘合剂上;其后使用测量设备测量位于处理平台上的半导体晶粒的下表面和衬底的上表面之间的键合层厚度。
Description
技术领域
本发明涉及半导体装配和封装领域,更具体地涉及使用粘合剂材料将半导体芯片或晶粒安装在衬底上。
背景技术
半导体晶粒安装工序是涉及半导体器件制造的步骤之一,它包括将半导体晶粒安装到引线框上特定的键合盘。这种安装通常通过首先滴涂粘合剂材料(如环氧树脂epoxy)至键合盘上,其次用特定的压力将晶粒按压进入该粘合剂材料中而得以完成。
其后,使用烘箱固化(oven cure)的热处理被执行,以在晶粒安装工艺之后将粘合剂固化和将晶粒固定在引线框上。固化后的晶粒然后通过在晶粒和引线框上的导电引线之间连接键合导线而被电性连接至键合盘。固化后的晶粒和键合导线使用模塑材料如热塑性树脂(thermoplastic resin)或陶瓷制品被最终灌封在保护壳中,以完成半导体器件的封装。
图1为晶粒101通过粘合剂102被安装在引线框103上的剖面示意图。晶粒101的底部和引线框103的键合盘表面之间的粘合剂102的厚度被称作为键合层厚度(BLT:Bond Line Thickness)。在图1中,BLT表示为高度t1,而晶粒101的厚度表示为t2。BLT(t1)能够通过用晶粒101上表面的高度减去引线框103的键合盘表面的高度和晶粒101的厚度(t2)而被计算出。
由于粘合剂102被用来将晶粒101安装在引线框103上,所以键合层不能太薄。在晶粒101被加工处理以致于粘合剂102硬化之后,在后续的封装过程中晶粒101仍然遭受到热膨胀和收缩。如果键合层太薄,由于在晶粒101和粘合剂102之间热膨胀和收缩可能以不同的速率出现,所以在晶粒101下面可能没有充足的粘合剂102来适应晶粒101和粘合剂102的这种膨胀或收缩。这样可能导致晶粒101中的断裂和裂纹。在某些严厉的情形下,晶粒101可能也会出现从粘合剂102上分离。
另一方面,键合层也不能太厚。如果出现太多的粘合剂102,那么粘合剂102可能渗透出来并污染晶粒101的表面。除其他外,当在晶粒101和引线框103之间形成电气导线连接时这可能导致不良的导线键合质量。而且,以上所述的问题不可避免地使得封装半导体器件的可靠性和性能变坏。所以,在晶粒安装工序中,键合层厚度必须被认真地控制在合适的范围之内。
键合层厚度的精确测量是必要的,以便于实现键合层厚度的精确控制。传统的键合层厚度的测量方法是横断面测量(cross-sectioning),其要求加工处理后的晶粒沿着剖面(line)被切开。然后,将横断切开的晶粒和粘合剂放置在显微镜下测量键合层厚度。横断面测量是一种破坏性的方法,切割过程使得该方法浪费时间。
由于在线反馈很难实现,所以存在很多方法被建议来通过设计特定的引线框控制键合层厚度。在专利出版号为:2009/0115039A1、发明名称为“半导体器件的高键合层厚度”的美国专利中,推荐来在引线框的键合盘端缘处产生边界特征(boundary features)。当粘合剂被滴涂在键合盘上时,粘合剂被限制在由边界特征所规定的键合盘区域之内并被堆积。这样保证了键合盘区域具有足够的粘合剂以生成用于键合层的特定厚度。而且,专利号为:5,214,307、发明名称为“具有改良的粘合剂的键合层控制的半导体器件的引线框”的美国专利描述了一种类似的方法。在键合盘区域之内的四个凸块(bumps)被使用,取代端缘处的边界特征。当晶粒被键合在引线框上时,晶粒会接触该凸块,特定的键合层厚度会被实现。在这种特定的引线框设计的帮助下,键合层被保证至少具有特定的厚度。这防止了当薄键合层太薄时所面临的问题。可是,在避免键合层太厚方面仍然没有控制。
发明内容
所以,本发明的目的在于寻求提供一种在线的键合层厚度的测量方法,以便于键合后的晶粒样本不需要从晶粒安装平台处移离,而测量键合层厚度。
本发明相关联的目的在于寻求在晶粒安装过程中,利用在线测量的结果,以控制键合层的厚度。
因此,本发明一方面提供一种用于制造半导体封装件的方法,该方法包括将半导体晶粒安装在位于处理平台的衬底上的步骤,该将半导体晶粒安装在衬底上的步骤还包含有以下步骤:使用滴涂器将粘合剂滴涂在衬底上;使用键合工具将半导体晶粒键合在已经滴涂于衬底的粘合剂上;其后使用测量设备测量位于处理平台上的半导体晶粒的下表面和衬底的上表面之间的键合层厚度。
本发明另一方面提供一种用于制造半导体封装件的晶粒安装装置,该晶粒安装装置包含有:滴涂器,用于将粘合剂滴涂在衬底上;键合工具,用于将半导体晶粒键合在已经滴涂于衬底的粘合剂上;以及测量设备,用于测量半导体晶粒的下表面和衬底的上表面之间的键合层厚度。
参阅后附的描述本发明实施例的附图,随后来详细描述本发明是很方便的。附图和相关的描述不能理解成是对本发明的限制,本发明的特点限定在权利要求书中。
附图说明
现在参考附图描述本发明所述装置和方法的示例,其中。
图1所示为通过粘合剂安装在引线框上的半导体晶粒的剖面示意图。
图2所示为表明包含有本发明较佳实施例所述的键合层厚度控制系统的晶粒安装装置的示意图。
图3所示为安装在键合盘上的晶粒的俯视图,其表示了分别位于晶粒和键合盘上的用于激光位移测量的示范点。
图4所示表明根据本发明较佳实施例所述激光位移测量如何可能被完成。以及。
图5所示为根据本发明较佳实施例所述的在线键合层厚度测量和控制工序的作业流程图。
具体实施方式
图2所示为表明包含有本发明较佳实施例所述的键合层厚度控制系统的晶粒安装装置201的示意图。晶粒安装装置201包括处理平台202、粘合剂滴涂器203、晶粒键合工具204和测量设备如激光位移传感器205。粘合剂滴涂器203、晶粒键合工具204和激光位移传感器205设置在处理平台202上的不同位置处。所以,在晶粒安装操作期间传送机构被操作来传送衬底相继至各个位置。
在晶粒安装操作期间,以引线框103形式存在的衬底沿着平台202被传送。首先,引线框103设置在粘合剂滴涂器203的位置,以将粘合剂102滴涂在引线框103上。接着,其上已经滴涂有粘合剂102的引线框103被前转至晶粒键合工具204的位置,以将半导体晶粒101键合在已经滴涂在引线框103的粘合剂102上。然后,键合后的引线框103被移动至后键合位置,在那里安装有激光位移传感器205。激光位移传感器205被操作来测量晶粒表面和引线框表面之间的高度差异,以便于测量晶粒101的下表面和引线框103的上表面之间的键合层厚度或BLT。
图3所示为安装在引线框103的键合盘上的晶粒101的俯视图,其表示了分别位于晶粒和键合盘上的用于激光位移测量的示范点301、302。其表明:激光位移传感器205从晶粒101表面的几个区域和引线框103的键合盘表面的多个点处获得计量结果。在这个示例中,在晶粒表面的四个角301获得计量结果,以及在键合盘处获得另外四个计量结果302。从而,对于整个键合后的晶粒101,平均BLT能够得以获得。BLT通过用晶粒101上表面的高度减去引线框103的上表面的高度和晶粒101的厚度而被计算出。任何的晶粒斜置也能够从晶粒101表面上的四个角301的高度差异中而得以被监测。在激光测量之后,键合后的引线框103从晶粒安装装置201处被移离,以进行烘箱固化。
所以,激光位移传感器205被采用在晶粒安装装置201的后键合位置。在晶粒101被键合之后,晶粒表面和引线框表面的位移结果被同时测量。然后,通过和激光位移传感器205、粘合剂滴涂器203和晶粒键合工具204电性连接的处理器如微处理器206,BLT能够被计算出。根据BLT测量的结果,处理参数得以被在线调整,以便于控制BLT在合适的范围以内。
图4所示表明根据本发明较佳实施例所述激光位移测量如何可能被完成。在当前发明中所使用的较佳的激光位移传感器205利用了激光三角法(laser triangulation)技术进行距离测量。激光位移传感器205由两个主要部件组成:激光发射器210和激光接收器211。该技术被称之为三角法,是因为激光发射器210、激光接收器211和被测量的物体101、103在测量期间被设置成形成三角形(如图4所述)。首先,从激光发射器210发出激光束至物体上。该激光束在物体表面被反射,激光接收器211其后捕获到反射后的激光束。由于激光位移传感器205和物体表面之间的距离偏差改变了激光反射角度,所以反射后的激光束会在激光接收器211的不同位置处被检测。根据在激光接收器211所检测的位置差异,晶粒101的表面和引线框103的表面之间的高度偏差能够得以被确定。
图5所示为根据本发明较佳实施例所述的、应用在晶粒安装装置201上的在线BLT测量和控制工序的作业流程图。使用晶粒键合工具将晶粒101键合401,晶粒表面和引线框表面之间的相对高度位移通过激光位移传感器205针对键合后晶粒101的测量得以完成402。其后,通过微处理器206,这个数据被进行处理,根据晶粒和引线框表面之间的位移减去晶粒厚度计算出BLT。根据该BLT,微处理器206确定键合层是否在预定的期望厚度变化范围以内404。如果这样,处理参数保持不再变化406。在线反馈控制通过微处理器206被建立。如果BLT太薄或者太厚306,那么在线修正调节将会被需要。然后,修正调节被反馈回相应的模块,如粘合剂滴涂器203、晶粒键合工具204,以及修正调节将会被执行307、308。
如图5所示,可能的修正调节包括:提高或降低粘合剂滴涂压力以控制滴涂的粘合剂的数量;提高或降低键合工具所在的键合水平面,以控制晶粒和粘合剂接触的垂直水平;提高或降低键合力以控制晶粒被按压进入粘合剂的深度;和/或 提高或降低键合时滞以控制晶粒被按压的时间。在触发修正调节以前,可能也迎合不同的触发环境。例如,系统可能被如此设置,以便于当BLT在期望范围之外时,或者当BLT仍然在期望范围之内但是在安全界限以外时,修正调节才被触发。
值得注意的是,根据本发明较佳实施例所述的晶粒安装装置201允许BLT被实时控制。为了实现BLT控制的目的,没有必要来移离键合后的晶粒以测量BLT或者设计特定的引线框。所以,所述的晶粒安装装置201有助于提高晶粒安装工序的产能和质量。
此处描述的本发明在所具体描述的内容基础上很容易产生变化、修正和/或补充,可以理解的是所有这些变化、修正和/或补充都包括在本发明的上述描述的精神和范围内。
Claims (20)
1.一种用于制造半导体封装件的方法,该方法包含将半导体晶粒安装在位于处理平台的衬底上的步骤,该将半导体晶粒安装在衬底上的步骤还包含有以下步骤:
使用滴涂器将粘合剂滴涂在衬底上;
使用键合工具将半导体晶粒键合在已经滴涂于衬底的粘合剂上;其后
使用测量设备测量位于处理平台上的半导体晶粒的下表面和衬底的上表面之间的键合层厚度。
2.如权利要求1所述的方法,其中,滴涂粘合剂、安装半导体晶粒和测量键合层厚度的步骤是在处理平台上的不同位置处进行的,该方法还包含有以下步骤:
移动该衬底相继至各个位置。
3.如权利要求1所述的方法,其中,该测量设备测量半导体晶粒的上表面的高度和衬底的上表面的高度。
4.如权利要求3所述的方法,该方法还包含有以下步骤:
通过用半导体晶粒上表面的高度减去衬底上表面的高度和半导体晶粒的厚度,计算出键合层厚度。
5.如权利要求3所述的方法,其中,半导体晶粒的上表面的高度和衬底的上表面的高度分别在多个点处获得计量结果。
6.如权利要求5所述的方法,该方法还包含有以下步骤:
检测该晶粒是否相对于衬底斜置。
7.如权利要求3所述的方法,其中,该测量设备包括激光位移传感器。
8.如权利要求7所述的方法,其中,激光位移传感器通过使用激光发射器和激光接收器由激光三角法获得距离测量而测量各个高度。
9.如权利要求1所述的方法,该方法还包含有以下步骤:
使用和测量设备相连的处理器调节用于将半导体晶粒安装至衬底上的处理参数,以将键合层厚度保持在期望变化范围以内。
10.如权利要求9所述的方法,其中,该被调节的处理参数为所滴涂的粘合剂数量和/或键合半导体晶粒的键合水平面。
11.如权利要求9所述的方法,其中,该被调节的处理参数为施加于半导体晶粒上的键合力和/或用于控制施加于半导体晶粒上的键合力持续时间的键合时滞。
12.一种将半导体晶粒安装在位于处理平台的衬底上的方法,该方法包含有以下步骤:
使用滴涂器将粘合剂滴涂在衬底上;
使用键合工具将半导体晶粒键合在已经滴涂于衬底的粘合剂上;其后
使用测量设备测量位于处理平台上的半导体晶粒的下表面和衬底的上表面之间的键合层厚度。
13.一种用于制造半导体封装件的晶粒安装装置,该晶粒安装装置包含有:
滴涂器,用于将粘合剂滴涂在衬底上;
键合工具,用于将半导体晶粒键合在已经滴涂于衬底的粘合剂上;以及
测量设备,用于测量半导体晶粒的下表面和衬底的上表面之间的键合层厚度。
14.如权利要求13所述的晶粒安装装置,其中,滴涂器、键合工具和测量设备设置在不同位置处,该晶粒安装装置还包含有:
传送机构,用于移动该衬底相继至该各个位置。
15.如权利要求13所述的晶粒安装装置,其中,该测量设备被操作来测量半导体晶粒的上表面的高度和衬底的上表面的高度。
16.如权利要求15所述的晶粒安装装置,其中,该键合层厚度通过用半导体晶粒上表面的高度减去衬底上表面的高度和半导体晶粒的厚度而被计算出。
17.如权利要求15所述的晶粒安装装置,其中,该测量设备包括激光位移传感器。
18.如权利要求13所述的晶粒安装装置,该晶粒安装装置还包含有:
处理器,其和该测量设备相连,该处理器被操作来调节用于将半导体晶粒安装至衬底上的处理参数,以将键合层厚度保持在期望变化范围以内。
19.如权利要求18所述的晶粒安装装置,其中,该被调节的处理参数为所滴涂的粘合剂数量和/或键合半导体晶粒的键合水平面。
20.如权利要求18所述的晶粒安装装置,其中,该被调节的处理参数为施加于半导体晶粒上的键合力和/或用于控制施加于半导体晶粒上的键合力持续时间的键合时滞。
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US20190202684A1 (en) * | 2017-12-29 | 2019-07-04 | Texas Instruments Incorporated | Protective bondline control structure |
CN114279349A (zh) * | 2021-12-31 | 2022-04-05 | 深圳电通纬创微电子股份有限公司 | 一种集成电路固晶胶水厚度测量方法 |
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JPH0611313A (ja) * | 1991-08-20 | 1994-01-21 | Hitachi Ltd | 厚み測定装置 |
KR20070013479A (ko) * | 2005-07-26 | 2007-01-31 | 삼성전자주식회사 | 본드 레벨 두께 측정부를 갖는 다이 본딩 장치 |
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US20050097736A1 (en) * | 2003-11-10 | 2005-05-12 | Texas Instruments Incorporated | Method and system for integrated circuit bonding |
US20120202300A1 (en) * | 2011-02-03 | 2012-08-09 | Texas Instruments Incorporated | Die bonder including automatic bond line thickness measurement |
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JPH0611313A (ja) * | 1991-08-20 | 1994-01-21 | Hitachi Ltd | 厚み測定装置 |
KR20070013479A (ko) * | 2005-07-26 | 2007-01-31 | 삼성전자주식회사 | 본드 레벨 두께 측정부를 갖는 다이 본딩 장치 |
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