CN102867785A - Nonvolatile memory device and manufacturing method thereof - Google Patents
Nonvolatile memory device and manufacturing method thereof Download PDFInfo
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- CN102867785A CN102867785A CN2011101946572A CN201110194657A CN102867785A CN 102867785 A CN102867785 A CN 102867785A CN 2011101946572 A CN2011101946572 A CN 2011101946572A CN 201110194657 A CN201110194657 A CN 201110194657A CN 102867785 A CN102867785 A CN 102867785A
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Abstract
The invention relates to a nonvolatile memory device and a manufacturing method thereof. The manufacturing method of the nonvolatile memory device comprises the following steps of: forming a conducting layer, wherein the conducting layer is provided with a first top; and transforming the first top into a second top, wherein the second top is provided with an arched surface. The nonvolatile memory device comprises a transistor structure and a first conducting layer, wherein the first conducting layer is formed in the transistor structure and is provided with a top surface; and the top surface is provided with a limited minimum fitting curvature radius.
Description
Technical field
The present invention relates to a kind of memory device and manufacture method thereof, particularly relate to a kind of non-volatility memory device and manufacture method thereof.
Background technology
In the prior art, a non-volatility memory device comprises a substrate, a floating grid, control grid and an insulator.This insulator is arranged between this substrate and this control grid, and this floating grid is imbedded in this insulator.This insulator comprises a tunnel oxide and a dielectric layers between polycrystal silicon.This tunnel oxide is arranged between this substrate and this floating grid, and this dielectric layers between polycrystal silicon is arranged between this floating grid and this control grid.
Employing is less than the manufacture process of 20 nanometer technology levels, and the floating grid memory cell with said structure is produced.This floating grid memory cell suffers the high inter polysilicon dielectric leakage current relevant with the field crowding effect at the edge of this floating grid.Serious inter polysilicon dielectric leakage current causes the durability of little planning window and difference, and reduces the data reservation power of fast flash memory bank.
This shows, above-mentioned existing non-volatility memory device and manufacture method thereof obviously still have inconvenience and defective, and demand urgently further being improved in product structure, manufacture method and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but have no for a long time applicable design is finished by development always, and common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious wish of relevant dealer solves.Therefore how to found a kind of new non-volatility memory device and manufacture method thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
Main purpose of the present invention is, overcome the defective that existing non-volatility memory device and manufacture method thereof exist, and provide a kind of new non-volatility memory device and manufacture method thereof, technical problem to be solved is to reduce the problem of inter polysilicon dielectric leakage current in the element, is very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.The manufacture method of a kind of non-volatility memory device that proposes according to the present invention, this manufacture method comprises the following steps: to form one first conductive structure, and wherein this first conductive structure has one first top; And, this first top is converted to one second top, this second top has a vaulted surface.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid non-volatility memory device, also comprise the following steps: to form a workpiece, wherein this workpiece comprises this first conductive structure and one first dielectric structure that is coupled in this first conductive structure, this first top has a subdivision, this subdivision has an edge pruning surface that exposes, and the step of described this workpiece of formation comprises the following steps: to provide a substrate; Above this substrate, form one first dielectric layer; Above this first dielectric layer, form one first conductive layer; Form one second dielectric layer at this first conductive layer; Pattern also removes the part of this second dielectric layer, this first conductive layer, this first dielectric layer and this substrate, form residual second dielectric layer, residual first conductive layer, residual the first dielectric layer and a groove structure, wherein this residual first conductive layer forms this first conductive structure, and this first conductive structure has a upper surface; Fill up this groove structure with a dielectric structure; Planarization also removes this dielectric structure of part to form one first dielectric structure, and wherein the upper surface of this first dielectric structure with a upper surface and this first dielectric structure is lower than the upper surface of this first conductive structure; Remove this residual second dielectric layer and exposed this first conductive structure to form this workpiece, wherein this top edge partly is removed to form the edge pruning surface of this exposure; Edge pruning surface applications one low-temperature oxidation process by to this exposure changes this subdivision into one first oxide layer, and so that this first top is converted to one the 3rd top, wherein this first oxide layer covers the 3rd top; Remove this first oxide layer, the 3rd top is converted to this second top; And cover this second top and form this non-volatility memory device.
The manufacture method of aforesaid non-volatility memory device, the wherein said step that removes this dielectric structure is carried out by one of them of a dilute hydrofluoric acid cleaning course and a dry etch process; The described step that removes this residual the second dielectric layer is carried out by using a hot phosphoric acid cleaning course; This first top has one first forward sight lid profile, this second top has one second forward sight lid profile, this the first forward sight lid profile and this second forward sight lid profile have respectively one first minimum match radius of curvature and one second minimum match radius of curvature, and this first minimum match radius of curvature is less than this second minimum match radius of curvature; This low-temperature oxidation process comprises from a low temperature plasma oxidizing process, a free-radical oxidation process and an ozone clean process selected one; And this low-temperature oxidation process comprises first-classly in oxidizing process, and this first top is in the edge pruning damaged surfaces of this exposure, and the described step that this subdivision is changed comprises that one repairs the step of this damage.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The manufacture method of a kind of non-volatility memory device that proposes according to the present invention, this manufacture method comprise the following steps: to form a transistor workpiece and are arranged on one first conductive layer in this transistor workpiece; And, form a top surface of this conductive layer, wherein to have be a limited minimum match radius of curvature to this top surface.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid non-volatility memory device, wherein this transistor workpiece comprises a dielectric module, this first conductive layer is arranged on below this dielectric module; This dielectric module comprises one first dielectric part and a dielectric structure, and wherein this first dielectric part has one first thickness, and is arranged on this first conductive layer and below this dielectric structure, and this dielectric structure is coupled in this first conductive layer; This dielectric structure comprises one second dielectric part, one the 3rd dielectric part and a dielectric layer; This first conductive layer has one second thickness, top edge part and a current-carrying part; This manufacture method also comprises the following steps: one of them by a chemical mechanical planarization process and an etch back process, and this dielectric structure planarization is removed this second dielectric part; Use greater than this first thickness one to remove thickness the 3rd dielectric part is removed, to stay this dielectric layer of this dielectric structure, wherein this dielectric layer comprises one the 4th dielectric part; This first dielectric part and this top edge are partly removed to stay this current-carrying part of this first conductive layer, wherein this current-carrying part comprises one first top, this first top has a subdivision, this subdivision has an edge pruning surface that exposes, and this top edge partly is removed to form the edge pruning surface of this exposure; Edge pruning surface applications one low-temperature oxidation process by to this exposure changes this subdivision into one first oxide layer, and so that this first top is converted to one second top, wherein this first oxide layer covers this second top; By removing this first oxide layer and the 4th dielectric part, this second top is converted to one the 3rd top, wherein the 3rd top has this top surface; And cover the 3rd top and form this non-volatility memory device.
The manufacture method of aforesaid non-volatility memory device, the step of this transistor workpiece of wherein said formation comprises the following steps: to provide a substrate, and wherein this substrate comprises a substrate portion; Form one first dielectric layer above this substrate, wherein this first dielectric layer comprises one first dielectric part; Form one second conductive layer above this first dielectric layer, wherein this second conductive layer comprises a current-carrying part and this first conductive layer; Form one second dielectric layer at this second conductive layer, wherein this second dielectric layer comprises one second dielectric part and one the 3rd dielectric part; By this second dielectric part, this current-carrying part, this first dielectric part and this substrate portion are removed, form a groove structure, with this first conductive layer of the 3rd dielectric part that stays this second dielectric layer and this second conductive layer; And fill up this groove structure with a dielectric structure and form this transistor workpiece.
The object of the invention to solve the technical problems realizes in addition more by the following technical solutions.According to a kind of non-volatility memory device that the present invention proposes, this non-volatility memory device comprises a transistor arrangement and one first conductive layer.This conductive layer is arranged in this transistor arrangement and has a top surface, and wherein to have be a limited minimum match radius of curvature to this top surface.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid non-volatility memory device, wherein said transistor arrangement comprises: a substrate has a top; One tunneling layer is arranged on this top of this substrate, and wherein this first conductive layer is arranged on this tunneling layer and has a bottom; One trench isolation layer is coupled in this bottom of this top, this tunneling layer and this first conductive layer of this substrate; One dielectric layer is arranged on this first conductive layer and this trench isolation layer; And one second conductive layer, be arranged on this dielectric layer, wherein: this bottom of this top of this substrate, this tunneling layer and this conductive layer becomes alignment; This first conductive layer is a poly floating grid layer, this second conductive layer is a control grid layer, and have more a first surface and the match radius of curvature in this first surface and distribute, wherein this first surface comprises this top surface and a side surface that is coupled in this top surface; This match radius of curvature is distributed in has this minimum match radius of curvature in this top surface; And this top surface extends to this side surface smoothly.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.According to a kind of non-volatility memory device that the present invention proposes, this non-volatility memory device comprises one first conductive layer, one second conductive layer and a dielectric layer.This dielectric layer is arranged between this first conductive layer and this second conductive layer, and has an interior vaulted surface.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid non-volatility memory device also comprises: a substrate has a top; One tunneling layer is arranged on this top of this substrate, and wherein this second conductive layer is arranged on this tunneling layer and has a bottom; And a trench isolation layer, be coupled in this bottom of this top, this tunneling layer and this conductive layer of this substrate, wherein: this first conductive layer is arranged on this dielectric layer, and this dielectric layer is arranged on this second conductive layer and this trench isolation layer; This dielectric layer has more an outer vaulted surface, an inner surface and an outer surface; Should have one first bottom and one first top that forms an interior round tip in interior vaulted surface; Should have one second bottom and one second top that forms an outer ring tip in outer vaulted surface; This first bottom extends to this inner surface and this first top smoothly; And this second bottom extends to this outer surface and this second top smoothly.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, non-volatility memory device of the present invention and manufacture method thereof have following advantages and beneficial effect at least: utilize manufacture method of the present invention to form one first conductive structure, wherein this first conductive structure has one first top; And, this first top is converted to one second top, this second top has a vaulted surface.The generation of leakage current can be reduced in above-mentioned vaulted surface, improves the data reserve force of element.
In sum, the invention relates to a kind of non-volatility memory device and manufacture method thereof.The manufacture method of this non-volatility memory device comprises the following steps: to form a conductive layer, and wherein this conductive layer has one first top; And, this first top is converted to one second top, this second top has a vaulted surface.This non-volatility memory device comprises: a transistor arrangement; And one first conductive layer, be arranged in this transistor arrangement and have a top surface, wherein to have be a limited minimum match radius of curvature to this top surface.The present invention has significant progress technically, and has obvious good effect, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above and other purpose of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and the cooperation accompanying drawing, be described in detail as follows.
Description of drawings
Fig. 1 is the flow chart that one embodiment of the invention provides the manufacture method of a non-volatility memory device.
Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E and Fig. 2 F are the schematic diagrames that one embodiment of the invention provides the manufacture method of this non-volatility memory device.
Fig. 2 G is the schematic diagram of the alternative configuration that configures in Fig. 2 F of one embodiment of the invention be provided for.
Fig. 3 is the schematic diagram that one embodiment of the invention provides a non-volatility memory device.
Fig. 4 is the schematic diagram that one embodiment of the invention provides another non-volatility memory device.
41,81: substrate
411,51: substrate portion
42,44,48,66,88: dielectric layer
43,49: conductive layer
431,53: current-carrying part
44S, 52S, 53S, 54S, 56S, 66S, 76S: top surface
45: groove structure
45S, 9S: surface
46: dielectric structure
46A: pad oxide layer
46B: filler oxide
46Q, 421,52,441,54,56Q, 66Q, 76: dielectric part
47: oxide layer
50: the transistor workpiece
501: the dielectric module
51D, 511D, 52D, 53D, 83D, 83P: side surface
531,631,731,831,8322,8822,8842,9322: the top
53E: top edge part
56: plat structure
60: workpiece
63,83: conductive layer
632: subdivision
633: the edge pruning surface of exposure
80: transistor arrangement
82: tunneling layer
83: conductive layer
832: vaulted surface
8321,835,8821,8841,9321: the bottom
86: trench isolation layer
882: outer vaulted surface
882D: outer surface
884: interior vaulted surface
884D: inner surface
89: the control grid layer
91,91A, 91B, 93,94: non-volatility memory device
932: top surface
DS1, DS2: specific range
H83: highly
L83: length
MR: mask regions
NR: non-mask regions
R1: the match radius of curvature distributes
RM: minimum match radius of curvature
TH1, TH2: the thickness that removes
TH53, TH54, TH88: thickness
W83: width
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, non-volatility memory device and its embodiment of manufacture method, structure, method, step, feature and effect thereof to foundation the present invention proposes are described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known to present in the following detailed description that cooperates with reference to graphic preferred embodiment.Explanation by embodiment, should be to reach technological means and the effect that predetermined purpose takes to obtain one more deeply and concrete understanding to the present invention, yet appended graphic only provide with reference to the usefulness of explanation, the present invention is limited.
See also shown in Figure 1ly, it provides the flow chart of the manufacture method 300 of a non-volatility memory device for one embodiment of the invention, and the figure that wherein is used for explaining orally in detail manufacture method 300 is presented at Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E and Fig. 2 F.The following narration that is used for Fig. 1 flow process relates to one that makes in a plurality of non-volatility memories unit.In step 302, a substrate 41 is provided, substrate 41 comprises a substrate portion 411 and a substrate portion 51.For example, substrate 41 is semiconductor substrates, such as a silicon substrate.In step 304, form a dielectric layer 42 at substrate 41, dielectric layer 42 comprises a dielectric part 421 and a dielectric part 52.For example, dielectric layer 42 is monoxide layers, such as silicon monoxide (SiO
2) layer.
In step 306, form a conductive layer 43 at dielectric layer 42, conductive layer 43 comprises a current-carrying part 431 and a current-carrying part 53.For example, conductive layer 43 is polysilicon layers.In step 308, form a dielectric layer 44 at conductive layer 43, dielectric layer 44 comprises a dielectric part 441 and a dielectric part 54.For example, dielectric layer 44 is hard mask layers.Dielectric layer 44 can be a silicon nitride (Si
3N
4) layer.
In step 310, pattern dielectric layer 44 is used from the shallow trench isolation that aligns and is formed a groove structure 45 from (self-aligned shallow trench isolation, SA-STI) process.Described groove structure 45 extends down into substrate 41 by dielectric layer 44, conductive layer 43 and dielectric layer 42.For example, dielectric layer 44 configurations have a mask regions and a non-mask regions thereon.This shallow trench isolation processes of certainly aliging forms groove structure 45 in this non-shade part.Groove structure 45 is used for a plurality of memory cells zone separately.By step 310, by dielectric part 441, current-carrying part 431, dielectric part 421 and substrate 411 parts are removed, form groove structure 45, to stay dielectric part 54, current-carrying part 53, dielectric part 52 and substrate portion 51.Dielectric part 54 and current-carrying part 53 (being a conductive layer) can be respectively as a mask layer and floating grid layers.Dielectric part 52 and substrate portion 51 can form respectively a tunneling layer and a substrate of this non-volatility memory device.
In step 312, form a dielectric structure 46 and fill up groove structure 45.For example, dielectric structure 46 is filler dielectric and comprises a selectable pad oxide layer 46A and a filler oxide 46B.For example, this filler oxide can form by adopting a high-density plasma (high density plasma, HDP) deposition or a glass to be coated with (spinon glass, SOG) technology.
In step 314, cmp (chemical-mechanical polishing, CMP) process or etch back process are used to planarization dielectric structure 46, and wherein dielectric structure 46 is processed until expose dielectric part 54.Utilize step 314, dielectric structure 46 has a plat structure 56 that is left.As a result, the top surface of dielectric part 54 can align with the top surface of plat structure 56.For example, plat structure 56 is filled up in groove structure 45, and is coupled in dielectric part 54, current-carrying part 53 (being a conductive layer) and dielectric part 52.
In step 316, use one greater than the thickness of dielectric part 54 to remove thickness, eat-back or process plat structure 56 by CMP the part of plat structure 56 is removed, so that plat structure 56 has a dielectric layer 66 that is left.For example, step 316 is carried out by a dilute hydrofluoric acid (dilute HF) cleaning course and a dry etch process one of them.For example, dielectric layer 66 has a top surface, and this top surface of dielectric layer 66 is lower than a top surface of current-carrying part 53 with a specific range.
In step 318, dielectric part 54 is removed, and a conductive layer 63 (being a current-carrying part) that can be simultaneously a top edge part 53E of current-carrying part 53 is removed that current-carrying part 53 is had and is left.Conductive layer 63 has a top 631, and wherein the top 631 of conductive layer 63 can have a subdivision 632, and subdivision 632 has an edge pruning surface 633 that exposes.For example, the top edge part 53E of current-carrying part 53 is removed to form the edge pruning surface 633 of exposure, and step 318 is by using a hot phosphoric acid (hot H
3P0
4) cleaning course carries out.
In step 320,, change subdivision 632 into an oxide layer 47 top 631 is converted to a top 731 to the edge pruning surface 633 that exposes by the low-temperature oxidation process of application, wherein oxide layer 47 covers top 731.For example, this low-temperature oxidation process comprises from a low temperature plasma oxidizing process, a free-radical oxidation process and an ozone clean process selected one.
In step 322, oxide layer 47 is removed, and use relevant one of thickness with current-carrying part 53 to remove thickness, the part of dielectric layer 66 is removed, top 731 be converted to a top 831 and make dielectric layer 66 and conductive layer 63 has respectively a conductive layer 83 and a dielectric part 76 that is left, wherein conductive layer 83 has top 831, and top 831 be expose and have a vaulted surface (domed surface) 832.For example, step 322 is carried out by using a dilute hydrofluoric acid (dilute HF) cleaning course.For example, dielectric part 76 has a top surface, and this top surface of dielectric part 76 is higher than a top surface of dielectric part 52 with a specific range.
In step 324, form a dielectric layer 48 at the top 831 of dielectric part 76 and conductive layer 83.For example, dielectric layer 48 is monoxide oxide nitride (ONO) layers that are deposited on the top 831 of dielectric part 76 and conductive layer 83.In step 326, form a conductive layer 49 at dielectric layer 48 and form this non-volatility memory device.For example, conductive layer 49 is polysilicon layers, and dielectric layer 48 is dielectric layers between polycrystal silicon.For example, dielectric layer 48 is control grid layers of this non-volatility memory device.
See also Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E and Fig. 2 F trival matters, it provides the schematic diagram of the manufacture method 300 of non-volatility memory device 91 for one embodiment of the invention.In Fig. 2 A-Fig. 2 F, non-volatility memory device 91 comprises two non-volatility memory device 91A and 91B, such as two floating grid non-volatility memory unit.Be convenient to understand for following narration, will be referred to each non-volatility memory device although discuss, with reference to one of them of non-volatility memory device 91A and 91B.For example, non-volatility memory device 91A is one of them of a NAND floating grid memory device and a NOR floating grid memory device.
In Fig. 2 A, a substrate 41 is provided, substrate 41 comprises two substrates part 411 and 51.For example, substrate 41 is semiconductor substrates, such as a silicon substrate.Formed a dielectric layer 42 on substrate 41, dielectric layer 42 comprises two dielectric part 421 and 52.For example, dielectric layer 42 is monoxide layers, such as silicon monoxide (SiO
2) layer.Formed a conductive layer 43 on dielectric layer 42, conductive layer 43 comprises two current-carrying parts 431 and 53.For example, conductive layer 43 is polysilicon layers.Formed a dielectric layer 44 on conductive layer 43, dielectric layer 44 comprises two dielectric part 441 and 54.For example, dielectric layer 44 is hard mask layers.Dielectric layer 44 can be a silicon nitride (Si
3N
4) layer.
In Fig. 2 B, by dielectric part 441, current-carrying part 431, dielectric part 421 and substrate portion 411 are removed, groove structure 45 has been formed, to stay dielectric part 54, current-carrying part 53, dielectric part 52 and substrate portion 51.Groove structure 45 extends down into substrate 41 from the top surface 44S of dielectric layer 44 by dielectric layer 44, conductive layer 43 and dielectric layer 42.For example, use from the shallow trench isolation that aligns from (self-aligned shallow trench isolation, SA-STI) process to form groove structure 45.For example, dielectric part 54 and current-carrying part 53 (being a conductive layer) can be respectively as a mask layer and floating grid layers.Dielectric part 52 and substrate portion 51 can form respectively a tunneling layer and the substrate of non-volatility memory device 91A.
In Fig. 2 B, form a dielectric structure 46 and filled up groove structure 45, and formed a transistor workpiece 50, dielectric structure 46 is as a filler dielectric.In one embodiment, dielectric structure 46 is monoxide structures, and comprises a pad oxide layer 46A and a filler oxide 46B; Pad oxide layer 46A is by on-site steam growth (in-situ steam growth, ISSG) or a heat treatment process (thermal process) and being deposited on the surperficial 45S of groove structure 45, then filler oxide 46B fills up groove structure 45 what pad oxide layer 46A formed.For example, filler oxide 46B can form by adopting a high-density plasma (high density plasma, HDP) deposition or a glass to be coated with (spin on glass, SOG) technology.For example, dielectric structure 46 comprises a dielectric part 46Q, a dielectric part 56Q and a dielectric layer 66.
For example, transistor workpiece 50 can comprise substrate portion 51, dielectric part 52 and a dielectric module 501, wherein dielectric part 52 is arranged on the substrate portion 51, current-carrying part 53 is arranged in the transistor workpiece 50, and dielectric module 501 is coupled in substrate portion 51, dielectric part 52 and current-carrying part 53.Dielectric module 501 comprises dielectric part 54 and dielectric structure 46, wherein dielectric part 54 is arranged on the current-carrying part 53 (being a conductive layer) and below dielectric structure 46, and dielectric structure 46 is coupled in dielectric part 54, current-carrying part 53 and dielectric part 52.Current-carrying part 53 comprises a top edge part 53E and a conductive layer 63 (being a current-carrying part), and be arranged on the dielectric part 52 and dielectric module 501 below.For example, dielectric part 54, current-carrying part 53 and dielectric part 52 are centered on by dielectric structure 46.
In Fig. 2 C, cmp (CMP) process or etch back process have been used to planarization dielectric structure 46, and are stopped by the top surface 54S of dielectric part 54.Therefore, the dielectric part 46Q of dielectric structure 46 (being presented among Fig. 2 B) can be removed to expose dielectric part 54, and a plat structure 56 that dielectric structure 46 is had be left, wherein current-carrying part 53 has a top surface 53S and a thickness T H53.Plat structure 56 comprises dielectric part 56Q and dielectric layer 66, and dielectric part 56Q has one and removes thickness T H1, and the top surface of dielectric part 54 can align with the top surface of plat structure 56.
In Fig. 2 D, use the thickness T H1 that removes greater than the thickness T H54 of dielectric part 54, eat-back or processed plat structure 56 by CMP the dielectric part 56Q of plat structure 56 has been removed, and the dielectric layer 66 that plat structure 56 is had be left.For example, the part 56Q of plat structure 56 removes by one of them of a dilute hydrofluoric acid (dilute HF) cleaning course and a dry etch process.For example, dielectric layer 66 has a top surface 66S, and top surface 66S is lower than the top surface 53S of current-carrying part 53 with a specific range DS1.Dielectric layer 66 comprises two dielectric part 66Q and 76, and wherein dielectric part 66Q has one and removes thickness T H2.
In Fig. 2 D, dielectric part 54 is removed, and can simultaneously the top edge part 53E (being presented among Fig. 2 B) of current-carrying part 53 be removed to make the conductive layer 63 (being a current-carrying part) of current-carrying part 53 to stay and form a workpiece 60.Conductive layer 63 comprises a top 631, and wherein the top 631 of conductive layer 63 can have a subdivision 632, and subdivision 632 has an edge pruning surface 633 that exposes.For example, top edge part 53E is removed to form the edge pruning surface 633 of exposure, and hot phosphoric acid (hot H3PO4) cleaning course is to make to remove dielectric part 54 and top edge part 53E.
For example, workpiece 60 can comprise substrate portion 51, dielectric part 52, conductive layer 63 and dielectric layer 66.Dielectric layer 66 comprises two dielectric part 66Q and 76, is arranged on the substrate portion 51, and is coupled in dielectric part 52 and conductive layer 63.For example, dielectric part 52 and conductive layer 63 are centered on by dielectric layer 66.
In Fig. 2 E,, change subdivision 632 into an oxide layer 47 top 631 is converted to a top 731 to the edge pruning surface 633 that exposes by the low-temperature oxidation process of application, wherein oxide layer 47 covers top 731.For example, this low-temperature oxidation process comprises from a low temperature plasma oxidizing process, a free-radical oxidation process and an ozone clean process selected one.
For example, during this low temperature plasma oxidizing process, the temperature of conductive layer 63 is in the scope between 600 ℃ and 700 ℃; During this free-radical oxidation process, the temperature of conductive layer 63 is in the scope between 600 ℃ and 700 ℃; During this ozone clean process, the temperature of conductive layer 63 is in the scope between 400 ℃ and 500 ℃.For example, this low-temperature oxidation process comprises first-class in oxidizing process, and the top 631 of conductive layer 63 is damaged on the edge pruning surface 633 that exposes, and this damage on the edge pruning surface 633 that exposes is repaired during this low temperature plasma oxidizing process.
In Fig. 2 F, oxide layer 47 is removed, and use relevant one of thickness T H53 (being presented among Fig. 2 C) with current-carrying part 53 to remove thickness T H2, the dielectric part 66Q (being presented among Fig. 2 E) of dielectric layer 66 is removed, top 731 be converted to a top 831 and make conductive layer 63 and dielectric layer 66 has respectively a conductive layer 83 and a dielectric part 76 that is left, wherein conduct electricity and 83 have top 831, and top 831 be expose and have one vaulted surperficial 832.For example, a dilute hydrofluoric acid (dilute HF) cleaning course is the dielectric part 66Q that makes to remove oxide layer 47 and dielectric layer 66.For example, dielectric part 76 has a top surface 76S, and top surface 76S is higher than a top surface 52S of dielectric part 52 with a specific range DS2, and dielectric part 76 forms the trench isolation layer of non-volatility memory device 91A.
For example, the top 631 of conductive layer 63 has one first forward sight lid profile (front-view cap profile), the top 831 of conductive layer 83 has one second forward sight lid profile, this the first forward sight lid profile and this second forward sight lid profile have respectively one first minimum match radius of curvature (minimum fitted curvature radius) and one second minimum match radius of curvature, and this first minimum match radius of curvature is less than this second minimum match radius of curvature.For example, vaulted surperficial 832 have a bottom 8321 and a top 8322 that is coupled in bottom 8321, and round tip (a perhaps dome) are formed on top 8322.Conductive layer 83 has more a side surface 83D, and bottom 8321 extends to side surface 83D and top 8322 smoothly.For example, conductive layer 83 has length L 83, width W 83 (in the direction perpendicular to paper) and height H 83, wherein height H 83 is greater than length L 83, and/or height H 83 is greater than width W 83, and perhaps height H 83 is the lateral width greater than conductive layer 83.
In Fig. 2 F, on the top 831 of dielectric part 76 and conductive layer 83, formed a dielectric layer 48.For example, dielectric layer 48 is monoxide oxide nitride (ONO) layers that are deposited on dielectric part 76 and the top 831.
In Fig. 2 F, on dielectric layer 48, formed a conductive layer 49 and formed non-volatility memory device 91A.For example, conductive layer 49 is polysilicon layers, and dielectric layer 48 is dielectric layers between polycrystal silicon.For example, conductive layer 83 and conductive layer 49 form respectively a floating grid layer and the control grid layer of non-volatility memory device 91A.
See also shown in Fig. 2 G the schematic diagram of the alternative configuration that it configures in Fig. 2 F for one embodiment of the invention be provided for.At Fig. 2 F) with Fig. 2 G in have a same-sign element have similar function.Shown in Fig. 2 G, the top 831 of conductive layer 83 has a top surface 932, and wherein to have be a limited minimum match radius of curvature (minimum fitted curvature radius) RM to top surface 932.For example, conductive layer 83 has more a surperficial 9S and the match radius of curvature distribution R1 in surperficial 9S, and wherein surperficial 9S comprises top surface 932 and a side surface 83D who is coupled in top surface 932.Match radius of curvature distribution R1 has minimum match radius of curvature R M in top surface 932.For example, top surface 932 and side surface 83D have an inverted U-shaped cross section.
For example, top surface 932 is vaulted surfaces and extends to smoothly side surface 83D.Top surface 932 is by a method manufacturing, and the method is same as the method for making top surface 832.For example, top surface 932 has a bottom 9321 and is coupled in a top 9322 of bottom 9321, and a round tip (a perhaps dome) can be formed on top 9322.Bottom 9321 extends to side surface 83D and top 9322 smoothly.
For example, when continuing to dwindle NAND memory cell big or small, since on the top edge of floating grid layer than small curvature radius, thinner dielectric layers between polycrystal silicon and less coupling efficiency, planning (programming) operating period by dielectric layers between polycrystal silicon, higher electric field is induced in this top edge of this floating grid layer.In order to overcome this problem, the floating grid layer (such as conductive layer 83) with round tip is provided to for NAND fast-flash memory body unit, and wherein this round tip has large radius of curvature.For example, provide this round tip of low-temperature oxidation process modulation than the low heat budget process, and for certainly align shallow trench isolation from the not impact of unit doping profile.
In one embodiment, provide the manufacture method of a kind of non-volatility memory device 91A according to Fig. 2 A-Fig. 2 G, this manufacture method comprises the following steps: to form a conductive layer 63, and wherein conductive layer 63 has a top 631; And, top 631 is converted to a top 831, top 831 has one vaulted surperficial 832.For example, this manufacture method more comprises the step that forms a workpiece 60, and wherein workpiece 60 can comprise substrate portion 51, dielectric part 52, conductive layer 63 and dielectric layer 66.Dielectric part 52 is arranged on the substrate portion 51, and conductive layer 63 is arranged on the dielectric part 52, and dielectric layer 66 is arranged on the substrate portion 51 and is coupled in dielectric part 52 and conductive layer 63.
In one embodiment, according to Fig. 2 A)-Fig. 2 G provides the manufacture method of a kind of non-volatility memory device 91A, and this manufacture method comprises the following steps: to form a transistor workpiece 50 and is arranged on a conductive layer (such as current-carrying part 53) in the transistor workpiece 50; And, form a top surface 932 of this conductive layer, wherein to have be a limited minimum match radius of curvature R M to top surface 932.
For example, top surface 932 has more a match radius of curvature distribution R1 and a top 9322 therein, and formed by conversioning transistor workpiece 50 and conductive layer (such as current-carrying part 53), wherein match radius of curvature distribution R1 has minimum match radius of curvature R M in top 9322.For example, top surface 932 is formed by a part of of a part that removes transistor workpiece 50 and this conductive layer, wherein this part of transistor workpiece 50 comprises dielectric part 46Q, 54,56Q and 66Q, and this part of this conductive layer comprises top edge part 53E and subdivision 632.For example, top surface 932 can be vaulted surperficial 832.
See also shown in Figure 3ly, it provides the schematic diagram of a non-volatility memory device 93 for one embodiment of the invention.As shown in the figure, non-volatility memory device 93 comprises a transistor arrangement 80 and a conductive layer 83.Conductive layer 83 is arranged in the transistor arrangement 80 and has one vaulted surperficial 832.For example, transistor arrangement 80 comprises a substrate 81, a tunneling layer 82, a trench isolation layer 86, control grid layer 89 and a dielectric layer 88.For example, conductive layer 83 is as a floating grid layer.
For example, the bottom 835 of the top 811 of substrate 81, tunneling layer 82 and conductive layer 83 becomes alignment.Conductive layer 83 can be a poly floating grid layer.For example, vaulted surperficial 832 have a bottom 8321 and a top 8322 that is coupled in bottom 8321, and a round tip or domes are formed on top 8322.Conductive layer 83 has more a side surface 83D, and bottom 8321 extends to side surface 83D and top 8322 smoothly.For example, conductive layer 83 has length L 83, width W 83 (in the direction perpendicular to paper) and height H 83, wherein height H 83 is greater than length L 83, and/or height H 83 is greater than width W 83, and perhaps height H 83 is the lateral width greater than conductive layer 83.For example, vaulted surperficial 832 are coupled in side surface 83D, and vaulted surperficial 832 and side surface 83D have an inverted U-shaped cross section.
In one embodiment, non-volatility memory device 93 comprises control grid layer 89, a conductive layer 83 and a dielectric layer 88.Dielectric layer 88 is arranged between control grid layer 89 and the conductive layer 83, and have one interior vaulted surperficial 884, vaulted surperficial 884 consistent with vaulted surperficial 832 in wherein.For example, dielectric layer 88 has more outer vaulted surperficial 882, one inner surface 884D and an outer surface 882D, and wherein inner surface 884D is consistent with side surface 83D.For example, dielectric layer 88 has a thickness T H88, and outer vaulted surperficial 882 is to depart from from interior vaulted surperficial 884 by thickness T H88.
For example, interior vaulted surperficial 884 have a bottom 8841 and a top 8842 that is coupled in bottom 8841, and outer vaulted surperficial 882 have a bottom 8821 and a top 8822 that is coupled in bottom 8821.One interior round tip is formed on top 8842, and outer ring tip is formed on top 8822.Bottom 8841 extends to inner surface 884D and top 8842 smoothly, and bottom 8821 extends to outer surface 882D and top 8822 smoothly.For example, outer vaulted surperficial 882 are coupled in outer surface 882D, and outer vaulted surperficial 882 and outer surface 882D have an inverted U-shaped cross section.
See also shown in Figure 4ly, it provides the schematic diagram of another non-volatility memory device 94 for one embodiment of the invention.The element that has same-sign in Fig. 3 and Fig. 4 has similar function.As shown in Figure 4, non-volatility memory device 94 comprises a transistor arrangement 80 and a conductive layer 83.Conductive layer 83 is arranged in the transistor arrangement 80 and has a top surface 932, and wherein to have be a limited minimum match radius of curvature R M to top surface 932.For example, transistor arrangement 80 comprises a substrate 81, a tunneling layer 82, a trench isolation layer 86, control grid layer 89 and a dielectric layer 88.
For example, conductive layer 83 has more a surperficial 9S and the match radius of curvature distribution R1 in surperficial 9S, and wherein surperficial 9S comprises top surface 932 and a side surface 83D who is coupled in top surface 932.Match radius of curvature distribution R1 has minimum match radius of curvature R M in top surface 932.For example, top surface 932 and side surface 83D have an inverted U-shaped cross section.For example, top surface 932 is vaulted surfaces and extends to smoothly side surface 83D.For example, top surface 932 has a bottom 9321 and is coupled in a top 9322 of bottom 9321, and a round tip (a perhaps dome) can be formed on top 9322.Bottom 9321 extends to side surface 83D and top 9322 smoothly.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet be not to limit the present invention, any those skilled in the art, within not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, any simple modification that foundation technical spirit of the present invention is done above embodiment, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (10)
1. the manufacture method of a non-volatility memory device is characterized in that it may further comprise the steps:
Form one first conductive structure, wherein this first conductive structure has one first top; And
This first top is converted to one second top, and this second top has a vaulted surface.
2. the manufacture method of non-volatility memory device according to claim 1 is characterized in that it also comprises the following steps:
Form a workpiece, wherein this workpiece comprises this first conductive structure and one first dielectric structure that is coupled in this first conductive structure, this first top has a subdivision, and this subdivision has an edge pruning surface that exposes, and the step of described this workpiece of formation comprises the following steps:
One substrate is provided;
Above this substrate, form one first dielectric layer;
Above this first dielectric layer, form one first conductive layer;
Form one second dielectric layer at this first conductive layer;
Pattern also removes the part of this second dielectric layer, this first conductive layer, this first dielectric layer and this substrate, form residual second dielectric layer, residual first conductive layer, residual the first dielectric layer and a groove structure, wherein this residual first conductive layer forms this first conductive structure, and this first conductive structure has a upper surface;
Fill up this groove structure with a dielectric structure;
Planarization also removes this dielectric structure of part to form one first dielectric structure, and wherein the upper surface of this first dielectric structure with a upper surface and this first dielectric structure is lower than the upper surface of this first conductive structure;
Remove this residual second dielectric layer and exposed this first conductive structure to form this workpiece, wherein this top edge partly is removed to form the edge pruning surface of this exposure;
Edge pruning surface applications one low-temperature oxidation process by to this exposure changes this subdivision into one first oxide layer, and so that this first top is converted to one the 3rd top, wherein this first oxide layer covers the 3rd top;
Remove this first oxide layer, the 3rd top is converted to this second top; And
Cover this second top and form this non-volatility memory device.
3. the manufacture method of non-volatility memory device according to claim 2 is characterized in that wherein:
The described step that removes this dielectric structure is carried out by one of them of a dilute hydrofluoric acid cleaning course and a dry etch process;
The described step that removes this residual the second dielectric layer is carried out by using a hot phosphoric acid cleaning course;
This first top has one first forward sight lid profile, this second top has one second forward sight lid profile, this the first forward sight lid profile and this second forward sight lid profile have respectively one first minimum match radius of curvature and one second minimum match radius of curvature, and this first minimum match radius of curvature is less than this second minimum match radius of curvature;
This low-temperature oxidation process comprises from a low temperature plasma oxidizing process, a free-radical oxidation process and an ozone clean process selected one; And
This low-temperature oxidation process comprises first-class in oxidizing process, and this first top is in the edge pruning damaged surfaces of this exposure, and the described step that this subdivision is changed comprises that one repairs the step of this damage.
4. the manufacture method of a non-volatility memory device is characterized in that it may further comprise the steps:
Form a transistor workpiece and one first conductive layer that is arranged in this transistor workpiece; And
Form a top surface of this first conductive layer, wherein to have be a limited minimum match radius of curvature to this top surface.
5. the manufacture method of non-volatility memory device according to claim 4 is characterized in that wherein:
This transistor workpiece comprises a dielectric module, and this first conductive layer is arranged on below this dielectric module;
This dielectric module comprises one first dielectric part and a dielectric structure, and wherein this first dielectric part has one first thickness, and is arranged on this first conductive layer and below this dielectric structure, and this dielectric structure is coupled in this first conductive layer;
This dielectric structure comprises one second dielectric part, one the 3rd dielectric part and a dielectric layer;
This first conductive layer has one second thickness, top edge part and a current-carrying part;
This manufacture method also comprises the following steps:
By a chemical mechanical planarization process and an etch back process one of them, this dielectric structure planarization is removed this second dielectric part;
Use greater than this first thickness one to remove thickness the 3rd dielectric part is removed, to stay this dielectric layer of this dielectric structure, wherein this dielectric layer comprises one the 4th dielectric part;
This first dielectric part and this top edge are partly removed to stay this current-carrying part of this first conductive layer, wherein this current-carrying part comprises one first top, this first top has a subdivision, this subdivision has an edge pruning surface that exposes, and this top edge partly is removed to form the edge pruning surface of this exposure;
Edge pruning surface applications one low-temperature oxidation process by to this exposure changes this subdivision into one first oxide layer, and so that this first top is converted to one second top, wherein this first oxide layer covers this second top;
By removing this first oxide layer and the 4th dielectric part, this second top is converted to one the 3rd top, wherein the 3rd top has this top surface; And
Cover the 3rd top and form this non-volatility memory device.
6. the manufacture method of non-volatility memory device according to claim 4 is characterized in that the step of this transistor workpiece of wherein said formation comprises the following steps:
One substrate is provided, and wherein this substrate comprises a substrate portion;
Form one first dielectric layer above this substrate, wherein this first dielectric layer comprises one first dielectric part;
Form one second conductive layer above this first dielectric layer, wherein this second conductive layer comprises a current-carrying part and this first conductive layer;
Form one second dielectric layer at this second conductive layer, wherein this second dielectric layer comprises one second dielectric part and one the 3rd dielectric part;
By this second dielectric part, this current-carrying part, this first dielectric part and this substrate portion are removed, form a groove structure, with this first conductive layer of the 3rd dielectric part that stays this second dielectric layer and this second conductive layer; And
Fill up this groove structure with a dielectric structure and form this transistor workpiece.
7. non-volatility memory device is characterized in that it comprises:
One transistor arrangement; And
One first conductive layer is arranged in this transistor arrangement and has a top surface, and wherein to have be a limited minimum match radius of curvature to this top surface.
8. non-volatility memory device according to claim 7 is characterized in that wherein said transistor arrangement comprises:
One substrate has a top;
One tunneling layer is arranged on this top of this substrate, and wherein this first conductive layer is arranged on this tunneling layer and has a bottom;
One trench isolation layer is coupled in this bottom of this top, this tunneling layer and this first conductive layer of this substrate;
One dielectric layer is arranged on this first conductive layer and this trench isolation layer; And
One second conductive layer is arranged on this dielectric layer, wherein:
This bottom of this top of this substrate, this tunneling layer and this conductive layer becomes alignment;
This first conductive layer is a poly floating grid layer, this second conductive layer is a control grid layer, and have more a first surface and the match radius of curvature in this first surface and distribute, wherein this first surface comprises this top surface and a side surface that is coupled in this top surface;
This match radius of curvature is distributed in has this minimum match radius of curvature in this top surface; And
This top surface extends to this side surface smoothly.
9. non-volatility memory device is characterized in that it comprises:
One first conductive layer;
One second conductive layer; And
One dielectric layer is arranged between this first conductive layer and this second conductive layer, and has an interior vaulted surface.
10. non-volatility memory device according to claim 9 is characterized in that it also comprises:
One substrate has a top;
One tunneling layer is arranged on this top of this substrate, and wherein this second conductive layer is arranged on this tunneling layer and has a bottom; And
One trench isolation layer is coupled in this bottom of this top, this tunneling layer and this conductive layer of this substrate, wherein:
This first conductive layer is arranged on this dielectric layer, and this dielectric layer is arranged on this second conductive layer and this trench isolation layer;
This dielectric layer has more an outer vaulted surface, an inner surface and an outer surface;
Should have one first bottom and one first top that forms an interior round tip in interior vaulted surface;
Should have one second bottom and one second top that forms an outer ring tip in outer vaulted surface;
This first bottom extends to this inner surface and this first top smoothly; And
This second bottom extends to this outer surface and this second top smoothly.
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| US20080277714A1 (en) * | 2007-05-09 | 2008-11-13 | Hynix Semiconductor Inc. | Nonvolatile memory device and method for fabricating the same |
| US20100006915A1 (en) * | 2008-07-09 | 2010-01-14 | Dana Lee | Dielectric layer above floating gate for reducing leakage current |
| US20100009503A1 (en) * | 2008-07-09 | 2010-01-14 | Kai James K | Method of forming dielectric layer above floating gate for reducing leakage current |
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| US20070126046A1 (en) * | 2005-12-02 | 2007-06-07 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and method of fabricating the same |
| US20080277714A1 (en) * | 2007-05-09 | 2008-11-13 | Hynix Semiconductor Inc. | Nonvolatile memory device and method for fabricating the same |
| US20100006915A1 (en) * | 2008-07-09 | 2010-01-14 | Dana Lee | Dielectric layer above floating gate for reducing leakage current |
| US20100009503A1 (en) * | 2008-07-09 | 2010-01-14 | Kai James K | Method of forming dielectric layer above floating gate for reducing leakage current |
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