CN102867785B - Nonvolatile memory device and manufacturing method thereof - Google Patents
Nonvolatile memory device and manufacturing method thereof Download PDFInfo
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- CN102867785B CN102867785B CN201110194657.2A CN201110194657A CN102867785B CN 102867785 B CN102867785 B CN 102867785B CN 201110194657 A CN201110194657 A CN 201110194657A CN 102867785 B CN102867785 B CN 102867785B
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Abstract
The invention relates to a nonvolatile memory device and a manufacturing method thereof. The manufacturing method of the nonvolatile memory device comprises the following steps of: forming a conducting layer, wherein the conducting layer is provided with a first top; and transforming the first top into a second top, wherein the second top is provided with an arched surface. The nonvolatile memory device comprises a transistor structure and a first conducting layer, wherein the first conducting layer is formed in the transistor structure and is provided with a top surface; and the top surface is provided with a limited minimum fitting curvature radius.
Description
Technical field
The present invention relates to a kind of memory device and manufacture method thereof, particularly relate to a kind of nonvolatile memory device and manufacture method thereof.
Background technology
In the prior art, a nonvolatile memory device comprises a substrate, a floating grid, a control gate and an insulator.This insulator is arranged between this substrate and this control gate, and this floating grid is imbedded in this insulator.This insulator comprises a tunnel oxide and a dielectric layers between polycrystal silicon.This tunnel oxide is arranged between this substrate and this floating grid, and this dielectric layers between polycrystal silicon is arranged between this floating grid and this control gate.
Adopt the manufacture process being less than 20 nanotechnology level, the floating grid memory cell with said structure is produced.This floating grid memory cell suffers the high inter polysilicon dielectric leakage current relevant to field crowding effect on the edge of this floating grid.Serious inter polysilicon dielectric leakage current causes little planning window and poor durability, and reduces the data retention of fast flash memory bank.
As can be seen here, above-mentioned existing nonvolatile memory device and manufacture method thereof, in product structure, manufacture method and use, obviously still have inconvenience and defect, and are urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development always, and common product and method do not have appropriate structure and method to solve the problem, this is obviously the anxious problem for solving of relevant dealer.Therefore how to found a kind of new nonvolatile memory device and manufacture method thereof, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
Main purpose of the present invention is, overcome the defect of existing nonvolatile memory device and manufacture method existence thereof, and a kind of new nonvolatile memory device and manufacture method thereof are provided, technical problem to be solved to reduce the problem of inter polysilicon dielectric leakage current in element, is very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.The manufacture method of a kind of nonvolatile memory device proposed according to the present invention, this manufacture method comprises the following steps: formation one first conductive structure, and wherein this first conductive structure has one first top; And this first top is converted to one second top, and this second top has a domed surface.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid nonvolatile memory device, also comprise the following steps: formation one workpiece, wherein this workpiece comprises this first conductive structure and is coupled in one first dielectric structure of this first conductive structure, this first top has a subdivision, this subdivision has the edge pruning surface of an exposure, and the step of described this workpiece of formation comprises the following steps: to provide a substrate; Square one-tenth one first dielectric layer on the substrate; One first conductive layer is formed at this first dielectric layer; This first conductive layer forms one second dielectric layer; Patterning and remove the part of this second dielectric layer, this first conductive layer, this first dielectric layer and this substrate, form residual second dielectric layer, residual first conductive layer, residual first dielectric layer and a groove structure, wherein this residual first conductive layer forms this first conductive structure, and this first conductive structure has a upper surface; This groove structure is filled up with a dielectric structure; Planarization also removes this dielectric structure of part to form one first dielectric structure, wherein this first dielectric structure there is a upper surface and the upper surface of this first dielectric structure lower than the upper surface of this first conductive structure; Remove this residual second dielectric layer and exposed this first conductive structure to form this workpiece, wherein this top edge-portion is removed the edge pruning surface forming this exposure; By edge pruning surface applications one low temperature oxidization process to this exposure, this subdivision is changed into one first oxide layer, so that this first top is converted to one the 3rd top, wherein this first oxide layer covers the 3rd top; Remove this first oxide layer, the 3rd top is converted to this second top; And cover this second top to form this nonvolatile memory device.
The manufacture method of aforesaid nonvolatile memory device, the wherein said step removing this dielectric structure performs by one of them of a dilute hydrofluoric acid cleaning course and a dry etch process; The described step removing this residual second dielectric layer performs by the hot phosphoric acid cleaning course of use one; This first top has one first forward sight lid profile, this second top has one second forward sight lid profile, this the first forward sight lid profile and this second forward sight lid profile have one first minimum regressive curvature radius and one second minimum regressive curvature radius respectively, and this first minimum regressive curvature radius is less than this second minimum regressive curvature radius; This low temperature oxidization process comprises one selected from a low temperature plasma oxidation process, a free-radical oxidation process and an ozone clean process; And this low temperature oxidization process comprises first-class to oxidizing process, this first top is in the edge pruning damaged surfaces of this exposure, and the described step step that this subdivision changes being comprised this damage of repairing.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The manufacture method of a kind of nonvolatile memory device proposed according to the present invention, this manufacture method comprises the following steps: formation one transistor workpiece and is arranged on one first conductive layer in this transistor workpiece; And form a top surface of this conductive layer, wherein this top surface has is a limited minimum regressive curvature radius.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid nonvolatile memory device, wherein this transistor workpiece comprises a dielectric module, and this first conductive layer is arranged on below this dielectric module; This dielectric module comprises one first dielectric part and a dielectric structure, and wherein this first dielectric part has one first thickness, and is arranged on this first conductive layer and below this dielectric structure, and this dielectric structure is coupled in this first conductive layer; This dielectric structure comprises one second dielectric part, one the 3rd dielectric part and a dielectric layer; This first conductive layer has one second thickness, a top edge-portion and a current-carrying part; This manufacture method also comprises the following steps: one of them by a chemical mechanical planarization process and an etch back process, and this dielectric structure planarization is removed this second dielectric part; 3rd dielectric part removed with the thickness that removes being greater than this first thickness, to leave this dielectric layer of this dielectric structure, wherein this dielectric layer comprises one the 4th dielectric part; This first dielectric part and this top edge-portion are removed this current-carrying part leaving this first conductive layer, wherein this current-carrying part comprises one first top, this first top has a subdivision, this subdivision has the edge pruning surface of an exposure, and this top edge-portion is removed the edge pruning surface forming this exposure; By edge pruning surface applications one low temperature oxidization process to this exposure, this subdivision is changed into one first oxide layer, so that this first top is converted to one second top, wherein this first oxide layer covers this second top; By removing this first oxide layer and the 4th dielectric part, this second top is converted to one the 3rd top, wherein the 3rd top has this top surface; And cover the 3rd top to form this nonvolatile memory device.
The manufacture method of aforesaid nonvolatile memory device, the step of this transistor workpiece of wherein said formation comprises the following steps: to provide a substrate, and wherein this substrate comprises a substrate portion; Square one-tenth one first dielectric layer on the substrate, wherein this first dielectric layer comprises one first dielectric part; Form one second conductive layer at this first dielectric layer, wherein this second conductive layer comprises a current-carrying part and this first conductive layer; This second conductive layer forms one second dielectric layer, and wherein this second dielectric layer comprises one second dielectric part and one the 3rd dielectric part; Remove by by this second dielectric part, this current-carrying part, this first dielectric part and this substrate portion, form a groove structure, with this first conductive layer of the 3rd dielectric part He this second conductive layer that leave this second dielectric layer; And fill up this groove structure with a dielectric structure and form this transistor workpiece.
The object of the invention to solve the technical problems realizes in addition more by the following technical solutions.According to a kind of nonvolatile memory device that the present invention proposes, this nonvolatile memory device comprises a transistor arrangement and one first conductive layer.This conductive layer to be arranged in this transistor arrangement and to have a top surface, and wherein this top surface has is a limited minimum regressive curvature radius.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid nonvolatile memory device, wherein said transistor arrangement comprises: a substrate, has a top; One tunneling layer, is arranged on this top of this substrate, and wherein this first conductive layer to be arranged on this tunneling layer and to have bottom one; One trench isolation layer, be coupled in this top of this substrate, this tunneling layer and this first conductive layer this bottom; One dielectric layer, is arranged on this first conductive layer and this trench isolation layer; And one second conductive layer, be arranged on this dielectric layer, wherein: this top of this substrate, this tunneling layer and this conductive layer this bottom become alignment; This first conductive layer is a polysilicon floating gate layer, this second conductive layer is a control gate layer, and have more a first surface and the regressive curvature radius distribution in this first surface, wherein this first surface comprises this top surface and is coupled in a side surface of this top surface; This regressive curvature radius distribution has this minimum regressive curvature radius in this top surface; And this top surface extends to this side surface smoothly.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.According to a kind of nonvolatile memory device that the present invention proposes, this nonvolatile memory device comprises one first conductive layer, one second conductive layer and a dielectric layer.This dielectric layer is arranged between this first conductive layer and this second conductive layer, and has domed surface in.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid nonvolatile memory device, also comprises: a substrate, has a top; One tunneling layer, is arranged on this top of this substrate, and wherein this second conductive layer to be arranged on this tunneling layer and to have bottom one; And a trench isolation layer, be coupled in this top of this substrate, this tunneling layer and this conductive layer this bottom, wherein: this first conductive layer is arranged on this dielectric layer, and this dielectric layer is arranged on this second conductive layer and this trench isolation layer; This dielectric layer has more an outer domed surface, an inner surface and an outer surface; This interior domed surface has bottom one first and forms one first top of rounded tip in; This outer domed surface has bottom one second and forms one second top at an outer ring tip; This extends to this inner surface and this first top bottom first smoothly; And this extends to this outer surface and this second top bottom second smoothly.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, nonvolatile memory device of the present invention and manufacture method thereof at least have following advantages and beneficial effect: utilize manufacture method of the present invention to form one first conductive structure, wherein this first conductive structure has one first top; And this first top is converted to one second top, and this second top has a domed surface.Above-mentioned domed surface can reduce the generation of leakage current, improves the data reserve force of element.
In sum, the invention relates to a kind of nonvolatile memory device and manufacture method thereof.The manufacture method of this nonvolatile memory device comprises the following steps: formation one conductive layer, and wherein this conductive layer has one first top; And this first top is converted to one second top, and this second top has a domed surface.This nonvolatile memory device comprises: a transistor arrangement; And one first conductive layer, being arranged in this transistor arrangement and having a top surface, wherein this top surface has is a limited minimum regressive curvature radius.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 be one embodiment of the invention the flow chart of the manufacture method of a nonvolatile memory device is provided.
Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E and Fig. 2 F be one embodiment of the invention the schematic diagram of the manufacture method of this nonvolatile memory device is provided.
Fig. 2 G be one embodiment of the invention the schematic diagram of an alternative configuration that is provided for configuring in fig. 2f.
Fig. 3 be one embodiment of the invention the schematic diagram of a nonvolatile memory device is provided.
Fig. 4 be one embodiment of the invention the schematic diagram of another nonvolatile memory device is provided.
41,81: substrate
411,51: substrate portion
42,44,48,66,88: dielectric layer
43,49: conductive layer
431,53: current-carrying part
44S, 52S, 53S, 54S, 56S, 66S, 76S: top surface
45: groove structure
45S, 9S: surface
46: dielectric structure
46A: pad oxide layer
46B: filler oxide
46Q, 421,52,441,54,56Q, 66Q, 76: dielectric part
47: oxide layer
50: transistor workpiece
501: dielectric module
51D, 511D, 52D, 53D, 83D, 83P: side surface
531,631,731,831,8322,8822,8842,9322: top
53E: top edge-portion
56: plat structure
60: workpiece
63,83: conductive layer
632: subdivision
633: the edge pruning surface of exposure
80: transistor arrangement
82: tunneling layer
83: conductive layer
832: domed surface
8321,835,8821,8841,9321: bottom
86: trench isolation layer
882: outer domed surface
882D: outer surface
884: interior domed surface
884D: inner surface
89: control gate layer
91,91A, 91B, 93,94: nonvolatile memory device
932: top surface
DS1, DS2: specific range
H83: highly
L83: length
MR: mask regions
NR: non-masking region
R1: regressive curvature radius distribution
RM: minimum regressive curvature radius
TH1, TH2: institute removes thickness
TH53, TH54, TH88: thickness
W83: width
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the nonvolatile memory device proposed according to the present invention and its embodiment of manufacture method, structure, method, step, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, should to the present invention for the technological means reaching predetermined object and take and effect obtain one more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the present invention.
Refer to shown in Fig. 1, the flow chart of its provide to by one embodiment of the invention manufacture method 300 of a nonvolatile memory device, the figure wherein for explaining orally manufacture method 300 is in detail presented in Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E and Fig. 2 F.One that relates to and manufacturing in multiple non-volatility memory unit is described for the following of flow process in Fig. 1.In step 302, provide a substrate 41, substrate 41 comprises substrate portion 411 and a substrate portion 51.Such as, substrate 41 is semiconductor substrates, such as a silicon substrate.In step 304, substrate 41 forms a dielectric layer 42, dielectric layer 42 comprises dielectric part 421 and a dielectric part 52.Such as, dielectric layer 42 is monoxide layers, such as silicon monoxide (SiO
2) layer.
Within step 306, dielectric layer 42 forms a conductive layer 43, conductive layer 43 comprises current-carrying part 431 and a current-carrying part 53.Such as, conductive layer 43 is polysilicon layers.In step 308, conductive layer 43 forms a dielectric layer 44, dielectric layer 44 comprises dielectric part 441 and a dielectric part 54.Such as, dielectric layer 44 is hard mask layers.Dielectric layer 44 can be a silicon nitride (Si
3n
4) layer.
In the step 310, pattern dielectric layer 44, application self-aligned shallow trench isolation forms a groove structure 45 from (self-alignedshallow trench isolation, SA-STI) process.Described groove structure 45 extends down into substrate 41 by dielectric layer 44, conductive layer 43 and dielectric layer 42.Such as, dielectric layer 44 configures and has a mask regions and a non-masking region thereon.This self-aligned shallow trench isolation processes forms groove structure 45 in this non-masking part.Groove structure 45 is for separating multiple memory cell region.By step 310, remove by by dielectric part 441, current-carrying part 431, dielectric part 421 and substrate 411 part, form groove structure 45, to leave dielectric part 54, current-carrying part 53, dielectric part 52 and substrate portion 51.Dielectric part 54 and current-carrying part 53 (being a conductive layer) can respectively as a mask layer and floating-gate.Dielectric part 52 and substrate portion 51 can form a tunneling layer and a substrate of this nonvolatile memory device respectively.
In step 312, a dielectric structure 46 is formed to fill up groove structure 45.Such as, dielectric structure 46 is a filler dielectric and comprises an a selectable pad oxide layer 46A and filler oxide 46B.Such as, this filler oxide can be coated with (spinon glass, SOG) technology and formed by employing one high-density plasma (high densityplasma, HDP) deposition or a glass.
In a step 314, cmp (chemical-mechanical polishing, CMP) process or etch back process are used to planarization dielectric structure 46, and wherein dielectric structure 46 is processed until expose dielectric part 54.Utilize step 314, dielectric structure 46 has the plat structure 56 be left.As a result, dielectric part 54 top surface can with the align of plat structure 56.Such as, plat structure 56 is filled up in groove structure 45, and is coupled in dielectric part 54, current-carrying part 53 (being a conductive layer) and dielectric part 52.
In step 316, with the thickness that removes of thickness being greater than dielectric part 54, eat-back or by CMP process plat structure 56, a part for plat structure 56 removed, the dielectric layer 66 be left to make plat structure 56 have.Such as, step 316 performs by a dilute hydrofluoric acid (dilute HF) cleaning course and a dry etch process one of them.Such as, dielectric layer 66 has a top surface, and this top surface of dielectric layer 66 is with the top surface of a specific range lower than current-carrying part 53.
In step 318, dielectric part 54 is removed, and a top edge-portion 53E of current-carrying part 53 can be removed the conductive layer 63 (being a current-carrying part) current-carrying part 53 being had be left simultaneously.Conductive layer 63 has a top 631, and wherein the top 631 of conductive layer 63 can have a subdivision 632, and subdivision 632 has the edge pruning surface 633 of an exposure.Such as, the top edge-portion 53E of current-carrying part 53 is removed the edge pruning surface 633 forming exposure, and step 318 is by the hot phosphoric acid of use one (hot H
3p0
4) cleaning course performs.
In step 320, by application one low temperature oxidization process to the edge pruning surface 633 exposed, subdivision 632 is changed into an oxide layer 47 and top 631 is converted to a top 731, wherein oxide layer 47 covers top 731.Such as, this low temperature oxidization process comprises one selected from a low temperature plasma oxidation process, a free-radical oxidation process and an ozone clean process.
In step 322, oxide layer 47 is removed, and with relevant to the thickness of current-carrying part 53 one thickness that removes, a part for dielectric layer 66 is removed, top 731 is converted to a top 831 and conductive layer 83 and the dielectric part 76 making dielectric layer 66 and conductive layer 63 have respectively to be left, wherein conductive layer 83 has top 831, and top 831 exposes and has a domed surface (domedsurface) 832.Such as, step 322 performs by use one dilute hydrofluoric acid (dilute HF) cleaning course.Such as, dielectric part 76 has a top surface, and this top surface of dielectric part 76 is with the top surface of a specific range higher than dielectric part 52.
In step 324, a dielectric layer 48 is formed on the top 831 of dielectric part 76 and conductive layer 83.Such as, dielectric layer 48 is monoxide oxide nitride (ONO) layers be deposited on the top 831 of dielectric part 76 and conductive layer 83.In step 326, dielectric layer 48 is formed a conductive layer 49 to form this nonvolatile memory device.Such as, conductive layer 49 is polysilicon layers, and dielectric layer 48 is dielectric layers between polycrystal silicon.Such as, dielectric layer 48 is control gate layer for this nonvolatile memory device.
Refer to Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E and Fig. 2 F trival matters, the schematic diagram of its provide to by one embodiment of the invention manufacture method 300 of nonvolatile memory device 91.In Fig. 2 A-Fig. 2 F, nonvolatile memory device 91 comprises two nonvolatile memory device 91A and 91B, such as two floating grid non-volatility memory unit.In order to following describing is convenient to understand, each nonvolatile memory device will be related to although discuss, with reference to one of them of nonvolatile memory device 91A and 91B.Such as, nonvolatile memory device 91A is one of them of a NAND floating grid memory device and a NOR floating grid memory device.
In fig. 2, provide a substrate 41, substrate 41 comprises two substrates part 411 and 51.Such as, substrate 41 is semiconductor substrates, such as a silicon substrate.Substrate 41 has been formed a dielectric layer 42, and dielectric layer 42 comprises two dielectric part 421 and 52.Such as, dielectric layer 42 is monoxide layers, such as silicon monoxide (SiO
2) layer.Dielectric layer 42 has been formed a conductive layer 43, and conductive layer 43 comprises two current-carrying parts 431 and 53.Such as, conductive layer 43 is polysilicon layers.Conductive layer 43 has been formed a dielectric layer 44, and dielectric layer 44 comprises two dielectric part 441 and 54.Such as, dielectric layer 44 is hard mask layers.Dielectric layer 44 can be a silicon nitride (Si
3n
4) layer.
In fig. 2b, remove by by dielectric part 441, current-carrying part 431, dielectric part 421 and substrate portion 411, groove structure 45 is formed, to leave dielectric part 54, current-carrying part 53, dielectric part 52 and substrate portion 51.Groove structure 45 extends down into substrate 41 from the top surface 44S of dielectric layer 44 by dielectric layer 44, conductive layer 43 and dielectric layer 42.Such as, self-aligned shallow trench isolation is applied from (self-aligned shallow trench isolation, SA-STI) process to form groove structure 45.Such as, dielectric part 54 and current-carrying part 53 (being a conductive layer) can respectively as a mask layer and floating-gate.Dielectric part 52 and substrate portion 51 can form a tunneling layer and a substrate of nonvolatile memory device 91A respectively.
Dielectric layer 44 configures has an a mask regions MR and non-masking region NR thereon.This self-aligned shallow trench isolation processes forms groove structure 45 at non-masking part NR.Groove structure 45 is for separating multiple non-volatility memory unit area.Such as, the top 511 of substrate portion 51, dielectric part 52 and current-carrying part 53 become alignment.
In fig. 2b, formed a dielectric structure 46 to fill up groove structure 45, and formed a transistor workpiece 50, dielectric structure 46 is as a filler dielectric.In one embodiment, dielectric structure 46 is monoxide structure, and comprises an a pad oxide layer 46A and filler oxide 46B; Pad oxide layer 46A is by an on-site steam growth (in-situ steam growth, ISSG) or a heat treatment process (thermal process) and be deposited on the surperficial 45S of groove structure 45, then filler oxide 46B be formed on pad oxide layer 46A fill up groove structure 45.Such as, filler oxide 46B can be coated with (spin on glass, SOG) technology and formed by employing one high-density plasma (high densityplasma, HDP) deposition or a glass.Such as, dielectric structure 46 comprises a dielectric part 46Q, a dielectric part 56Q and a dielectric layer 66.
Such as, transistor workpiece 50 can comprise substrate portion 51, dielectric part 52 and a dielectric module 501, wherein dielectric part 52 is arranged in substrate portion 51, current-carrying part 53 is arranged in transistor workpiece 50, and dielectric module 501 is coupled in substrate portion 51, dielectric part 52 and current-carrying part 53.Dielectric module 501 comprises dielectric part 54 and dielectric structure 46, wherein dielectric part 54 is arranged on current-carrying part 53 (being a conductive layer) and below dielectric structure 46, and dielectric structure 46 is coupled in dielectric part 54, current-carrying part 53 and dielectric part 52.Current-carrying part 53 comprises a top edge-portion 53E and a conductive layer 63 (being a current-carrying part), and is to be arranged in dielectric part 52 and below dielectric module 501.Such as, dielectric part 54, current-carrying part 53 and dielectric part 52 by dielectric structure 46 institute around.
In fig. 2 c, cmp (CMP) process or etch back process have been used to planarization dielectric structure 46, and stopped by the top surface 54S of dielectric part 54.Therefore, the dielectric part 46Q (display in fig. 2b) of dielectric structure 46 can be removed to expose dielectric part 54, and the plat structure 56 dielectric structure 46 being had be left, wherein current-carrying part 53 has an a top surface 53S and thickness TH53.Plat structure 56 comprises dielectric part 56Q and dielectric layer 66, dielectric part 56Q has the thickness TH1 that removes, and the top surface of dielectric part 54 can with the align of plat structure 56.
In figure 2d, with the thickness TH1 that removes of thickness TH54 being greater than dielectric part 54, eat-back or by CMP process plat structure 56, the dielectric part 56Q of plat structure 56 removed, and the dielectric layer 66 plat structure 56 being had be left.Such as, the part 56Q of plat structure 56 removes by one of them of a dilute hydrofluoric acid (dilute HF) cleaning course and a dry etch process.Such as, dielectric layer 66 has a top surface 66S, and top surface 66S is with the top surface 53S of a specific range DS1 lower than current-carrying part 53.Dielectric layer 66 comprises two dielectric part 66Q and 76, wherein dielectric part 66Q have one institute remove thickness TH2.
In figure 2d, dielectric part 54 is removed, and the top edge-portion 53E of current-carrying part 53 (display in fig. 2b) can be removed simultaneously make the conductive layer 63 (being a current-carrying part) of current-carrying part 53 stay and form a workpiece 60.Conductive layer 63 comprises a top 631, and wherein the top 631 of conductive layer 63 can have a subdivision 632, and subdivision 632 has the edge pruning surface 633 of an exposure.Such as, top edge-portion 53E is removed the edge pruning surface 633 forming exposure, and hot phosphoric acid (hot H3PO4) cleaning course makes for removing dielectric part 54 and top edge-portion 53E.
Such as, workpiece 60 can comprise substrate portion 51, dielectric part 52, conductive layer 63 and dielectric layer 66.Dielectric layer 66 comprises two dielectric part 66Q and 76, is arranged in substrate portion 51, and is coupled in dielectric part 52 and conductive layer 63.Such as, dielectric part 52 and conductive layer 63 by dielectric layer 66 institute around.
In Fig. 2 E, by application one low temperature oxidization process to the edge pruning surface 633 exposed, subdivision 632 is changed into an oxide layer 47 and top 631 is converted to a top 731, wherein oxide layer 47 covers top 731.Such as, this low temperature oxidization process comprises one selected from a low temperature plasma oxidation process, a free-radical oxidation process and an ozone clean process.
Such as, during this low temperature plasma oxidation process, the temperature of conductive layer 63 is in the scope between 600 DEG C and 700 DEG C; During this free-radical oxidation process, the temperature of conductive layer 63 is in the scope between 600 DEG C and 700 DEG C; During this ozone clean process, the temperature of conductive layer 63 is in the scope between 400 DEG C and 500 DEG C.Such as, this low temperature oxidization process comprises first-class in oxidizing process, and the top 631 of conductive layer 63 is damaged on the edge pruning surface 633 exposed, and this damage on the edge pruning surface 633 exposed is repaired during this low temperature plasma oxidation process.
In fig. 2f, oxide layer 47 is removed, and with the relevant thickness TH2 that removes of the thickness TH53 (showing in fig. 2 c) to current-carrying part 53, the dielectric part 66Q (being presented in Fig. 2 E) of dielectric layer 66 is removed, top 731 is converted to a top 831 and conductive layer 83 and the dielectric part 76 making conductive layer 63 and dielectric layer 66 have respectively to be left, wherein conduction 83 has top 831, and top 831 exposes and has a domed surface 832.Such as, a dilute hydrofluoric acid (dilute HF) cleaning course is the dielectric part 66Q made for removing oxide layer 47 and dielectric layer 66.Such as, dielectric part 76 has a top surface 76S, and top surface 76S is with the top surface 52S of a specific range DS2 higher than dielectric part 52, and dielectric part 76 forms a trench isolation layer of nonvolatile memory device 91A.
Such as, the top 631 of conductive layer 63 has one first forward sight lid profile (front-view capprofile), the top 831 of conductive layer 83 has one second forward sight lid profile, this the first forward sight lid profile and this second forward sight lid profile have one first minimum regressive curvature radius (minimum fittedcurvature radius) and one second minimum regressive curvature radius respectively, and this first minimum regressive curvature radius is less than this second minimum regressive curvature radius.Such as, domed surface 832 to have bottom one 8321 and be coupled in a top 8322 of bottom 8321, and a rounded tip (or a dome) is formed on top 8322.Conductive layer 83 has more a side surface 83D, and bottom 8321 extends to side surface 83D and top 8322 smoothly.Such as, conductive layer 83 has length L83, width W 83 (direction perpendicular to paper) and height H 83, wherein height H 83 is greater than length L83, and/or height H 83 is greater than width W 83, or height H 83 is the lateral width being greater than conductive layer 83.
In fig. 2f, a dielectric layer 48 has been formed on the top 831 of dielectric part 76 and conductive layer 83.Such as, dielectric layer 48 is monoxide oxide nitride (ONO) layers be deposited on dielectric part 76 and top 831.
In fig. 2f, dielectric layer 48 has been formed a conductive layer 49 to form nonvolatile memory device 91A.Such as, conductive layer 49 is polysilicon layers, and dielectric layer 48 is dielectric layers between polycrystal silicon.Such as, conductive layer 83 and conductive layer 49 form a floating-gate and a control gate layer of nonvolatile memory device 91A respectively.
Refer to shown in Fig. 2 G, the schematic diagram of its alternative configuration that be provided for by one embodiment of the invention configuring in fig. 2f.At Fig. 2 F) with the element in Fig. 2 G with same-sign, there is similar function.As shown in Figure 2 G, the top 831 of conductive layer 83 has a top surface 932, and wherein top surface 932 has is a limited minimum regressive curvature radius (minimum fitted curvatureradius) RM.Such as, conductive layer 83 has more a surperficial 9S and the regressive curvature radius distribution R1 in surperficial 9S, and wherein surperficial 9S comprises top surface 932 and is coupled in a side surface 83D of top surface 932.Regressive curvature radius distribution R1 has minimum regressive curvature radius R M in top surface 932.Such as, top surface 932 and side surface 83D have an inverted U-shaped cross section.
Such as, top surface 932 is domed surface and extends to side surface 83D smoothly.Top surface 932 is manufactured by a method, and the method is same as the method manufacturing top surface 832.Such as, top surface 932 to have bottom one 9321 and be coupled in a top 9322 of bottom 9321, and a rounded tip (or a dome) can be formed on top 9322.Bottom 9321 extends to side surface 83D and top 9322 smoothly.
Such as, when continuing the size reducing NAND memory cell, due in the top edge of floating-gate compared with small curvature radius, thinner dielectric layers between polycrystal silicon and less coupling efficiency, by dielectric layers between polycrystal silicon during planning (programming) operation, higher electric field is induced in this top edge of this floating-gate.In order to overcome this problem, the floating-gate (such as conductive layer 83) with rounded tip is provided to for NAND fast-flash memory body unit, and wherein this rounded tip has large radius of curvature.Such as, provide this rounded tip of low temperature oxidization process modulation compared with low thermal budget process, and for self-aligned shallow trench isolation from unit doping profile do not affect.
In one embodiment, provide the manufacture method of a kind of nonvolatile memory device 91A according to Fig. 2 A-Fig. 2 G, this manufacture method comprises the following steps: formation one conductive layer 63, and wherein conductive layer 63 has a top 631; And top 631 is converted to a top 831, top 831 has a domed surface 832.Such as, this manufacture method more comprises the step of formation one workpiece 60, and wherein workpiece 60 can comprise substrate portion 51, dielectric part 52, conductive layer 63 and dielectric layer 66.Dielectric part 52 is arranged in substrate portion 51, and conductive layer 63 is arranged in dielectric part 52, and dielectric layer 66 to be arranged in substrate portion 51 and to be coupled in dielectric part 52 and conductive layer 63.
In one embodiment, according to Fig. 2 A)-Fig. 2 G and provide the manufacture method of a kind of nonvolatile memory device 91A, the conductive layer (such as current-carrying part 53) that this manufacture method comprises the following steps: formation one transistor workpiece 50 and is arranged in transistor workpiece 50; And form a top surface 932 of this conductive layer, wherein top surface 932 has is a limited minimum regressive curvature radius R M.
Such as, top surface 932 has more a regressive curvature radius distribution R1 wherein and a top 9322, and be formed by conversioning transistor workpiece 50 and conductive layer (such as current-carrying part 53), wherein regressive curvature radius distribution R1 has minimum regressive curvature radius R M in top 9322.Such as, top surface 932 formed by a part for the part and this conductive layer that remove transistor workpiece 50, wherein this part of transistor workpiece 50 comprise dielectric part 46Q, 54,56Q and 66Q, this part of this conductive layer comprises top edge-portion 53E and subdivision 632.Such as, top surface 932 can be domed surface 832.
Refer to shown in Fig. 3, the schematic diagram of its provide to by one embodiment of the invention nonvolatile memory device 93.As shown in the figure, nonvolatile memory device 93 comprises transistor arrangement 80 and a conductive layer 83.Conductive layer 83 to be arranged in transistor arrangement 80 and to have a domed surface 832.Such as, transistor arrangement 80 comprises substrate 81, tunneling layer 82, trench isolation layer 86, control gate layer 89 and a dielectric layer 88.Such as, conductive layer 83 is as a floating-gate.
Substrate 81 comprises a top 811.Tunneling layer 82 is arranged on the top 811 of substrate 81, and wherein conductive layer 83 to be arranged on tunneling layer 82 and bottom having one 835.Trench isolation layer 86 is coupled in the bottom 835 of the top 811 of substrate 81, tunneling layer 82 and conductive layer 83.Dielectric layer 88 is arranged on conductive layer 83 and trench isolation layer 86.Control gate layer 89 is arranged on dielectric layer 88.Such as, top 811, tunneling layer 82 and bottom 835 by trench isolation layer 86 institute around, and trench isolation layer 86 is arranged on substrate 81.
Such as, the bottom 835 of the top 811 of substrate 81, tunneling layer 82 and conductive layer 83 becomes alignment.Conductive layer 83 can be a polysilicon floating gate layer.Such as, domed surface 832 to have bottom one 8321 and be coupled in a top 8322 of bottom 8321, and a rounded tip or a dome are formed on top 8322.Conductive layer 83 has more a side surface 83D, and bottom 8321 extends to side surface 83D and top 8322 smoothly.Such as, conductive layer 83 has length L83, width W 83 (direction perpendicular to paper) and height H 83, wherein height H 83 is greater than length L83, and/or height H 83 is greater than width W 83, or height H 83 is the lateral width being greater than conductive layer 83.Such as, domed surface 832 is coupled in side surface 83D, and domed surface 832 and side surface 83D have an inverted U-shaped cross section.
In one embodiment, nonvolatile memory device 93 comprises control gate layer 89, conductive layer 83 and a dielectric layer 88.Dielectric layer 88 is arranged between control gate layer 89 and conductive layer 83, and has domed surface 884 in, and wherein, domed surface 884 is consistent with domed surface 832.Such as, dielectric layer 88 has more outer domed surface 882, inner surface 884D and outer surface 882D, and wherein inner surface 884D is consistent with side surface 83D.Such as, dielectric layer 88 has a thickness TH88, and outer domed surface 882 deviated from from interior domed surface 884 by thickness TH88.
Such as, interior domed surface 884 to have bottom one 8841 and be coupled in a top 8842 of bottom 8841, and outer domed surface 882 to have bottom one 8821 and bottom being coupled in 8821 a top 8822.Rounded tip in one is formed on top 8842, and an outer ring tip is formed on top 8822.Bottom 8841 extends to inner surface 884D and top 8842 smoothly, and bottom 8821 extends to outer surface 882D and top 8822 smoothly.Such as, outer domed surface 882 is coupled in outer surface 882D, and outer domed surface 882 and outer surface 882D have an inverted U-shaped cross section.
Refer to shown in Fig. 4, the schematic diagram of its provide to by one embodiment of the invention another nonvolatile memory device 94.The element in figs. 3 and 4 with same-sign has similar function.As shown in Figure 4, nonvolatile memory device 94 comprises transistor arrangement 80 and a conductive layer 83.Conductive layer 83 to be arranged in transistor arrangement 80 and to have a top surface 932, and wherein top surface 932 has is a limited minimum regressive curvature radius R M.Such as, transistor arrangement 80 comprises substrate 81, tunneling layer 82, trench isolation layer 86, control gate layer 89 and a dielectric layer 88.
Such as, conductive layer 83 has more a surperficial 9S and the regressive curvature radius distribution R1 in surperficial 9S, and wherein surperficial 9S comprises top surface 932 and is coupled in a side surface 83D of top surface 932.Regressive curvature radius distribution R1 has minimum regressive curvature radius R M in top surface 932.Such as, top surface 932 and side surface 83D have an inverted U-shaped cross section.Such as, top surface 932 is domed surface and extends to side surface 83D smoothly.Such as, top surface 932 to have bottom one 9321 and be coupled in a top 9322 of bottom 9321, and a rounded tip (or a dome) can be formed on top 9322.Bottom 9321 extends to side surface 83D and top 9322 smoothly.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when the method and technology contents that can utilize above-mentioned announcement are made a little change or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (6)
1. a manufacture method for nonvolatile memory device, is characterized in that it comprises the following steps:
Form one first conductive structure, wherein this first conductive structure has one first top, and this first top has a subdivision, and this subdivision has the edge pruning surface of an exposure; And
This first top is converted to one second top, and this second top has a domed surface; And
Cover this second top to form this nonvolatile memory device;
Wherein, the formation at this second top comprises the following steps:
By edge pruning surface applications one low temperature oxidization process to this exposure, this subdivision is changed into one first oxide layer, so that this first top is converted to one the 3rd top, wherein this first oxide layer covers the 3rd top; And
Remove this first oxide layer, the 3rd top is converted to this second top.
2. the manufacture method of nonvolatile memory device according to claim 1, is characterized in that it also comprises the following steps:
Form a workpiece, wherein this workpiece comprises this first conductive structure and is coupled in one first dielectric structure of this first conductive structure, and the step of described this workpiece of formation comprises the following steps:
One substrate is provided;
Square one-tenth one first dielectric layer on the substrate;
One first conductive layer is formed at this first dielectric layer;
This first conductive layer forms one second dielectric layer;
Patterning and remove the part of this second dielectric layer, this first conductive layer, this first dielectric layer and this substrate, form residual second dielectric layer, residual first conductive layer, residual first dielectric layer and a groove structure, wherein this residual first conductive layer forms this first conductive structure, and this first conductive structure has a upper surface;
This groove structure is filled up with a dielectric structure;
Planarization also removes this dielectric structure of part to form one first dielectric structure, wherein this first dielectric structure there is a upper surface and the upper surface of this first dielectric structure lower than the upper surface of this first conductive structure;
Remove this residual second dielectric layer to expose this first conductive structure to form this workpiece, wherein the top edge-portion of this first conductive structure is removed the edge pruning surface forming this exposure.
3. the manufacture method of nonvolatile memory device according to claim 2, is characterized in that wherein:
The described step removing this dielectric structure performs by one of them of a dilute hydrofluoric acid cleaning course and a dry etch process;
The described step removing this residual second dielectric layer performs by the hot phosphoric acid cleaning course of use one;
This first top has one first forward sight lid profile, this second top has one second forward sight lid profile, this the first forward sight lid profile and this second forward sight lid profile have one first minimum regressive curvature radius and one second minimum regressive curvature radius respectively, and this first minimum regressive curvature radius is less than this second minimum regressive curvature radius;
This low temperature oxidization process comprises one selected from a low temperature plasma oxidation process, a free-radical oxidation process and an ozone clean process; And
This low temperature oxidization process comprises first-class to oxidizing process, and this first top is in the edge pruning damaged surfaces of this exposure, and the described step step that this subdivision changes being comprised this damage of repairing.
4. a manufacture method for nonvolatile memory device, is characterized in that it comprises the following steps:
Form a transistor workpiece and be arranged on one first conductive layer in this transistor workpiece, wherein, this first conductive layer has one first top, and this first top has a subdivision, and this subdivision has the edge pruning surface of an exposure; And
Form a top surface of this first conductive layer, wherein, this top surface is that a domed surface is formed by the edge pruning surface conversion of this exposure of this first conductive layer, and this top surface to have be a limited minimum regressive curvature radius; And
Cover this top surface to form this nonvolatile memory device;
Wherein, the formation of this top surface comprises the following steps:
By edge pruning surface applications one low temperature oxidization process to this exposure, this subdivision is changed into one first oxide layer, so that this first top is converted to one second top, wherein this first oxide layer covers this second top;
By removing this first oxide layer, this second top is converted to one the 3rd top, wherein the 3rd top has this top surface.
5. the manufacture method of nonvolatile memory device according to claim 4, is characterized in that wherein:
This transistor workpiece comprises a dielectric module, and this first conductive layer is arranged on below this dielectric module;
This dielectric module comprises one first dielectric part and a dielectric structure, and wherein this first dielectric part has one first thickness, and is arranged on this first conductive layer and below this dielectric structure, and this dielectric structure is coupled in this first conductive layer;
This dielectric structure comprises one second dielectric part, one the 3rd dielectric part and a dielectric layer;
This first conductive layer has one second thickness, a top edge-portion and a current-carrying part;
This manufacture method also comprises the following steps:
By one of them of a chemical mechanical planarization process and an etch back process, this dielectric structure planarization is removed this second dielectric part;
3rd dielectric part removed with the thickness that removes being greater than this first thickness, to leave this dielectric layer of this dielectric structure, wherein this dielectric layer comprises one the 4th dielectric part;
This first dielectric part and this top edge-portion are removed this current-carrying part leaving this first conductive layer, and wherein this current-carrying part comprises this first top, and this top edge-portion is removed the edge pruning surface forming this exposure;
By removing this first oxide layer and the 4th dielectric part, this second top is converted to the 3rd top.
6. the manufacture method of nonvolatile memory device according to claim 4, is characterized in that the step of this transistor workpiece of wherein said formation comprises the following steps:
There is provided a substrate, wherein this substrate comprises a substrate portion;
Square one-tenth one first dielectric layer on the substrate, wherein this first dielectric layer comprises one first dielectric part;
Form one second conductive layer at this first dielectric layer, wherein this second conductive layer comprises a current-carrying part and this first conductive layer;
This second conductive layer forms one second dielectric layer, and wherein this second dielectric layer comprises one second dielectric part and one the 3rd dielectric part;
Remove by by this second dielectric part, this current-carrying part, this first dielectric part and this substrate portion, form a groove structure, with this first conductive layer of the 3rd dielectric part He this second conductive layer that leave this second dielectric layer; And
Fill up this groove structure with a dielectric structure and form this transistor workpiece.
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