CN102856255B - There is semiconductor element of metal gates and preparation method thereof - Google Patents
There is semiconductor element of metal gates and preparation method thereof Download PDFInfo
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Abstract
The present invention discloses a kind of preparation method of the semiconductor element with metal gates, the substrate that first provides a surface to be formed with a first transistor and a transistor seconds, and in this first transistor, be formed with a first grid groove. This first transistor has one first conductive type, and this transistor seconds has one second conductive type, and this first conductive type is contrary with this second conductive type. Next sequentially in this first grid groove, form one first workfunction layers and a sacrificial mask layer, remove this sacrificial mask layer of part to expose this first workfunction layers of part subsequently. Afterwards, remove this first workfunction layers of part of exposure, to form a U-shaped workfunction layers in this first grid groove. And after forming this U-shaped workfunction layers, remove this sacrificial mask layer.
Description
Technical field
The present invention relates to one and have semiconductor element of metal gates (metalgate) and preparation method thereof, what especially relate to grid (gatelast) manufacture craft after a kind of enforcement has semiconductor element of metal gates and preparation method thereof.
Background technology
Along with semiconductor element micro constantly, work function (workfunction) metal is in order to replace the control electrode of traditional polysilicon as coupling high-k (high-K) dielectric layer. And the preparation method of difunctional function metal gates can generally be divided into normal-gate (gatefirst) and the large class of rear grid (gatelast) manufacture craft two, wherein, gate fabrication process is again because avoiding the activation tempering of source/drain supershallow connection surface and the contour heat budget manufacture craft of metal silicide, select and there is wider material, therefore gradually replace normal-gate manufacture craft.
Refer to Fig. 1, Fig. 1 is the generalized section of the semiconductor element with metal gates of gate fabrication process after an existing enforcement. In existing rear gate fabrication process, prior to forming a nominal grid (dummygate) in substrate 100 or replacing grid (replacementgate), and complete the general (metal-oxidesemiconductor of metal-oxide-semiconductor (MOS), MOS) transistor unit 110 with inner layer dielectric layer (inter-layerdielectric, ILD) after the making of layer 120, grid is put/replaced to void to be removed, and form a gate trench (gatetrench), then insert different metals according to electrical demand. But, remove void put/replace grid after with insert workfunction metal before, the rete 130 of often first inserting other as barrier layer (barrierlayer) even stressor layers (strainedlayer) etc. And the formation of each rete 130 all can cause the A/F of gate trench to dwindle, form overhang (overhang) as shown in Fig. 1 circle A, and cause subsequent film to be difficult for inserting the problem of gate trench as workfunction layers 140. Serious overhang problem even may cause overhang itself or the follow-up workfunction layers of inserting 140 closely sealed, and then make filling metal (fillingmetal) layer 150 of finally inserting cannot insert gate trench and form space 160, affect the electrical performance of transistor unit 110.
Summary of the invention
Therefore, an object of the present invention is to provide the making of gate fabrication process after a kind of enforcement that solves above-mentioned overhang problem to have the method for the semiconductor element of metal gates.
For reaching above-mentioned purpose, according to the preparation method of a kind of semiconductor element with metal gates provided by the present invention. This preparation method comprises provides a substrate, this substrate surface to be formed with a first transistor and a transistor seconds, and in this first transistor, is formed with a first grid groove (gatetrench). This first transistor has one first conductive type, and this transistor seconds has one second conductive type, and this first conductive type is contrary with this second conductive type. Next in this first grid groove, form one first workfunction metal (workfunctionmetal) layer. After forming this first workfunction layers, in this first grid groove, form a sacrificial mask layer (sacrificialmaskinglayer), remove subsequently this sacrificial mask layer of part, to expose this first workfunction layers of part. Afterwards, remove this first workfunction layers of part of exposure, to form a U-shaped workfunction layers in this first grid groove of part. After forming this U-shaped workfunction layers, remove this sacrificial mask layer.
According to the present invention, separately provide a kind of preparation method of the semiconductor element with metal gates. First this preparation method provides a substrate, this substrate surface is formed with a first transistor and a transistor seconds, in this first transistor, be formed with a first grid groove, and in this transistor seconds, be formed with a second grid groove, and the A/F of this second grid groove is greater than the A/F of this first grid groove. Afterwards, in this first grid groove, form one first workfunction layers. After forming this first workfunction layers, in this first grid groove and this second grid groove, form a sacrificial mask layer, in this substrate, form subsequently a patterning photoresist, this patterning photoresist covers this transistor seconds and exposes this sacrificial mask layer in this first grid groove. Afterwards, remove this sacrificial mask layer of part, to expose this first workfunction layers of part. Finally remove this first workfunction layers of part, to form a U-shaped workfunction layers in this first grid groove.
According to the present invention, also provide a kind of semiconductor element with metal gates. this semiconductor element includes a substrate with a first grid groove and a second grid groove, one is arranged at the gate dielectric in this first grid groove and this second grid groove, the first workfunction layers on one this gate dielectric being arranged in this first grid groove, one is arranged at the second workfunction layers in this second grid groove and this first grid groove, and the filling metal level being arranged in this first workfunction layers and this second workfunction layers. it should be noted that this second workfunction layers in this first grid groove comprises a shape of reverse omega
According to the preparation method of the semiconductor element with metal gates provided by the present invention; to utilize this sacrificial mask layer that does not fill up this first grid groove to protect this first workfunction layers in this first grid groove; to remove smoothly non-essential this first workfunction layers in this substrate; the more important thing is, remove near the plurality of overhang of first grid groove opening. Therefore, the follow-up rete of wanting to insert in this first grid groove can successfully be inserted in first grid groove as the second workfunction layers and filling metal level, avoids the formation in space and can avoid the negative effect of space to semiconductor element electric.
Brief description of the drawings
Fig. 1 is the generalized section of the semiconductor element with metal gates of gate fabrication process after an existing enforcement;
Fig. 2 A to Fig. 8 is the schematic diagram of one first preferred embodiment of the preparation method of the semiconductor element with metal gates provided by the present invention;
Fig. 9 to Figure 12 is the schematic diagram of one second preferred embodiment of the preparation method of the semiconductor element with metal gates provided by the present invention;
Figure 13 to Figure 17 is the schematic diagram of one the 3rd preferred embodiment of the preparation method of the semiconductor element with metal gates provided by the present invention; And
Figure 18 is the schematic diagram of a change type of the present invention's the 3rd preferred embodiment.
Main element symbol description
100 substrates
110 transistor units
120 inner layer dielectric layers
130 retes
140 workfunction layers
150 fill metal level
160 spaces
A circle
200,300 substrates
202,302 shallow isolating trough
204,304 gate dielectrics
204a high dielectric constant gate dielectric layer
206 nominal grids
208,308 intermediate layers
210,310 the first transistors
212,312 transistor secondses
214 the 3rd transistors
220,320 first lightly doped drains
222,322 second lightly doped drains
224 the 3rd lightly doped drains
226,326 clearance walls
230,330 first source/drains
232,332 second source/drains
234 the 3rd source/drains
236 metal silicides
240,340 contact hole etching stopping layers
242,342 inner layer dielectric layers
250 hard mask
260,360 first grid grooves
262,362 second grid grooves
264 the 3rd gate trench
270,370 first workfunction layers
272,372 overhang
274,374U type workfunction layers
276 second workfunction layers
278 fill metal level
280,380 sacrificial mask layers
280a, 380a polysilicon layer
280b, 380b rete
282,382 patterning photoresists
Detailed description of the invention
Refer to Fig. 2 A to Fig. 8, Fig. 2 A to Fig. 8 is the schematic diagram of one first preferred embodiment of the preparation method of the semiconductor element with metal gates provided by the present invention. As shown in Figure 2 A, first this preferred embodiment provides a substrate 200, for example a silicon base, containing silicon base or silicon-coated insulated (silicon-on-insulator, SOI) substrate. In substrate 200, be formed with multiple shallow isolating trough (shallowtrenchisolation, STI) 202 that electrical isolation is provided, in substrate 200, be formed with a first transistor 210, a transistor seconds 212 and one the 3rd transistor 214. The first transistor 210 and the 3rd transistor 214 have one first conductive type, and 212 of transistor secondses have one second conductive type, and the first conductive type is contrary with the second conductive type. There is STI202 that electrical isolation is provided having between the first transistor 210 of opposite conductivity type formula and transistor seconds 212 in addition. Although the first transistor 210 has identical conductive type with the 3rd transistor 214, but there is the difference of live width size, the first transistor 210 can be the transistor unit that live width is less than 40 nanometers (nanometer, nm), for example logic circuit component for instance; The 3rd transistor 214 is for example, for live width is greater than 0.15 micron of (micrometer, μ transistor unit m), static RAM (staticrandomaccessmemory, SRAM) element. In this preferred embodiment, the first conductive type is P type; And the second conductive type is N-type, but be familiar with the personage Ying Zhi of this technology, vice versa.
Refer to Fig. 2 A. The first transistor 210, transistor seconds 212 and the 3rd transistor 214 respectively comprise a gate dielectric 204 and nominal grid 206 as a polysilicon layer, and gate dielectric 204 can be a traditional silicon dioxide layer or a high dielectric constant gate dielectric layer. In addition the first transistor 210, transistor seconds 212 and the 3rd transistor 214 comprise respectively one first lightly doped drain (lightdopeddrain, LDD) 220, one the 2nd LDD222 and one the 3rd LDD224, a clearance wall 226, with one first source/drain 230, one second source/drain 232 and one the 3rd source/drain 234. In addition, the first source/drain 230, the second source/drain 232 and the 3rd source/drain 234 surfaces include respectively a metal silicide 236. And on the first transistor 210, transistor seconds 212 and the 3rd transistor 214, sequentially form a contact hole etching stopping layer (contactetchstoplayer, CESL) 240 and internal layer dielectric (inter-layerdielectric, an ILD) layer 242. The making step of said elements and material are selected, or even implement selective epitaxial growth (selectiveepitaxialgrowth for providing effect of stress more to improve electrical performance in semiconductor industry, SEG) method forms the personage that source/drain 230/232/234 grade is all this field and knows, therefore all repeat no more in this.
Please continue to refer to Fig. 2 A. Forming after CESL240 and ILD layer 242, remove CESL240 and the ILD layer 242 of part by a planarization manufacture craft, until expose the nominal grid 206 of the first transistor 210, transistor seconds 212 and the 3rd transistor 214. Next, in substrate 200, form a hard mask 250. Hard mask 250 covers transistor seconds 212, and is preferably a lamination layer structure. After hard mask 250 to be formed; utilize an applicable etching process to remove the nominal grid of the first transistor 210 and the 3rd transistor 214; respectively at the interior formation one first grid groove 260 of the first transistor 210 and in the interior formation 1 of the 3rd transistor 214 the 3rd gate trench 264, and hard mask 250 covering protection transistor seconds 212 in the time forming first grid groove 260 and the 3rd gate trench 264. As shown in Figure 2 A, because the A/F of gate trench equals the live width of nominal grid 206, therefore the A/F of the 3rd gate trench 264 is greater than the A/F of first grid groove 260. After this etching process finishes, gate dielectric 204 is exposed to the bottom of first grid groove 260 and the 3rd gate trench 264. It should be noted that, this preferred embodiment can be integrated with first gate dielectric (high-Kfirst) manufacture craft, now gate dielectric 204 comprises a high-k (high-K) gate dielectric, it can be selected from the group that silicon nitride (SiN), silicon oxynitride (SiON) and metal oxide form, wherein metal oxide comprises hafnium oxide (hafniumoxide, HfO2), hafnium silicate oxygen compound (hafniumsiliconoxide, HfSiO4), hafnium silicate oxynitrides (hafniumsiliconoxynitride, HfSiON), aluminium oxide (aluminumoxide, Al2O3), lanthana (lanthanumoxide, La2O3), lanthanum aluminate (lanthanumaluminumoxide, LaAlO), tantalum oxide (tantalumoxide, Ta2O5), zirconia (zirconiumoxide, ZrO2), zirconium silicate oxygen compound (zirconiumsiliconoxide, ZrSiO4) or zirconic acid hafnium (hafniumzirconiumoxide, HfZrO4) etc.
In a change type of this preferred embodiment, can expose after the nominal grid 206 of the first transistor 210, transistor seconds 214 and the 3rd transistor 214 in planarization manufacture craft, in substrate 200, directly form a patterning photoresist (not shown). Patterning photoresist covers transistor seconds 212, and exposes the first transistor 210 and the 3rd transistor 214. Patterning photoresist can be at the nominal grid 206 that removes the first transistor 210 and the 3rd transistor 214; and in the first transistor 210 and the 3rd transistor 214 is interior while forming respectively first grid groove 260 and the 3rd gate trench 264, as the mask of protection transistor seconds 212.
Refer in addition Fig. 2 B, Fig. 2 B is the schematic diagram of this first another change type of preferred embodiment. As shown in Figure 2 B, this preferred embodiment also can be integrated with rear gate dielectric (high-Klast) manufacture craft, gate dielectric 204 can be first a traditional silicon dioxide layer, and after forming first grid groove 260 and the 3rd gate trench 264, remove the gate dielectric 204 that is exposed to first grid groove 260 and the 3rd gate trench 264 bottoms, form subsequently a high dielectric constant gate dielectric layer 204a, it can comprise above-mentioned material. And as shown in Figure 2 B, the high dielectric constant gate dielectric layer 204a in first grid groove 260 and the 3rd gate trench 264 has a U-shaped shape, cover sidewall and the bottom of first grid groove 260 and the 3rd gate trench 264.
In addition, please again with reference to figure 2A. After forming first grid groove 260 and the 3rd gate trench 264, or after forming high dielectric constant gate dielectric layer 204a, can in first grid groove 260 and the 3rd gate trench 264, form again an intermediate layer (interlayer) 208 according to product needed, for example a barrier layer (barrierlayer), a stressor layers (strainedstresslayer), a work function are adjusted metal level (tuningmetallayer) or its combination, and are not limited to this.
Please still consult Fig. 2 A. Subsequently, in first grid groove 260 and interior formation one first workfunction layers 270 of the 3rd gate trench 264. It should be noted that while forming the first workfunction layers 270, can near the opening of first grid groove 260, form the overhang indicating just like circle 272. Can be observed significantly by Fig. 2 A, because the A/F of first grid groove 260 is less, therefore the impact of the A/F of overhang 272 on first grid groove 260 is more obvious, and overhang 272 has been dwindled the A/F of first grid groove 260 more. The first workfunction layers 270 is one to meet the metal that the required work function of P transistor npn npn requires, it can be single layer structure or lamination layer structure, for example titanium nitride (titaniumnitride, TiN), titanium carbide (titaniumcarbide, TiC), tantalum nitride (tantalumnitride, TaN), ramet (tantalumcarbide, TaC), tungsten carbide (tungstencarbide, or TiAlN (aluminumtitaniumnitride, TiAlN) etc. WC). But it should be noted that, because the first transistor 210 is a P transistor npn npn, and the work function of its metal gates is between 4.8eV and 5.2eV, the first workfunction layers 270 that therefore this preferred embodiment provides is also not limited to any applicable metal material.
Refer to Fig. 3. after the first workfunction layers 270 to be formed, in substrate 200, form a sacrificial mask layer 280. sacrificial mask layer 280 can be one and fills out the good rete of hole ability, one bottom anti-reflective (the bottomanti-reflectivecoating that for example can form by rotary coating mode, BARC) layer, one polysilicon (polysilicon) layer, the one silicon key (silicondanglingbond that dangles, SHB) lower than many silicon layers (Si-richlayer) of 43%, one spin-on glasses (spin-onglass, SOG) layer, one sacrifices light absorbent (sacrificiallightabsorbingmaterial, SLAM) layer, one oxide-rich (oxide-rich) layer as the DUO being sold by Honeywell company of the U.S.TMDeng, but be not limited to this. In addition, sacrificial mask layer 280 can be illustrated in figure 3 a single rete, but it also can be a composite film (multilayer). Sacrificial mask layer 280 has been inserted first grid groove 260 and the 3rd gate trench 264; And after forming sacrificial mask layer 280, more in substrate 200, form a patterning photoresist 282. As shown in Figure 3, patterning photoresist 282 at least covers the 3rd transistor 214, and exposes the first transistor 210 and transistor seconds 212 regions.
Refer to Fig. 4. Next, carry out an etch-back (etchingback) manufacture craft, utilize applicable etchant, for example carbon monoxide (CO) or oxygen (O2) plasma, remove the partial sacrifice mask layer 280 in substrate 200 surfaces and first grid groove 260. after etch-back manufacture craft, the surface of the sacrificial mask layer 280 in first grid groove 260 is lower than the opening of first grid groove 260, that is lower than the surface of ILD layer 242. now, part the first workfunction layers 270 in substrate 200 surfaces and first grid groove 260 is exposed. in this etch-back manufacture craft, the sacrificial mask layer 280 in the 3rd gate trench 264 is protected by patterning photoresist 282, is not therefore subject to the impact of etch-back manufacture craft. because the A/F of the 3rd gate trench 264 is large compared with the A/F of first grid groove 260, for fear of the impact of micro loading effect (microloadingeffect), for fear of etchant, the larger etching target of contact area being had to this situation of higher rate of etch occurs, and cause sacrificial mask layer 280 in the 3rd gate trench 264 to be damage the first workfunction layers 270 of the 3rd gate trench 264 bottoms by over etching, this preferred embodiment more forms patterning photoresist 282 and protects the sacrificial mask layer 280 in the 3rd gate trench 264.
Refer to Fig. 5. Utilize subsequently another etch-back manufacture craft, utilize applicable etchant, for example chlorine (Cl) or ammoniacal liquor and hydrogen peroxide mixture (ammoniumperoxidemixture, APM), remove and be not sacrificed the first workfunction layers 270 and intermediate layer 208 that mask layer 280 covers. In other words, etch-back manufacture craft removes the first workfunction layers 270 and intermediate layer 208 being exposed in substrate 200 and first grid groove 260; Further remove the hard mask 250 of transistor seconds 212 tops simultaneously. The more important thing is, this etch-back manufacture craft has removed the overhang 272 that first grid groove 260 opening parts form more simultaneously, therefore the first grid groove opening width originally being dwindled by overhang 272 can be returned back to original size. In the time that this etch-back manufacture craft finishes, the interior formation one of first grid groove 260 is by the U-shaped workfunction layers 274 of 280 covering protection of sacrificial mask layer, and the nominal grid 206 in transistor seconds 212 is exposed.
Refer to Fig. 6. Afterwards, utilize a suitable etchant, for example an etchant that comprises oxygen, hydrogen, nitrogen, removes sacrificial mask layer 280. The oxygen content of this etchant is lower than 10%, to avoid being oxidized the first workfunction layers 270 while removing sacrificial mask layer 280, and reduces the electrical performance of semiconductor element. In addition, sacrificial mask layer 280 for different materials still can adopt different etchants, for example, in the time that sacrificial mask layer 280 is many silicon materials, can select concentration to remove lower than 2.5% TMAH (tetramethylammoniumhydroxide, TMAH) solution. It should be noted that in addition sacrificial mask layer 280 etch-back manufacture craft, remove part the first workfunction layers 270, overhang 272 and hard mask 250 etch-back manufacture craft, with remove above-mentioned three steps such as sacrificial mask layer 280 can be coordination (in-situ) implement. And after removing sacrificial mask layer 280, remove the nominal grid 206 of transistor seconds 212 by another suitable etching process, and in the interior formation of transistor seconds 212 second grid groove 262 as shown in Figure 6. A/F that it should be noted that second grid groove 262 is identical with the A/F of first grid groove 260. After this etching process finishes, gate dielectric 204 is exposed to the bottom of second grid groove 262. As previously mentioned, in the time that this preferred embodiment is integrated with first gate dielectric manufacture craft, gate dielectric 204 comprises a high dielectric constant gate dielectric layer; In the time that this preferred embodiment is integrated with rear gate dielectric manufacture craft, gate dielectric 204 can be first a traditional silicon dioxide layer, and remove after forming second grid groove 262, form subsequently a high dielectric constant gate dielectric layer 204a with U-shaped shape. Because the material selected shape of high dielectric constant gate dielectric layer can be with reference to above-mentioned accompanying drawing and disclosure, therefore in this and repeat no more.
Refer to Fig. 7. In addition, after forming second grid groove 262 or forming high dielectric constant gate dielectric layer, optionally in second grid groove 262, form an intermediate layer (not shown) according to product needed, the selection in intermediate layer can be consulted above-mentioned explanation, therefore repeat no more in this again. And after forming intermediate layer, within first grid groove 260, second grid groove 262 and the 3rd gate trench 264, form one second workfunction layers 276. It should be noted that therefore the second workfunction layers 276 can be inserted all gate trench 260/262/264 easily because the opening part of first grid groove 260 no longer includes the overhang that rete forms before. In addition, due to the existence of the interior existing U-shaped workfunction layers 274 of first grid groove 260, the second workfunction layers 276 being therefore formed in first grid groove 260 in U-shaped workfunction layers 274 can have along with this specific profile a Ω or the shape of clock (invertedbell). The second workfunction layers 276 is one to meet the metal that the required work function of N-type transistor requires, and it can be single layer structure or lamination layer structure. The second workfunction layers 276 can be selected from the group that titanium aluminide (TiAl), calorize zirconium (ZrAl), calorize tungsten (WAl), calorize tantalum (TaAl) or calorize hafnium (HfAl) form. But it should be noted that, because transistor seconds 212 is a N-type transistor, and the work function of its metal gates is between 3.9eV and 4.3eV, the second workfunction layers 276 that therefore this preferred embodiment provides is also not limited to any applicable metal material.
Please continue to refer to Fig. 7 and Fig. 8. After forming the second workfunction layers 276, form one in substrate 200 surfaces and fill metal level 278, in order to fill up first grid groove 260, second grid groove 262 and the 3rd gate trench 264. Fill metal level 278 for to have better single-layer metal layer or the complex metal layer of filling out hole ability, it can be selected from the group that the composition metals such as aluminium (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or titanium and titanium nitride (Ti/TiN) form. As shown in Figure 8, after forming filling metal level 278, can carry out a planarization manufacture craft, in order to remove the unnecessary filling metal level in ILD layer 242 surface 278, the second workfunction layers 276, the first workfunction layers 270 and intermediate layer 208, and obtain a rough smooth surface, and form the semiconductor element with metal gates. Have the knack of the personage Ying Zhi of this technology, after planarization manufacture craft, the surface of ILD layer 242 and the top surface copline of filling metal level 278. Above-mentioned planarization manufacture craft is that this has the knack of person known to the personage of this technology, therefore repeat no more in this.
In the first preferred embodiment, U-shaped workfunction layers 274 is in order to meet the work function requirement of P type metal gates, and therefore concerning the first transistor 210, the second workfunction layers 276 and filling metal level 278 can be considered the filling metal level of a compound kenel. It should be noted that, due to the shape facility of U-shaped workfunction layers 274, the first half opening of first grid groove 260 can maintain original size, and effectively reduce the depth-to-width ratio (aspectratio) of first grid groove 260, therefore the second workfunction layers 276 can be inserted smoothly with filling metal level 278, while being avoided filling up first grid groove 260, there is gap (seam), guarantee the reliability of the first transistor 210. The more important thing is; this preferred embodiment utilizes the step of etch-back the first workfunction layers 270 to remove the hard mask 250 of protection transistor seconds 212 simultaneously; need multiform to become a patterning photoresist in the time removing hard mask, to protect the step of the first transistor to compare with prior art; not only can save manufacturing process steps, manufacture craft cost, more can avoid the problems such as photoresist is residual.
It should be noted that in addition; owing to spreading all over each element that live width size is different on single wafer; and the plurality of size range is little to 30nm; more than greatly to 5 μ m; even cause live width to be affected performance by over etching compared with large element causing damage for fear of there is micro loading effect in etching process; this preferred embodiment more forms patterning photoresist 282 as shown in Figure 3 and Figure 4 in the substrate element region that is wider than 0.15 μ m of reaching the standard grade after forming sacrificial mask layer 280, to protect the plurality of element when the etch-back sacrificial mask layer 280. Certainly, in the time that major part on wafer is all live width and is less than the element of 0.15 μ m, in this preferred embodiment, forming patterning photoresist 282 these steps can omit, and directly carries out etch-back manufacture craft, with etch-back sacrificial mask layer 280 to the opening of its surface lower than first grid groove 260.
Refer to Fig. 9 to Figure 12, Fig. 9 to Figure 12 is the schematic diagram of one second preferred embodiment of the preparation method of the semiconductor element with metal gates provided by the present invention. First it should be noted that, in the second preferred embodiment, the element identical with the first preferred embodiment is with identical component symbol explanation, and the material of similar elements is selected and formation step can directly be consulted above-mentioned the first preferred embodiment those disclosed herein, therefore all repeat no more in this. In addition, in Fig. 9, only illustrate the first transistor 210 and transistor seconds 212, work as major part on wafer in order to explanation and be all the situation that live width is less than the element of 0.15 μ m. But in the time also having live width on wafer and be greater than element the 3rd transistor 214 as illustrated in the first preferred embodiment of 0.15 μ m, the personage Ying Ke that has the knack of this technology thinks easily according to Fig. 2 A to Fig. 8 and the status of implementation of the 3rd transistor 214 regions.
Refer to Fig. 9. The second preferred embodiment is different from the first preferred embodiment part and is: at the interior formation first grid of the first transistor 210 groove 260, and after interior formation the first workfunction layers 270 of first grid groove 260, in substrate, first form the rete 280b that a polysilicon layer 280a and an available rotary coating mode form, for example a bottom anti-reflection layer, the silicon key that dangles is sacrificed light absorbent layer, an oxide-rich layer as the DUO being sold by Honeywell company of the U.S. lower than many silicon layers of 43%, a spin-on glasses layer,TMDeng, but be not limited to this. The first workfunction layers 270 is one to meet the metal that the required work function of P transistor npn npn requires as previously mentioned, and it can be single layer structure or lamination layer structure. And in the time forming the first workfunction layers 270, can near the opening of first grid groove 260, form the overhang indicating just like circle 272. In addition, before forming the first workfunction layers 270, also optionally form a foregoing intermediate layer (not shown). Polysilicon layer 280a and rete 280b are respectively as one first mask layer and one second mask layer, and formation one sacrificial mask layer 280, and in other words, the sacrificial mask layer 280 that this preferred embodiment provides is a composite film.
It should be noted that and consider the impact of high temperature on the first workfunction layers 270, in the time forming polysilicon layer 280a, with low temperature manufacture craft for preferably implementing kenel. For instance, can utilize and implement long-pending manufacture craft (physicalvapordeposition, the PVD) formation in the physical vapor Shen polysilicon layer 280a that temperature is lower. In addition, the thickness of polysilicon layer 280a is to be no more than 150 dusts as main. The existence of polysilicon layer 280a; can form after the first workfunction layers 270 with form rete 280b before stand-by period (Q-time) in protect the first workfunction layers 270, avoid the first workfunction layers 270 to be oxidized and affect its work function. In addition, even occur bad in rotary coating manufacture craft patterning manufacture craft and while needing heavy industry (rework), polysilicon layer 280a can protect the first workfunction layers 270 in the time removing bad rete 280b as rete 280b.
Refer to Figure 10. Next, carry out an etch-back manufacture craft, utilize applicable etchant, for example carbon monoxide (CO), oxygen (O2) plasma, be preferably carbon monoxide and hydrogen bromide (HBr) etc., remove the partial sacrifice mask layer 280 in substrate 200 surfaces and first grid groove 260. In the time utilizing oxygen plasma etch-back sacrificial mask layer 280, may occur that oxygen plasma touches the first workfunction layers 270 and oxidation the first workfunction layers 270, and cause the disappearance of the usefulness drift (drift) of element. And in this preferred embodiment, can utilize polysilicon layer 280a as protective layer, avoid oxygen plasma to contact the first workfunction layers 270. After etch-back manufacture craft, the surface of the sacrificial mask layer 280 in first grid groove 260 is lower than the opening of first grid groove 260, that is lower than the surface of ILD layer 242. Now, part the first workfunction layers 270 in substrate 200 surfaces and first grid groove 260 is exposed.
Please continue to refer to Figure 10. Utilize subsequently another etch-back manufacture craft, utilize applicable etchant to remove and be not sacrificed the first workfunction layers 270 that mask layer 280 covers. In other words, etch-back manufacture craft removes the first workfunction layers 270 being exposed in substrate 200 and first grid groove 260; Further remove the hard mask 250 of transistor seconds 212 tops simultaneously. The more important thing is, this etch-back manufacture craft has removed the overhang 272 that first grid groove 260 opening parts form more simultaneously, therefore first grid groove 260 A/Fs that originally dwindled by overhang 272 can be returned back to original size. In the time that this etch-back manufacture craft finishes, the U-shaped workfunction layers 274 that the interior formation one of first grid groove 260 is protected by sacrificial mask layer 280, the nominal grid 206 in transistor seconds 212 is exposed.
In addition, in a change type of this preferred embodiment, after can forming the first workfunction layers 270 in substrate 200, first the first workfunction layers 270 of transistor seconds 212 tops is removed. In this external change type, even can, in the time removing the first workfunction layers 270, also hard mask 250 together be removed. And after the first workfunction layers 270 removing on transistor seconds 212, side forms compound sacrificial mask layer 280 in substrate 200. Remove the partial sacrifice mask layer 280 in substrate 200 surfaces and first grid groove 260 by above-mentioned etch-back manufacture craft subsequently, make the surface of the sacrificial mask layer 280 in first grid groove 260 lower than the opening of first grid groove 260. And remove and be not sacrificed the first workfunction layers 270 and the overhang 272 that mask layer 280 covers by another suitable etch-back manufacture craft, form U-shaped workfunction layers 274 as shown in figure 10.
Refer to Figure 11. Next, utilize a suitable etchant to remove the rete 280b of sacrificial mask layer 280. For instance, can utilize carbon monoxide or oxygen plasma to remove. Because polysilicon layer 208a can be used as the protective layer of the first workfunction layers 270, avoid oxygen plasma to contact the first workfunction layers 270 and cause oxidation, therefore this preferred embodiment more can adopt carbon monoxide or oxygen plasma as etchant. As previously mentioned, the etch-back manufacture craft of above-mentioned sacrificial mask layer 280, remove part the first workfunction layers 270, overhang 272 and hard mask 250 etch-back manufacture craft, with remove above-mentioned three steps such as rete 280b can be coordination implement.
Refer to Figure 12. And after removing rete 280b, remove the nominal grid 206 of transistor seconds 212 by another suitable etching process, and in the interior formation of transistor seconds 212 second grid groove 262 as shown in figure 12. Because nominal grid 206 comprises polysilicon mostly, therefore in the time removing nominal grid 206, can remove the interior remaining polysilicon layer 280a of first grid groove 260 simultaneously. As previously mentioned, the A/F of second grid groove 262 is identical with the A/F of first grid groove 260. After this etching process finishes, gate dielectric 204 is exposed to the bottom of second grid groove 262. And after forming second grid groove 262, can as described in the first preferred embodiment, form high dielectric constant gate dielectric layer, optionally form intermediate layer, form the second workfunction layers, form steps such as filling metal level, planarization manufacture craft, repeat no more in this.
The preparation method of the semiconductor element that has metal gates providing according to this second preferred embodiment; formation one has the sacrificial mask layer 280 of polysilicon layer 280a; to improve the etch-back manufacture craft result of sacrificial mask layer 280; and in etch-back manufacture craft or heavy industry manufacture craft, in the stand-by period, protect the first workfunction layers 270, therefore can more improve the usefulness of the metal gates of final formation.
Refer to Figure 13 to Figure 17, Figure 13 to Figure 17 is the schematic diagram of one the 3rd preferred embodiment of the preparation method of the semiconductor element with metal gates provided by the present invention. First it should be noted that in the 3rd preferred embodiment, the element identical or corresponding with the first preferred embodiment, its material is selected directly to consult above-mentioned the first preferred embodiment those disclosed herein, therefore all repeat no more in this. In addition, Figure 13 to Figure 17 only illustrates and is all the situation that live width is less than the element of 0.15 μ m when major part on wafer. But in the time also having live width on wafer and be greater than element the 3rd transistor 214 as illustrated in the first preferred embodiment of 0.15 μ m, the personage Ying Ke that is familiar with this technology thinks easily according to Fig. 2 A to Fig. 8 and the status of implementation of the 3rd transistor region.
As shown in figure 13, first this preferred embodiment provides a substrate 300, is formed with multiple STI302 that electrical isolation is provided in substrate 300, is formed with a first transistor 310 and a transistor seconds 312 in substrate 300. The first transistor 310 has one first conductive type, and 312 of transistor secondses have one second conductive type, and the first conductive type is contrary with the second conductive type. There is STI302 that electrical isolation is provided having between the first transistor 310 of opposite conductivity type formula and transistor seconds 312 in addition. In this preferred embodiment, the first conductive type is P type; And the second conductive type is N-type, but have the knack of the personage Ying Zhi of this technology, vice versa.
Refer to Figure 13. The first transistor 310 respectively comprises a gate dielectric 304 and a nominal grid (not shown) with transistor seconds 312, and gate dielectric 304 can be a traditional silicon dioxide layer or a high dielectric constant gate dielectric layer. In addition the first transistor 310 and transistor seconds 312 comprise respectively one the one LDD320 and one the 2nd LDD322, a clearance wall 326, and one first source/drain 330 and one second source/drain 332 and be formed at the metal silicide 336 on its surface. And on the first transistor 310 and transistor seconds 312, sequentially form a CESL340 and an ILD layer 342. The making step of said elements and material are selected, or even are known by providing effect of stress more to improve the personage that SEG method that electrical performance implements etc. is all this field in semiconductor industry, therefore all repeat no more in this.
Please continue to refer to Figure 13. Forming after CESL340 and ILD layer 342, remove CESL340 and ILD layer 342 by a planarization manufacture craft, until expose the nominal grid of the first transistor 310 and transistor seconds 312. Next, utilize an applicable etching process to remove the nominal grid of the first transistor 310 and transistor seconds 312, respectively at the first transistor 310 and the interior formation one first grid groove 360 of transistor seconds 312 and a second grid groove 362. After this etching process finishes, gate dielectric 304 is exposed to the bottom of first grid groove 360 and second grid groove 362. As previously mentioned, this preferred embodiment can be integrated with first gate dielectric manufacture craft, and now gate dielectric 304 comprises a high dielectric constant gate dielectric layer, and material options can be consulted the first preferred embodiment. In addition, this preferred embodiment also can be integrated with rear gate dielectric manufacture craft, gate dielectric 304 can be first a traditional silicon dioxide layer, and after forming first grid groove 360 and second grid groove 362, remove the gate dielectric 304 that is exposed to first grid groove 360 and second grid groove 362 bottoms, form subsequently a high dielectric constant gate dielectric layer (not shown), it can comprise above-mentioned material.
Please still consult Figure 13. Subsequently, in substrate 300, form one first workfunction layers 370, in addition before forming the first workfunction layers 370, can in each first grid groove 360 and second grid groove 362, form again an intermediate layer 308 according to product needed, for example a barrier layer, a stressor layers, a work function are adjusted metal level or its combination, and are not limited to this. And after forming the first workfunction layers 370, remove the first workfunction layers 370 in second grid groove 362 by a patterning manufacture craft, the first workfunction layers 370 is mainly present in first grid groove 360. It should be noted that in addition while forming the first workfunction layers 370, can near the opening of first grid groove 360, form the overhang indicating just like circle 372. Can be observed significantly by Figure 13, because the A/F of first grid groove 360 is less, therefore the impact of the A/F of the overhang 372 of the first workfunction layers 370 on first grid groove 360 is very obvious, and overhang 372 has been dwindled the A/F of first grid groove 360 more. Because the first transistor 310 is a P transistor npn npn, and the work function of its metal gates is between 4.8eV and 5.2eV, therefore the first workfunction layers 370 that this preferred embodiment provides can be consulted the first preferred embodiment, but is also not limited to any applicable metal material. And the first workfunction layers 370 can be a single layer structure or lamination layer structure.
Refer to Figure 14. After the first workfunction layers 370 to be formed, in substrate 300, form a sacrificial mask layer 380. Sacrificial mask layer 380 can be one and fills out the good rete of hole ability, and a bottom anti-reflection layer, a polysilicon layer, a silicon that for example can form by the rotary coating mode key that dangles is sacrificed light absorbent layer, an oxide-rich layer as the DUO being sold by Honeywell company of the U.S. lower than many silicon layers of 43%, a spin-on glasses layer,TMDeng, but be not limited to this. As previously mentioned, sacrificial mask layer 380 can be a single rete as shown in figure 14, but it also can be a composite film. Within sacrificial mask layer 380 has been inserted first grid groove 360 and second grid groove 362. And after forming sacrificial mask layer 380, more in substrate 300, form a patterning photoresist 382. As shown in figure 14, patterning photoresist 382 exposes the first transistor 310, especially the sacrificial mask layer 380 in first grid groove 360.
Refer to Figure 15. Next, carry out an etch-back manufacture craft, utilize applicable etchant, etch exposed partial sacrifice mask layer 380 out. After etch-back manufacture craft, the surface of sacrificial mask layer 380 is lower than the opening of first grid groove 360, that is lower than the surface of ILD layer 342. Now, part the first workfunction layers 370 in substrate 300 surfaces and first grid groove 360 is exposed. In this etch-back manufacture craft, the sacrificial mask layer 380 in second grid groove 362 is protected by patterning photoresist 382, is not therefore subject to the impact of etch-back manufacture craft. In other words, the sacrificial mask layer 380 in second grid groove 362 still can protect in follow-up manufacture craft relaying continuation of insurance the gate dielectric 304 of second grid groove 362 bottoms.
Refer to Figure 16. Utilize subsequently another etch-back manufacture craft, utilize applicable etchant, remove and be not sacrificed the first workfunction layers 370 and intermediate layer 308 that mask layer 380 covers. The more important thing is, this etch-back manufacture craft has removed the overhang 372 that first grid groove 360 opening parts form more simultaneously, therefore first grid groove 360 A/Fs that originally dwindled by overhang 372 can be returned back to original size. In the time that this etch-back manufacture craft finishes, the interior formation one of first grid groove 362 is by the U-shaped workfunction layers 374 of 380 covering protection of sacrificial mask layer.
Refer to Figure 17. Afterwards, utilize a suitable etchant, a for example etchant that comprises oxygen, hydrogen, nitrogen, removes patterning photoresist 382 and sacrificial mask layer 380. It should be noted that in addition sacrificial mask layer 380 etch-back manufacture craft, remove part the first workfunction layers 370 and the etch-back manufacture craft of overhang 372, with remove above-mentioned three steps such as sacrificial mask layer 380 and can be coordination and implement. After removing patterning photoresist 382 and sacrificial mask layer 380, U-shaped workfunction layers 374 is exposed in first grid groove 360, and gate dielectric 304 is exposed to the bottom of second grid groove 362. Afterwards, can as described in the first preferred embodiment, form high dielectric constant gate dielectric layer, optionally form intermediate layer, form the second workfunction layers, form steps such as filling metal level, planarization manufacture craft, repeat no more in this.
In this preferred embodiment, due to the shape facility of U-shaped workfunction layers 374, the first half opening of first grid groove 360 can maintain original size, and effectively reduce the depth-to-width ratio (aspectratio) of first grid groove 360, therefore the second workfunction layers can be inserted smoothly with filling metal level, while being avoided filling up first grid groove 360, there is gap (seam), guarantee the reliability of the first transistor 310.
It should be noted that in addition, electrically contrary owing to spreading all on single wafer, each element that live width size is different, and the plurality of size range is little to 30nm, more than greatly to 5 μ m, even cause live width to be affected performance by over etching compared with large element area causing damage for fear of there is micro loading effect in etching process, and avoid electrically contrary element area etched and have influence on gate dielectric, this preferred embodiment can form after sacrificial mask layer 380, reach the standard grade and be wider than the element region of 0.15 μ m and the element region of tool opposite conductivity type formula formation patterning photoresist 382 in substrate, to protect the plurality of element when the etch-back sacrificial mask layer 380. therefore,, even if the gate trench that conductive type is contrary, size is different forms simultaneously, it need U-shaped workfunction layers 374 parts of formation be the etching target of etch-back manufacture craft that this preferred embodiment still can be guaranteed only to have, and does not have influence on other element areas.
Refer in addition Figure 18, Figure 18 is the schematic diagram of a change type of the 3rd preferred embodiment. Sacrificial mask layer 380 in this 3rd preferred embodiment can, if Figure 14 is to Figure 16 shows that a single layer structure, can be also a lamination layer structure as shown in figure 18. This change type is after interior formation the first workfunction layers 370 of first grid groove 360, in substrate, first form the rete 380b that a polysilicon layer 380a and an available rotary coating mode form, for example a bottom anti-reflection layer, the silicon key that dangles is sacrificed light absorbent layer, an oxide-rich layer as the DUO being sold by Honeywell company of the U.S. lower than many silicon layers of 43%, a spin-on glasses layer,TMDeng, but be not limited to this. Polysilicon layer 380a and rete 380b are respectively as one first mask layer and one second mask layer, and the sacrificial mask layer 380 of formation one compound kenel.
As previously mentioned, consider the impact of high temperature on the first workfunction layers 370, in the time forming polysilicon layer 380a, with low temperature manufacture craft for preferably implementing kenel. For instance, can utilize and implement the long-pending manufacture craft formation in the physical vapor Shen polysilicon layer 380a that temperature is lower. In addition, the thickness of polysilicon layer 380a is to be no more than 150 dusts as main. The existence of polysilicon layer 380a; can form after the first workfunction layers 370 with form rete 380b before stand-by period (Q-time) in protect the first workfunction layers 370, avoid protecting the first workfunction layers 370 and touch oxygen and affect its work function. In addition, even occur bad in rotary coating manufacture craft patterning manufacture craft and while needing heavy industry, polysilicon layer 380a can protect the first workfunction layers 370 in the time removing bad rete 380b as rete 380b.
According to this change type; formation one has the sacrificial mask layer 380 of polysilicon layer 380a; to improve the etch-back manufacture craft result of sacrificial mask layer 380, therefore and in etch-back manufacture craft or heavy industry manufacture craft, in the stand-by period, protect the first workfunction layers 370 can more improve the usefulness of the metal gates of final formation.
According to the preparation method of the semiconductor element with metal gates provided by the present invention; utilize this sacrificial mask layer that does not fill up this first grid groove to protect this first workfunction layers in this first grid groove; to remove smoothly non-essential this first workfunction layers in this substrate; the more important thing is, remove near the plurality of overhang of first grid groove opening. Therefore, the follow-up rete of wanting to insert in this first grid groove can successfully be inserted in first grid groove as the second workfunction layers and filling metal level, avoids the formation in space and can avoid the negative effect of space to semiconductor element electric.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (31)
1. a preparation method with the semiconductor element of metal gates, includes:
One substrate is provided, and this substrate surface is formed with a first transistor and a transistor seconds, and this is first years oldTransistor has one first conductive type and this transistor seconds has one second conductive type, and this first is ledElectricity pattern is contrary with this second conductive type, is formed with a first grid groove (gate in this first transistorTrench), in this transistor seconds, be formed with a second grid groove, this second grid groove and this firstGate trench forms simultaneously, and the opening of the A/F of this second grid groove and this first grid grooveWidth is identical;
In this first grid groove, form one first workfunction metal (workfunctionmetal) layer;
In this first grid groove and this second grid groove, form a sacrificial mask layer (sacrificialmaskinglayer)；
Remove this sacrificial mask layer of part, to expose this first workfunction layers of part, and this sacrificeMask layer fills up this second grid groove;
Remove this first workfunction layers of part of exposure, with shape in this first grid groove of partBecome a U-shaped workfunction layers; And
Remove this sacrificial mask layer.
2. preparation method as claimed in claim 1, wherein this sacrificial mask layer is a composite film, andThis composite film comprises the first mask layer and the second mask layer.
3. preparation method as claimed in claim 2, also comprises an etch-back manufacture craft, in order to removeThis partial sacrifice mask layer, makes this sacrificial mask layer not fill up this first grid groove.
4. preparation method as claimed in claim 3, also comprises an etching process, in order to remove thisThis first mask layer of sacrificial mask layer, and leave this second mask layer.
5. preparation method as claimed in claim 1, also comprises an etch-back manufacture craft, in order to removeThis partial sacrifice mask layer, makes this sacrificial mask layer not fill up this first grid groove.
6. preparation method as claimed in claim 1 also comprised before removing this partial sacrifice mask layerOn this sacrificial mask layer, form one first patterning photoresist, and this first patterning photoresistAgent exposes this sacrificial mask layer in this first grid groove.
7. preparation method as claimed in claim 6, also comprises following steps:
In this substrate, form a hard mask, in the time forming this first grid groove, covering protection shouldTransistor seconds; And
Remove this part the first workfunction layers and this hard mask of exposure simultaneously.
8. preparation method as claimed in claim 7, wherein this first workfunction layers also comprises at leastOne overhang, and this part the first workfunction layers and this hard mask of this overhang and exposureWith by time remove.
9. preparation method as claimed in claim 1, also comprises one in this first grid groove and this secondIn gate trench, sequentially form one second workfunction layers and and fill the step of metal (fillingmetal) layerSuddenly.
10. preparation method as claimed in claim 9, wherein this second merit in this first grid grooveFunction metal level comprises a shape of reverse omega shape.
11. preparation methods as claimed in claim 1, also comprise one the 3rd transistor, are arranged at this base, while wherein forming this first grid groove, in the 3rd transistor, form one the 3rd grid simultaneously at the endGroove, and the A/F of the 3rd gate trench is greater than the A/F of this first grid groove.
12. preparation methods as claimed in claim 11, also comprise following steps, are carried out at this portion that removesPoint sacrificial mask layer is with before exposing this part first workfunction layers:
In the 3rd gate trench, form this sacrificial mask layer; And
In this substrate, form one second patterning photoresist, this second patterning photoresist coversCover the 3rd transistor and expose this first transistor.
13. 1 kinds have the preparation method of the semiconductor element of metal gates, include:
One substrate is provided, and this substrate surface is formed with a first transistor and a transistor seconds, and this is first years oldThis transistor seconds of transistor AND gate has the first conductive type, is formed with a first grid in this first transistorUtmost point groove, and be formed with a second grid groove in this transistor seconds, and the opening of this second grid grooveMouth width is greater than the A/F of this first grid groove;
In this first grid groove and this second grid groove, form one first workfunction layers;
In this first grid groove and this second grid groove, form a sacrificial mask layer;
In this substrate, form a patterning photoresist, this patterning photoresist cover this secondTransistor also exposes this sacrificial mask layer in this first grid groove;
Remove this sacrificial mask layer of part, to expose this first work function of part in first grid grooveMetal level, and this sacrificial mask layer fills up this second grid groove; And
Remove this first workfunction layers of part of exposure, to form a U in this first grid grooveShape workfunction layers.
14. preparation methods as claimed in claim 13, wherein this sacrificial mask layer is a composite film,And this composite film comprises one first mask layer and one second mask layer.
15. preparation methods as claimed in claim 14, also comprise an etch-back manufacture craft, in order to moveExcept this partial sacrifice mask layer, make this sacrificial mask layer not fill up this first grid groove.
16. preparation methods as claimed in claim 15, also comprise an etching process, in order to removeThis first mask layer of this sacrificial mask layer, and leave this second mask layer.
17. preparation methods as claimed in claim 13, also comprise an etch-back manufacture craft, in order to moveExcept this partial sacrifice mask layer.
18. preparation methods as claimed in claim 13, also comprise a step that removes this sacrificial mask layerSuddenly, after being carried out at this U-shaped workfunction layers of formation.
19. preparation methods as claimed in claim 13, also comprise one the 3rd transistor, are arranged at this base, the 3rd transistor has the second conductive type at the end, and this first conductive type and this second conductivity typeFormula is contrary.
20. preparation methods as claimed in claim 19, wherein the 3rd transistor also comprises the 3rd gridGroove, and the 3rd gate trench and this first grid groove and this second grid groove form simultaneously.
21. preparation methods as claimed in claim 20, wherein the A/F of the 3rd gate trench withThe A/F that this first grid groove comprises is identical, and this sacrificial mask layer fills up the 3rd grid ditchGroove.
22. preparation methods as claimed in claim 21, wherein this patterning photoresist also covers thisThis sacrificial mask layer in the 3rd gate trench.
23. preparation methods as claimed in claim 20, also comprise one this first grid groove, thisIn two gate trench and the 3rd gate trench, sequentially form one second workfunction layers and and fill goldBelong to the step of layer.
24. preparation methods as claimed in claim 23, wherein this second merit in this first grid grooveFunction metal level comprises a shape of reverse omega shape.
25. 1 kinds have the semiconductor element of metal gates, include:
Substrate, have first grid groove and second grid groove, and the opening of this second grid groove is wideDegree is greater than the A/F of this first grid groove;
Gate dielectric, is arranged at respectively in this first grid groove and this second grid groove;
The first workfunction layers, is arranged at these grid in this first grid groove and this second grid grooveOn utmost point dielectric layer, the highest part of this first workfunction layers in this first grid groove lower than thisOne opening of one gate trench, the highest part of this first workfunction layers in this second grid grooveAn opening copline with this second grid groove;
The second workfunction layers, is arranged at respectively in this second grid groove and this first grid groove,And this second workfunction layers in this first grid groove comprises a shape of reverse omega; And
Fill metal level, be arranged in this first workfunction layers and this second workfunction layers.
26. semiconductor elements as claimed in claim 25, wherein this gate dielectric is that a high dielectric is normalNumber (high-K) gate dielectric.
27. semiconductor elements as claimed in claim 26, wherein this high dielectric constant gate dielectric layer bagContaining a U-shaped shape or yi word pattern shape.
28. semiconductor elements as claimed in claim 25, also comprise an intermediate layer (interlayer), establishBe placed between this first workfunction layers and this gate dielectric, this intermediate layer comprises barrier layer (barrierLayer), a stressor layers (strainedstresslayer), a work function are adjusted metal level (tuningmetallayer)Or its combination.
29. semiconductor elements as claimed in claim 28, wherein this intermediate layer comprises a U-shaped shapeOr yi word pattern shape.
30. semiconductor elements as claimed in claim 25, wherein this first workfunction layers comprises oneU word shape.
31. semiconductor elements as claimed in claim 25, wherein in this first grid groove this secondWorkfunction layers is arranged between this first workfunction layers and this filling metal level.
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| CN105280486B (en) * | 2014-07-23 | 2020-09-22 | 联华电子股份有限公司 | Method for manufacturing metal gate structure |
| CN105552116B (en) * | 2014-10-30 | 2021-05-11 | 联华电子股份有限公司 | Metal gate structure and forming method thereof |
| KR102271239B1 (en) * | 2015-03-23 | 2021-06-29 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| CN106298656A (en) * | 2015-05-20 | 2017-01-04 | 联华电子股份有限公司 | Semiconductor device manufacturing method |
| CN105047613A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Metal gate forming method |
| CN106910737B (en) * | 2015-12-23 | 2021-01-15 | 联华电子股份有限公司 | Semiconductor device and method for forming the same |
| CN107731929B (en) * | 2017-09-28 | 2019-12-13 | 信利（惠州）智能显示有限公司 | Method for manufacturing thin film transistor |
| TWI750375B (en) * | 2018-05-16 | 2021-12-21 | 力智電子股份有限公司 | Trench gate mosfet and method of forming the same |
| CN110828377B (en) * | 2018-08-08 | 2022-06-21 | 联华电子股份有限公司 | Semiconductor element with asymmetric work function metal layer |
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