CN102856255A - Semiconductor element with metal gate and manufacture method thereof - Google Patents
Semiconductor element with metal gate and manufacture method thereof Download PDFInfo
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Abstract
The invention discloses a manufacture method of a semiconductor element with a metal gate. The manufacture method comprises the steps as follows: firstly forming a substrate with a first transistor and a second transistor on the surface, wherein a first grid groove is formed in the first transistor, the first transistor has a first conductive mode, the second transistor has a second conductive mode, and moreover, the first conductive mode is opposite to the second conductive mode; secondly forming a first work function metal layer and a sacrificed mask layer in the first grid groove in sequence; then removing partial sacrificed mask layer to expose a part of the first work function meal layer; afterwards, removing the first work function metal layer at the exposed part so as to form an U-shaped work function metal layer in the first grid groove; and removing the sacrificed mask layer after the U-shaped work function metal layer is formed.
Description
Technical field
The present invention relates to a kind of semiconductor element with metal gates (metal gate) and preparation method thereof, what especially relate to grid (gate last) manufacture craft after a kind of implement has semiconductor element of metal gates and preparation method thereof.
Background technology
Along with semiconductor element micro constantly, work function (work function) metal is in order to replace traditional polysilicon as the control electrode of coupling high-k (high-K) dielectric layer.And the manufacture method of difunctional function metal gates can generally be divided into normal-gate (gate first) and rear grid (gate last) manufacture craft two large classes, gate fabrication process is again because avoiding the activation tempering of source/drain supershallow connection surface and the contour heat budget manufacture craft of metal silicide wherein, select and have wider material, therefore gradually replace the normal-gate manufacture craft.
See also Fig. 1, Fig. 1 is the generalized section of the semiconductor element with metal gates of gate fabrication process after existing the enforcement.In existing rear gate fabrication process, prior to forming a nominal grid (dummy gate) in the substrate 100 or replacing grid (replacement gate), and finish (the metal-oxide semiconductor of general metal-oxide-semiconductor (MOS), MOS) transistor unit 110 with inner layer dielectric layer (inter-layer dielectric, ILD) after the making of layer 120, void being put/replace grid removes, and form a gate trench (gate trench), insert different metals according to electrical demand again.Yet, removing void and putting/replace grid after with insert workfunction metal before, the rete 130 of often inserting first other such as barrier layer (barrier layer) even stressor layers (strained layer) etc.And the formation of each rete 130 all can cause the A/F of gate trench to dwindle, and forms the overhang (overhang) shown in Fig. 1 circle A, and causes subsequent film such as workfunction layers 140 to be difficult for inserting the problem of gate trench.Serious overhang problem even may cause overhang itself or the follow-up workfunction layers of inserting 140 driving fits, and then so that the filling metal of inserting at last (filling metal) layer 150 can't be inserted gate trench and form space 160, affect the electrical performance of transistor unit 110.
Summary of the invention
Therefore, a purpose of the present invention is to provide that the making of gate fabrication process has the method for the semiconductor element of metal gates after a kind of enforcement that solves above-mentioned overhang problem.
For reaching above-mentioned purpose, according to a kind of manufacture method with semiconductor element of metal gates provided by the present invention.This manufacture method comprises provides a substrate, this substrate surface to be formed with a first transistor and a transistor seconds, and is formed with a first grid groove (gate trench) in this first transistor.This first transistor has one first conductive type, and this transistor seconds has one second conductive type, and this first conductive type is opposite with this second conductive type.Next in this first grid groove, form one first workfunction metal (work function metal) layer.Form after this first workfunction layers, in this first grid groove, form a sacrificial mask layer (sacrificial masking layer), remove subsequently this sacrificial mask layer of part, to expose this first workfunction layers of part.Afterwards, remove this first workfunction layers of part of exposure, in this first grid groove of part, to form a U-shaped workfunction layers.After forming this U-shaped workfunction layers, remove this sacrificial mask layer.
According to the present invention, other provides a kind of manufacture method with semiconductor element of metal gates.This manufacture method at first provides a substrate, this substrate surface is formed with a first transistor and a transistor seconds, be formed with a first grid groove in this first transistor, and be formed with a second grid groove in this transistor seconds, and the A/F of this second grid groove is greater than the A/F of this first grid groove.Afterwards, in this first grid groove, form one first workfunction layers.After forming this first workfunction layers, in this first grid groove and this second grid groove, form a sacrificial mask layer, form subsequently a patterning photoresist in this substrate, this patterning photoresist covers this transistor seconds and exposes this interior sacrificial mask layer of this first grid groove.Afterwards, remove this sacrificial mask layer of part, to expose this first workfunction layers of part.Remove at last this first workfunction layers of part, in this first grid groove, to form a U-shaped workfunction layers.
According to the present invention, also provide a kind of semiconductor element with metal gates.This semiconductor element includes a substrate with a first grid groove and a second grid groove, one is arranged at the gate dielectric in this first grid groove and this second grid groove, the first workfunction layers on one this gate dielectric that is arranged in this first grid groove, one is arranged at the second workfunction layers in this second grid groove and this first grid groove, an and filling metal level that is arranged on this first workfunction layers and this second workfunction layers.It should be noted that this second workfunction layers in this first grid groove comprises a shape of reverse omega
According to the manufacture method with semiconductor element of metal gates provided by the present invention; to utilize this sacrificial mask layer that does not fill up this first grid groove to protect this interior first workfunction layers of this first grid groove; to remove smoothly non-essential this first workfunction layers in this substrate; the more important thing is, remove near these a plurality of overhang of first grid groove opening.Therefore, the follow-up rete of wanting to insert in this first grid groove can successfully be inserted in the first grid groove such as the second workfunction layers and filling metal level, avoids the formation in space and can avoid the space to the negative effect of semiconductor element electric.
Description of drawings
Fig. 1 is the generalized section of the semiconductor element with metal gates of gate fabrication process after existing the enforcement;
Fig. 2 A to Fig. 8 is the schematic diagram of one first preferred embodiment of the manufacture method of the semiconductor element with metal gates provided by the present invention;
Fig. 9 to Figure 12 is the schematic diagram of one second preferred embodiment of the manufacture method of the semiconductor element with metal gates provided by the present invention;
Figure 13 to Figure 17 is the schematic diagram of one the 3rd preferred embodiment of the manufacture method of the semiconductor element with metal gates provided by the present invention; And
Figure 18 is the schematic diagram of a change type of the present invention's the 3rd preferred embodiment.
The main element symbol description
100 substrates
110 transistor units
120 inner layer dielectric layers
130 retes
140 workfunction layers
150 fill metal level
160 spaces
The A circle
200,300 substrates
202,302 shallow isolating trough
204,304 gate dielectrics
The 204a high dielectric constant gate dielectric layer
206 nominal grids
208,308 intermediate layers
210,310 the first transistors
212,312 transistor secondses
214 the 3rd transistors
220,320 first lightly doped drains
222,322 second lightly doped drains
224 the 3rd lightly doped drains
226,326 clearance walls
230,330 first source/drains
232,332 second source/drains
234 the 3rd source/drains
236 metal silicides
240,340 contact hole etching stopping layers
242,342 inner layer dielectric layers
250 hard mask
260,360 first grid grooves
262,362 second grid grooves
264 the 3rd gate trenchs
270,370 first workfunction layers
272,372 overhang
274,374U type workfunction layers
276 second workfunction layers
278 fill metal level
280,380 sacrificial mask layers
280a, 380a polysilicon layer
280b, 380b rete
282,382 patterning photoresists
Embodiment
See also Fig. 2 A to Fig. 8, Fig. 2 A to Fig. 8 is the schematic diagram of one first preferred embodiment of the manufacture method of the semiconductor element with metal gates provided by the present invention.Shown in Fig. 2 A, this preferred embodiment at first provides a substrate 200, for example a silicon base, contain silicon base or silicon-coated insulated (silicon-on-insulator, SOI) substrate.Be formed with a plurality of shallow isolating trough (shallow trench isolation, STI) 202 that electrical isolation is provided in the substrate 200, then be formed with a first transistor 210, a transistor seconds 212 and one the 3rd transistor 214 in the substrate 200.The first transistor 210 and the 3rd transistor 214 have one first conductive type, and 212 of transistor secondses have one second conductive type, and the first conductive type is opposite with the second conductive type.Between the first transistor 210 with opposite conductivity type formula and transistor seconds 212, then there is STI 202 that electrical isolation is provided in addition.Although the first transistor 210 has identical conductive type with the 3rd transistor 214, but the difference with live width size, the first transistor 210 can be live width less than the transistor unit of 40 nanometers (nanometer, nm), for example logic circuit component for instance; The 3rd transistor 214 then be live width greater than the transistor unit of 0.15 micron (micrometer, μ m), static RAM (static random access memory, SRAM) element for example.In this preferred embodiment, the first conductive type is the P type; And the second conductive type is N-type, and vice versa but be familiar with the personage Ying Zhi of this technology.
See also Fig. 2 A.The first transistor 210, transistor seconds 212 and the 3rd transistor 214 respectively comprise a gate dielectric 204 and nominal grid 206 as a polysilicon layer, and gate dielectric 204 can be a traditional silicon dioxide layer or a high dielectric constant gate dielectric layer.In addition the first transistor 210, transistor seconds 212 and the 3rd transistor 214 comprise respectively one first lightly doped drain (light doped drain, LDD), 220,1 the 2nd LDD 222 and one the 3rd LDD 224, a clearance wall 226, with one first source/drain 230, one second source/drain 232 and one the 3rd source/drain 234.In addition, the first source/drain 230, the second source/drain 232 and the 3rd source/drain 234 surfaces include respectively a metal silicide 236.And on the first transistor 210, transistor seconds 212 and the 3rd transistor 214, sequentially form a contact hole etching stopping layer (contact etch stop layer, CESL) 240 and one internal layer dielectric (inter-layer dielectric, ILD) layer 242.The making step of said elements and material are selected, or even implement selective epitaxial growth (selective epitaxial growth for providing effect of stress more to improve electrical performance in the semiconductor industry, SEG) method forms the personage that source/drain 230/232/234 grade is all this field and knows, therefore neitherly give unnecessary details in this again.
Please continue to consult Fig. 2 A.After forming CESL 240 and ILD layer 242, remove the CESL 240 and ILD layer 242 of part by a planarization manufacture craft, until expose the nominal grid 206 of the first transistor 210, transistor seconds 212 and the 3rd transistor 214.Next, in substrate 200, form a hard mask 250.Hard mask 250 covers transistor seconds 212, and is preferably a lamination layer structure.After the hard mask 250 to be formed; utilize an etching process that is fit to remove the nominal grid of the first transistor 210 and the 3rd transistor 214; respectively at the first transistor 210 interior formation one first grid grooves 260 and in the 3rd transistor 214 interior formation 1 the 3rd gate trenchs 264, and hard mask 250 covering protection transistor seconds 212 when forming first grid groove 260 and the 3rd gate trench 264.Shown in Fig. 2 A, because the A/F of gate trench equals the live width of nominal grid 206, therefore the A/F of the 3rd gate trench 264 is greater than the A/F of first grid groove 260.After this etching process finished, gate dielectric 204 was exposed to the bottom of first grid groove 260 and the 3rd gate trench 264.It should be noted that, this preferred embodiment can be integrated with first gate dielectric (high-K first) manufacture craft, this moment, gate dielectric 204 comprised a high-k (high-K) gate dielectric, it can be selected from the group that silicon nitride (SiN), silicon oxynitride (SiON) and metal oxide form, wherein metal oxide then comprises hafnium oxide (hafnium oxide, HfO
2), hafnium silicate oxygen compound (hafnium silicon oxide, HfSiO
4), hafnium silicate oxynitrides (hafnium silicon oxynitride, HfSiON), aluminium oxide (aluminum oxide, Al
2O
3), lanthana (lanthanum oxide, La
2O
3), lanthanum aluminate (lanthanum aluminum oxide, LaAlO), tantalum oxide (tantalum oxide, Ta
2O
5), zirconia (zirconium oxide, ZrO
2), zirconium silicate oxygen compound (zirconium silicon oxide, ZrSiO
4) or zirconic acid hafnium (hafnium zirconium oxide, HfZrO
4) etc.
In a change type of this preferred embodiment, can after the planarization manufacture craft exposes the nominal grid 206 of the first transistor 210, transistor seconds 214 and the 3rd transistor 214, in substrate 200, directly form a patterning photoresist (not shown).The patterning photoresist covers transistor seconds 212, and exposes the first transistor 210 and the 3rd transistor 214.The patterning photoresist can be at the nominal grid 206 that removes the first transistor 210 and the 3rd transistor 214; and in the first transistor 210 and the 3rd transistor 214 is interior when forming respectively first grid groove 260 and the 3rd gate trench 264, as the mask of protection transistor seconds 212.
See also in addition Fig. 2 B, Fig. 2 B is the schematic diagram of this first another change type of preferred embodiment.Shown in Fig. 2 B, this preferred embodiment also can be integrated with rear gate dielectric (high-K last) manufacture craft, then gate dielectric 204 can be first a traditional silicon dioxide layer, and after forming first grid groove 260 and the 3rd gate trench 264, remove the gate dielectric 204 that is exposed to first grid groove 260 and the 3rd gate trench 264 bottoms, form subsequently a high dielectric constant gate dielectric layer 204a, it can comprise above-mentioned material.And shown in Fig. 2 B, the high dielectric constant gate dielectric layer 204a in first grid groove 260 and the 3rd gate trench 264 has a U-shaped shape, covers sidewall and the bottom of first grid groove 260 and the 3rd gate trench 264.
In addition, please again with reference to figure 2A.After forming first grid groove 260 and the 3rd gate trench 264, or after forming high dielectric constant gate dielectric layer 204a, can in first grid groove 260 and the 3rd gate trench 264, form again an intermediate layer (inter layer) 208 according to product needed, for example a barrier layer (barrier layer), a stressor layers (strained stress layer), a work function are adjusted metal level (tuning metal layer) or its combination, and are not limited to this.
Please still consult Fig. 2 A.Subsequently, in first grid groove 260 and the 3rd gate trench 264 interior formation one first workfunction layers 270.It should be noted that when forming the first workfunction layers 270, can near the opening of first grid groove 260, form the overhang that indicates just like circle 272.Can be observed significantly by Fig. 2 A, because the A/F of first grid groove 260 is less, so overhang 272 is more obvious on the impact of the A/F of first grid groove 260, and namely overhang 272 has been dwindled the A/F of first grid groove 260 more.The first workfunction layers 270 is to satisfy the metal that the required work function of P transistor npn npn requires, it can be single layer structure or lamination layer structure, titanium nitride (titanium nitride for example, TiN), titanium carbide (titanium carbide, TiC), tantalum nitride (tantalum nitride, TaN), ramet (tantalum carbide, TaC), tungsten carbide (tungsten carbide, WC) or TiAlN (aluminum titanium nitride, TiAlN) etc.Yet it should be noted that, because the first transistor 210 is a P transistor npn npn, and the work function of its metal gates is between 4.8eV and 5.2eV, so the first workfunction layers 270 that this preferred embodiment provides also is not limited to any suitable metal material.
See also Fig. 3.After the first workfunction layers 270 to be formed, in substrate 200, form a sacrificial mask layer 280.Sacrificial mask layer 280 can be one and fills out the good rete of hole ability, a bottom anti-reflective (the bottom anti-reflective coating that forms of available rotary coating mode for example, BARC) layer, one polysilicon (polysilicon) layer, one silicon key (the silicon dangling bond that dangles, SHB) be lower than many silicon layers (Si-rich layer) of 43%, one spin-on glasses (spin-on glass, SOG) layer, one sacrifices light absorbent (sacrificial light absorbing material, SLAM) layer, one oxide-rich (oxide-rich) layer as the DUO that is sold by U.S. Honeywell company
TMDeng, but be not limited to this.In addition, sacrificial mask layer 280 can be illustrated in figure 3 as a single rete, but it also can be a composite film (multi layer).Sacrificial mask layer 280 has been inserted first grid groove 260 and the 3rd gate trench 264; And after forming sacrificial mask layer 280, more in substrate 200, form a patterning photoresist 282.As shown in Figure 3, patterning photoresist 282 covers the 3rd transistor 214 at least, and exposes the first transistor 210 and transistor seconds 212 regions.
See also Fig. 4.Next, carry out an etch-back (etching back) manufacture craft, utilize the etchant that is fit to, for example carbon monoxide (CO) or oxygen (O
2) plasma, remove the partial sacrifice mask layer 280 in substrate 200 surfaces and the first grid groove 260.After the etch-back manufacture craft, the surface of the sacrificial mask layer 280 in the first grid groove 260 is lower than the opening of first grid groove 260, that is is lower than the surface of ILD layer 242.At this moment, part the first workfunction layers 270 in substrate 200 surfaces and the first grid groove 260 is exposed.In this etch-back manufacture craft, the sacrificial mask layer 280 in the 3rd gate trench 264 is protected by patterning photoresist 282, therefore is not subjected to the impact of etch-back manufacture craft.Because the A/F of the 3rd gate trench 264 is large than the A/F of first grid groove 260; impact for fear of micro loading effect (micro loading effect); namely occur in order to avoid etchant that the larger etching target of contact area is had this situation of higher rate of etch; and causing the 3rd gate trench 264 interior sacrificial mask layers 280 to be damage the first workfunction layers 270 of the 3rd gate trench 264 bottoms by over etching, this preferred embodiment more forms the sacrificial mask layer 280 in patterning photoresist 282 protections the 3rd gate trench 264.
See also Fig. 5.Utilize subsequently another etch-back manufacture craft, utilize the etchant that is fit to, for example chlorine (Cl) or ammoniacal liquor and hydrogen peroxide mixture (ammonium peroxide mixture, APM) remove and are not sacrificed the first workfunction layers 270 and intermediate layer 208 that mask layer 280 covers.In other words, the etch-back manufacture craft removes the first workfunction layers 270 and intermediate layer 208 that is exposed in substrate 200 and the first grid groove 260; Further remove simultaneously the hard mask 250 of transistor seconds 212 tops.The more important thing is, this etch-back manufacture craft has removed the overhang 272 that first grid groove 260 opening parts form more simultaneously, therefore the first grid groove opening width that is originally dwindled by overhang 272 can be returned back to original size.When this etch-back manufacture craft finished, the 260 interior formation one of first grid groove were by the U-shaped workfunction layers 274 of 280 covering protection of sacrificial mask layer, and the nominal grid 206 in the transistor seconds 212 then is exposed.
See also Fig. 6.Afterwards, utilize a suitable etchant, for example an etchant that comprises oxygen, hydrogen, nitrogen removes sacrificial mask layer 280.The oxygen content of this etchant is lower than 10%, oxidation the first workfunction layers 270 when avoiding removing sacrificial mask layer 280, and reduce the electrical performance of semiconductor element.In addition, sacrificial mask layer 280 for different materials still can adopt different etchants, for example when sacrificial mask layer 280 is many silicon materials, can selects concentration to be lower than 2.5% Tetramethylammonium hydroxide (tetramethylammonium hydroxide, TMAH) solution and remove.It should be noted that in addition sacrificial mask layer 280 the etch-back manufacture craft, remove part the first workfunction layers 270, overhang 272 and hard mask 250 the etch-back manufacture craft, with remove above-mentioned three steps such as sacrificial mask layer 280 and can be coordination (in-situ) and implement.And after removing sacrificial mask layer 280, remove the nominal grid 206 of transistor seconds 212 by another suitable etching process, and in transistor seconds 212 interior formation second grid groove 262 as shown in Figure 6.A/F that it should be noted that second grid groove 262 is identical with the A/F of first grid groove 260.After this etching process finished, gate dielectric 204 was exposed to the bottom of second grid groove 262.As previously mentioned, when this preferred embodiment was integrated with first gate dielectric manufacture craft, gate dielectric 204 comprised a high dielectric constant gate dielectric layer; When this preferred embodiment is integrated with rear gate dielectric manufacture craft, gate dielectric 204 can be first a traditional silicon dioxide layer, and after forming second grid groove 262, remove, form subsequently a high dielectric constant gate dielectric layer 204a with U-shaped shape.Because the material selected shape of high dielectric constant gate dielectric layer can be with reference to above-mentioned accompanying drawing and disclosure, therefore in this and repeat no more.
See also Fig. 7.In addition, after forming second grid groove 262 or forming high dielectric constant gate dielectric layer, optionally form an intermediate layer (not shown) according to product needed in second grid groove 262, the selection in intermediate layer can be consulted above-mentioned explanation again, therefore repeat no more in this.And after forming the intermediate layer, within first grid groove 260, second grid groove 262 and the 3rd gate trench 264, form one second workfunction layers 276.It should be noted that therefore the second workfunction layers 276 can be inserted all gate trenchs 260/262/264 easily because the opening part of first grid groove 260 no longer includes the overhang of before rete formation.In addition, because the existence of first grid groove 260 interior existing U-shaped workfunction layers 274, so the second workfunction layers 276 that is formed in the first grid groove 260 on the U-shaped workfunction layers 274 can have along with this specific profile a Ω or the shape of clock (inverted bell).The second workfunction layers 276 is to satisfy the metal that the required work function of N-type transistor requires, and it can be single layer structure or lamination layer structure.The second workfunction layers 276 can be selected from the group that titanium aluminide (TiAl), calorize zirconium (ZrAl), calorize tungsten (WAl), calorize tantalum (TaAl) or calorize hafnium (HfAl) form.Yet it should be noted that, because transistor seconds 212 is a N-type transistor, and the work function of its metal gates is between 3.9eV and 4.3eV, so the second workfunction layers 276 that this preferred embodiment provides also is not limited to any suitable metal material.
Please continue to consult Fig. 7 and Fig. 8.After forming the second workfunction layers 276, form one in substrate 200 surfaces and fill metal level 278, in order to fill up first grid groove 260, second grid groove 262 and the 3rd gate trench 264.Fill metal level 278 for to have better single-layer metal layer or the complex metal layer of filling out the hole ability, it can be selected from the group that aluminium (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or the composition metals such as titanium and titanium nitride (Ti/TiN) form.As shown in Figure 8, after forming filling metal level 278, can carry out a planarization manufacture craft, in order to remove the unnecessary filling metal level 278 in ILD layer 242 surface, the second workfunction layers 276, the first workfunction layers 270 and intermediate layer 208, and obtain a rough smooth surface, and form the semiconductor element with metal gates.Have the knack of the personage Ying Zhi of this technology, after the planarization manufacture craft, the surface of ILD layer 242 and the top surface copline of filling metal level 278.Above-mentioned planarization manufacture craft is had the knack of person known to the personage of this technology for this, therefore repeat no more in this.
In the first preferred embodiment, U-shaped workfunction layers 274 is in order to satisfy the work function requirement of P type metal gates, and therefore concerning the first transistor 210, the second workfunction layers 276 and filling metal level 278 can be considered the filling metal level of a compound kenel.It should be noted that, because the shape facility of U-shaped workfunction layers 274, the first half opening of first grid groove 260 can be kept original size, and effectively reduce the depth-to-width ratio (aspect ratio) of first grid groove 260, therefore the second workfunction layers 276 can be inserted smoothly with filling metal level 278, slit (seam) occurs when being avoided filling up first grid groove 260, guarantees the reliability of the first transistor 210.The more important thing is; this preferred embodiment utilizes the step of etch-back the first workfunction layers 270 to remove simultaneously the hard mask 250 of protection transistor seconds 212; need multiform to become a patterning photoresist when removing hard mask, to protect the step of the first transistor to compare with prior art; not only can save manufacturing process steps, manufacture craft cost, more can avoid the problems such as photoresist is residual.
It should be noted that in addition; owing to spreading all over each different element of live width size on the single wafer; and these a plurality of size ranges are little to 30nm; greatly to more than the 5 μ m; even micro loading effect occurs in the etching process to be caused the larger element of live width to be affected performance by over etching causing damage; this preferred embodiment more forms as shown in Figure 3 and Figure 4 patterning photoresists 282 in the reach the standard grade element region that is wider than 0.15 μ m of substrate after forming sacrificial mask layer 280, with these a plurality of elements of protection when the etch-back sacrificial mask layer 280.Certainly, when major part on the wafer is all live width less than the element of 0.15 μ m, forming patterning photoresist 282 these steps in this preferred embodiment can omit, and directly carries out the etch-back manufacture craft, is lower than the opening of first grid groove 260 with etch-back sacrificial mask layer 280 to its surface.
See also Fig. 9 to Figure 12, Fig. 9 to Figure 12 is the schematic diagram of one second preferred embodiment of the manufacture method of the semiconductor element with metal gates provided by the present invention.At first it should be noted that, in the second preferred embodiment, the element identical with the first preferred embodiment be with the explanation of identical component symbol, and the material of similar elements selects and form step directly to consult above-mentioned the first preferred embodiment those disclosed herein, therefore neitherly give unnecessary details in this again.In addition, only illustrate the first transistor 210 and transistor seconds 212 among Fig. 9, be all live width less than the situation of the element of 0.15 μ m in order to explanation major part on wafer.Yet when also having live width on the wafer greater than the element of 0.15 μ m during such as illustrated the 3rd transistor 214 of the first preferred embodiment, the personage Ying Ke that has the knack of this technology thinks easily according to Fig. 2 A to Fig. 8 and the status of implementation of the 3rd transistor 214 regions.
See also Fig. 9.The second preferred embodiment is different from the first preferred embodiment part and is: at the first transistor 210 interior formation first grid grooves 260, and after first grid groove 260 interior formation the first workfunction layers 270, form first the rete 280b that a polysilicon layer 280a and an available rotary coating mode form in substrate, for example a bottom anti-reflection layer, a silicon dangle, and key is lower than many silicon layers of 43%, a spin-on glasses layer, is sacrificed light absorbent layer, the DUO of an oxide-rich layer as being sold by U.S. Honeywell company
TMDeng, but be not limited to this.The first workfunction layers 270 is to satisfy the metal that the required work function of P transistor npn npn requires as previously mentioned, and it can be single layer structure or lamination layer structure.And when forming the first workfunction layers 270, can near the opening of first grid groove 260, form the overhang that indicates just like circle 272.In addition, form before the first workfunction layers 270, also optionally form just like front described intermediate layer (not shown).Polysilicon layer 280a and rete 280b be respectively as one first mask layer and one second mask layer, and consist of a sacrificial mask layer 280, and in other words, the sacrificial mask layer 280 that this preferred embodiment provides is a composite film.
It should be noted that and consider high temperature to the impact of the first workfunction layers 270, when forming polysilicon layer 280a, take the low temperature manufacture craft as better enforcement kenel.For instance, can utilize the long-pending manufacture craft (physical vapor deposition, PVD) in the lower physical vapor Shen of enforcement temperature to form polysilicon layer 280a.In addition, the thickness of polysilicon layer 280a is to be no more than 150 dusts as main.The existence of polysilicon layer 280a; can be after forming the first workfunction layers 270 with the stand-by period (Q-time) that forms before the rete 280b in protect the first workfunction layers 270, avoid 270 oxidations of the first workfunction layers and affect its work function.In addition, even in rotary coating manufacture craft patterning manufacture craft, occur bad and when needing heavy industrys (rework), polysilicon layer 280a can protect the first workfunction layers 270 when removing bad rete 280b as rete 280b.
See also Figure 10.Next, carry out an etch-back manufacture craft, utilize the etchant that is fit to, for example carbon monoxide (CO), oxygen (O
2) plasma, be preferably carbon monoxide and hydrogen bromide (HBr) etc., remove the partial sacrifice mask layer 280 in substrate 200 surfaces and the first grid groove 260.When utilizing oxygen plasma etch-back sacrificial mask layer 280, oxygen plasma may occur touch the first workfunction layers 270 and oxidation the first workfunction layers 270, and cause the disappearance of the usefulness drift (drift) of element.And in this preferred embodiment, can utilize polysilicon layer 280a as protective layer, avoid oxygen plasma to contact the first workfunction layers 270.After the etch-back manufacture craft, the surface of the sacrificial mask layer 280 in the first grid groove 260 is lower than the opening of first grid groove 260, that is is lower than the surface of ILD layer 242.At this moment, part the first workfunction layers 270 in substrate 200 surfaces and the first grid groove 260 is exposed.
Please continue to consult Figure 10.Utilize subsequently another etch-back manufacture craft, utilize the etchant that is fit to remove and be not sacrificed the first workfunction layers 270 that mask layer 280 covers.In other words, the etch-back manufacture craft removes the first workfunction layers 270 that is exposed in substrate 200 and the first grid groove 260; Further remove simultaneously the hard mask 250 of transistor seconds 212 tops.The more important thing is, this etch-back manufacture craft has removed the overhang 272 that first grid groove 260 opening parts form more simultaneously, therefore first grid groove 260 A/Fs that originally dwindled by overhang 272 can be returned back to original size.When this etch-back manufacture craft finishes, the U-shaped workfunction layers 274 that the 260 interior formation one of first grid groove are protected by sacrificial mask layer 280, the nominal grid 206 in the transistor seconds 212 then is exposed.
In addition, in a change type of this preferred embodiment, can be after substrate 200 form the first workfunction layers 270, the first workfunction layers 270 with transistor seconds 212 tops removes first.In this external change type, even can when removing the first workfunction layers 270, also hard mask 250 together be removed.And after the first workfunction layers 270 on removing transistor seconds 212, the side forms compound sacrificial mask layer 280 in substrate 200.Remove partial sacrifice mask layer 280 in substrate 200 surfaces and the first grid groove 260 by above-mentioned etch-back manufacture craft subsequently, make the surface of the sacrificial mask layer 280 in the first grid groove 260 be lower than the opening of first grid groove 260.And remove by another suitable etch-back manufacture craft and not to be sacrificed the first workfunction layers 270 and the overhang 272 that mask layer 280 covers, form U-shaped workfunction layers 274 as shown in figure 10.
See also Figure 11.Next, utilize a suitable etchant to remove the rete 280b of sacrificial mask layer 280.For instance, can utilize carbon monoxide or oxygen plasma to remove.Because polysilicon layer 208a can be used as the protective layer of the first workfunction layers 270, avoid oxygen plasma to contact the first workfunction layers 270 and cause oxidation, so this preferred embodiment more can adopt carbon monoxide or oxygen plasma as etchant.As previously mentioned, the etch-back manufacture craft of above-mentioned sacrificial mask layer 280, remove part the first workfunction layers 270, overhang 272 and hard mask 250 the etch-back manufacture craft, with remove above-mentioned three steps such as rete 280b and can be coordination and implement.
See also Figure 12.And after removing rete 280b, remove the nominal grid 206 of transistor seconds 212 by another suitable etching process, and in the second grid groove 262 of transistor seconds 212 interior formation shown in Figure 12.Because nominal grid 206 comprises polysilicon mostly, therefore when removing nominal grid 206, can remove simultaneously first grid groove 260 interior remaining polysilicon layer 280a.As previously mentioned, the A/F of second grid groove 262 is identical with the A/F of first grid groove 260.After this etching process finished, gate dielectric 204 was exposed to the bottom of second grid groove 262.And after forming second grid groove 262, can as form as described in the first preferred embodiment high dielectric constant gate dielectric layer, optionally form the intermediate layer, form the second workfunction layers, form steps such as filling metal level, planarization manufacture craft, repeat no more in this.
The manufacture method of the semiconductor element that metal gates is arranged that second preferred embodiment provides according to basis; formation one has the sacrificial mask layer 280 of polysilicon layer 280a; to improve the etch-back manufacture craft result of sacrificial mask layer 280; and in etch-back manufacture craft or heavy industry manufacture craft, protection the first workfunction layers 270 in the stand-by period, therefore can more improve the usefulness of the metal gates of final formation.
See also Figure 13 to Figure 17, Figure 13 to Figure 17 is the schematic diagram of one the 3rd preferred embodiment of the manufacture method of the semiconductor element with metal gates provided by the present invention.At first it should be noted that in the 3rd preferred embodiment, the element identical or corresponding with the first preferred embodiment, its material are selected directly to consult above-mentioned the first preferred embodiment those disclosed herein, therefore neitherly give unnecessary details in this again.In addition, Figure 13 to Figure 17 only illustrates that major part is all live width less than the situation of the element of 0.15 μ m on wafer.Yet when also having live width on the wafer greater than the element of 0.15 μ m during such as illustrated the 3rd transistor 214 of the first preferred embodiment, the personage Ying Ke that is familiar with this technology thinks easily according to Fig. 2 A to Fig. 8 and the status of implementation of the 3rd transistor region.
As shown in figure 13, this preferred embodiment at first provides a substrate 300, is formed with a plurality of STI 302 that electrical isolation is provided in the substrate 300, then is formed with a first transistor 310 and a transistor seconds 312 in the substrate 300.The first transistor 310 has one first conductive type, and 312 of transistor secondses have one second conductive type, and the first conductive type is opposite with the second conductive type.Between the first transistor 310 with opposite conductivity type formula and transistor seconds 312, then there is STI 302 that electrical isolation is provided in addition.In this preferred embodiment, the first conductive type is the P type; And the second conductive type is N-type, and vice versa but have the knack of the personage Ying Zhi of this technology.
See also Figure 13.The first transistor 310 respectively comprises a gate dielectric 304 and a nominal grid (not shown) with transistor seconds 312, and gate dielectric 304 can be a traditional silicon dioxide layer or a high dielectric constant gate dielectric layer.The first transistor 310 and transistor seconds 312 comprise respectively one the one LDD 320 and one the 2nd LDD 322, a clearance wall 326, and one first source/drain 330 and one second source/drain 332 and the metal silicide 336 that is formed at its surface in addition.And on the first transistor 310 and transistor seconds 312, sequentially form a CESL 340 and an ILD layer 342.The making step of said elements and material are selected, or even are known by providing effect of stress more to improve the personage that SEG method that electrical performance implements etc. is all this field in the semiconductor industry, therefore neitherly give unnecessary details in this again.
Please continue to consult Figure 13.After forming CESL 340 and ILD layer 342, remove CESL 340 and ILD layer 342 by a planarization manufacture craft, until expose the nominal grid of the first transistor 310 and transistor seconds 312.Next, utilize an etching process that is fit to remove the nominal grid of the first transistor 310 and transistor seconds 312, respectively at the first transistor 310 and transistor seconds 312 interior formation one first grid groove 360 and second grid grooves 362.After this etching process finished, gate dielectric 304 was exposed to the bottom of first grid groove 360 and second grid groove 362.As previously mentioned, this preferred embodiment can be integrated with first gate dielectric manufacture craft, and this moment, gate dielectric 304 comprised a high dielectric constant gate dielectric layer, and material options can be consulted the first preferred embodiment.In addition, this preferred embodiment also can be integrated with rear gate dielectric manufacture craft, then gate dielectric 304 can be first a traditional silicon dioxide layer, and after forming first grid groove 360 and second grid groove 362, remove the gate dielectric 304 that is exposed to first grid groove 360 and second grid groove 362 bottoms, form subsequently a high dielectric constant gate dielectric layer (not shown), it can comprise above-mentioned material.
Please still consult Figure 13.Subsequently, in substrate 300, form one first workfunction layers 370, in addition before forming the first workfunction layers 370, can in each first grid groove 360 and second grid groove 362, form again an intermediate layer 308 according to product needed, for example a barrier layer, a stressor layers, a work function are adjusted metal level or its combination, and are not limited to this.And after forming the first workfunction layers 370, remove the first workfunction layers 370 in the second grid groove 362 by a patterning manufacture craft, the first workfunction layers 370 mainly is present in the first grid groove 360.It should be noted that in addition when forming the first workfunction layers 370, can near the opening of first grid groove 360, form the overhang that indicates just like circle 372.Can be observed significantly by Figure 13, because the A/F of first grid groove 360 is less, therefore the overhang 372 of the first workfunction layers 370 is very obvious on the impact of the A/F of first grid groove 360, and namely overhang 372 has been dwindled the A/F of first grid groove 360 more.Because the first transistor 310 is a P transistor npn npn, and the work function of its metal gates is between 4.8eV and 5.2eV, therefore the first workfunction layers 370 of providing of this preferred embodiment can be consulted the first preferred embodiment, but also is not limited to any suitable metal material.And the first workfunction layers 370 can be a single layer structure or lamination layer structure.
See also Figure 14.After the first workfunction layers 370 to be formed, in substrate 300, form a sacrificial mask layer 380.Sacrificial mask layer 380 can be one and fills out the good rete of hole ability, and for example the bottom anti-reflection layer, a polysilicon layer, the silicon that form of the available rotary coating mode key that dangles is lower than 43% many silicon layers, a spin-on glasses layer, and sacrifices light absorbent layer, the DUO of an oxide-rich layer as being sold by U.S. Honeywell company
TMDeng, but be not limited to this.As previously mentioned, sacrificial mask layer 380 can be a single rete as shown in figure 14, but it also can be a composite film.Sacrificial mask layer 380 has been inserted within first grid groove 360 and the second grid groove 362.And after forming sacrificial mask layer 380, more in substrate 300, form a patterning photoresist 382.As shown in figure 14, patterning photoresist 382 exposes the first transistor 310, especially the sacrificial mask layer 380 in the first grid groove 360.
See also Figure 15.Next, carry out an etch-back manufacture craft, utilize the etchant that is fit to, etch exposed partial sacrifice mask layer 380 out.After the etch-back manufacture craft, the surface of sacrificial mask layer 380 is lower than the opening of first grid groove 360, that is is lower than the surface of ILD layer 342.At this moment, part the first workfunction layers 370 in substrate 300 surfaces and the first grid groove 360 is exposed.In this etch-back manufacture craft, the sacrificial mask layer 380 in the second grid groove 362 is protected by patterning photoresist 382, therefore is not subjected to the impact of etch-back manufacture craft.In other words, the sacrificial mask layer 380 in the second grid groove 362 still can protect in follow-up manufacture craft relaying continuation of insurance the gate dielectric 304 of second grid groove 362 bottoms.
See also Figure 16.Utilize subsequently another etch-back manufacture craft, utilize the etchant that is fit to, remove and be not sacrificed the first workfunction layers 370 and intermediate layer 308 that mask layer 380 covers.The more important thing is, this etch-back manufacture craft has removed the overhang 372 that first grid groove 360 opening parts form more simultaneously, therefore first grid groove 360 A/Fs that originally dwindled by overhang 372 can be returned back to original size.When this etch-back manufacture craft finished, the 362 interior formation one of first grid groove were by the U-shaped workfunction layers 374 of 380 covering protection of sacrificial mask layer.
See also Figure 17.Afterwards, utilize a suitable etchant, for example an etchant that comprises oxygen, hydrogen, nitrogen removes patterning photoresist 382 and sacrificial mask layer 380.It should be noted that in addition sacrificial mask layer 380 the etch-back manufacture craft, remove part the first workfunction layers 370 and overhang 372 the etch-back manufacture craft, can be coordination with above-mentioned three steps such as removing sacrificial mask layer 380 and implement.After removing patterning photoresist 382 and sacrificial mask layer 380, U-shaped workfunction layers 374 is exposed in the first grid groove 360, and gate dielectric 304 then is exposed to the bottom of second grid groove 362.Afterwards, can as form as described in the first preferred embodiment high dielectric constant gate dielectric layer, optionally form the intermediate layer, form the second workfunction layers, form steps such as filling metal level, planarization manufacture craft, repeat no more in this.
In this preferred embodiment, because the shape facility of U-shaped workfunction layers 374, the first half opening of first grid groove 360 can be kept original size, and effectively reduce the depth-to-width ratio (aspect ratio) of first grid groove 360, therefore the second workfunction layers can be inserted smoothly with the filling metal level, slit (seam) occurs when being avoided filling up first grid groove 360, guarantees the reliability of the first transistor 310.
It should be noted that in addition; owing to spreading all over electrically opposite on the single wafer; each element that the live width size is different; and these a plurality of size ranges are little to 30nm; greatly to more than the 5 μ m; even micro loading effect occurs in the etching process to be caused the larger element area of live width to be affected performance by over etching causing damage; and avoid electrically opposite element area etched and have influence on gate dielectric; this preferred embodiment can be after forming sacrificial mask layer 380; form patterning photoresist 382 in the reach the standard grade element region of the element region that is wider than 0.15 μ m and tool opposite conductivity type formula of substrate, with these a plurality of elements of protection when the etch-back sacrificial mask layer 380.Therefore, even the gate trench that conductive type is opposite, size is different forms simultaneously, it need U-shaped workfunction layers 374 parts of formation be the etching target of etch-back manufacture craft that this preferred embodiment still can be guaranteed only to have, and does not have influence on other element areas.
See also in addition Figure 18, Figure 18 is the schematic diagram of a change type of the 3rd preferred embodiment.Sacrificial mask layer 380 in this 3rd preferred embodiment can such as Figure 14 to Figure 16 shows that a single layer structure, can be a lamination layer structure also as shown in figure 18.This change type is after first grid groove 360 interior formation the first workfunction layers 370, form first the rete 380b that a polysilicon layer 380a and an available rotary coating mode form in substrate, for example a bottom anti-reflection layer, a silicon dangle, and key is lower than many silicon layers of 43%, a spin-on glasses layer, is sacrificed light absorbent layer, the DUO of an oxide-rich layer as being sold by U.S. Honeywell company
TMDeng, but be not limited to this.Polysilicon layer 380a and rete 380b be respectively as one first mask layer and one second mask layer, and consist of the sacrificial mask layer 380 of a compound kenel.
As previously mentioned, consider high temperature to the impact of the first workfunction layers 370, when forming polysilicon layer 380a, take the low temperature manufacture craft as better enforcement kenel.For instance, can utilize the long-pending manufacture craft in the lower physical vapor Shen of enforcement temperature to form polysilicon layer 380a.In addition, the thickness of polysilicon layer 380a is to be no more than 150 dusts as main.The existence of polysilicon layer 380a; can be after forming the first workfunction layers 370 with the stand-by period (Q-time) that forms before the rete 380b in protect the first workfunction layers 370, avoid protecting the first workfunction layers 370 and touch oxygen and affect its work function.In addition, even in rotary coating manufacture craft patterning manufacture craft, occur bad and when needing heavy industry, polysilicon layer 380a can protect the first workfunction layers 370 when removing bad rete 380b as rete 380b.
According to this change type; formation one has the sacrificial mask layer 380 of polysilicon layer 380a; improving the etch-back manufacture craft result of sacrificial mask layer 380, therefore and in etch-back manufacture craft or heavy industry manufacture craft, protection the first workfunction layers 370 can more be improved the usefulness of the metal gates of final formation in the stand-by period.
According to the manufacture method with semiconductor element of metal gates provided by the present invention; utilize this sacrificial mask layer that does not fill up this first grid groove to protect this interior first workfunction layers of this first grid groove; to remove smoothly non-essential this first workfunction layers in this substrate; the more important thing is, remove near these a plurality of overhang of first grid groove opening.Therefore, the follow-up rete of wanting to insert in this first grid groove can successfully be inserted in the first grid groove such as the second workfunction layers and filling metal level, avoids the formation in space and can avoid the space to the negative effect of semiconductor element electric.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (33)
1. manufacture method with semiconductor element of metal gates includes:
One substrate is provided, this substrate surface is formed with a first transistor and the first transistor seconds, this the first transistor has one first conductive type and this transistor seconds has one second conductive type, this first conductive type is opposite with this second conductive type, and is formed with a first grid groove (gate trench) in this first transistor;
In this first grid groove, form one first workfunction metal (work function metal) layer;
In this first grid groove, form a sacrificial mask layer (sacrificial masking layer);
Remove this sacrificial mask layer of part, to expose this first workfunction layers of part;
Remove this first workfunction layers of part of exposure, in this first grid groove of part, to form a U-shaped workfunction layers; And
Remove this sacrificial mask layer.
2. manufacture method as claimed in claim 1, wherein this sacrificial mask layer is a composite film, and this composite film comprises the first mask layer and the second mask layer.
3. manufacture method as claimed in claim 2 also comprises an etch-back manufacture craft, in order to remove this partial sacrifice mask layer, makes this sacrificial mask layer not fill up this first grid groove.
4. manufacture method as claimed in claim 3 also comprises an etching process, in order to removing this first mask layer of this sacrificial mask layer, and stays this second mask layer.
5. manufacture method as claimed in claim 1 also comprises an etch-back manufacture craft, in order to remove this partial sacrifice mask layer, makes this sacrificial mask layer not fill up this first grid groove.
6. manufacture method as claimed in claim 1 wherein also comprises the second grid groove in this transistor seconds, and the A/F of this second grid groove is identical with the A/F of this first grid groove.
7. manufacture method as claimed in claim 6, wherein this second grid groove and this first grid groove form simultaneously, and this sacrificial mask layer fills up this second grid groove.
8. manufacture method as claimed in claim 7, before removing this partial sacrifice mask layer, also be contained in and form one first patterning photoresist on this sacrificial mask layer, and this first patterning photoresist exposes this sacrificial mask layer in this first grid groove.
9. manufacture method as claimed in claim 6 also comprises following steps:
In this substrate, form a hard mask, this transistor seconds of covering protection when forming this first grid groove;
Remove simultaneously this part the first workfunction layers and this hard mask of exposure; And
In this transistor seconds, form this second grid groove.
10. method as claimed in claim 9, wherein this first workfunction layers also comprises at least one overhang, and this overhang and part the first workfunction layers that exposes this and this hard mask together by the time remove.
11. manufacture method as claimed in claim 6 also comprises one and sequentially form the step that one second workfunction layers and is filled metal (filling metal) layer in this first grid groove and this second grid groove.
12. manufacture method as claimed in claim 11, wherein this second workfunction layers in this first grid groove comprises a shape of reverse omega shape.
13. manufacture method as claimed in claim 1, also comprise one the 3rd transistor, be arranged in this substrate, when wherein forming this first grid groove, in the 3rd transistor, form simultaneously one the 3rd gate trench, and the A/F of the 3rd gate trench is greater than the A/F of this first grid groove.
14. manufacture method as claimed in claim 13 also comprises following steps, is carried out to remove this partial sacrifice mask layer to expose before this part first workfunction layers:
In the 3rd gate trench, form this sacrificial mask layer; And
Form one second patterning photoresist in this substrate, this second patterning photoresist covers the 3rd transistor and exposes this first transistor.
15. the manufacture method with semiconductor element of metal gates includes:
One substrate is provided, this substrate surface is formed with a first transistor and a transistor seconds, be formed with a first grid groove in this first transistor, and be formed with a second grid groove in this transistor seconds, and the A/F of this second grid groove is greater than the A/F of this first grid groove;
In this first grid groove, form one first workfunction layers;
In this first grid groove and this second grid groove, form a sacrificial mask layer;
Form a patterning photoresist in this substrate, this patterning photoresist covers this transistor seconds and exposes this interior sacrificial mask layer of this first grid groove;
Remove this sacrificial mask layer of part, to expose this first workfunction layers of part; And
Remove this first workfunction layers of part of exposure, in this first grid groove, to form a U-shaped workfunction layers.
16. manufacture method as claimed in claim 15, wherein this sacrificial mask layer is a composite film, and this composite film comprises one first mask layer and one second mask layer.
17. manufacture method as claimed in claim 16 also comprises an etch-back manufacture craft, in order to remove this partial sacrifice mask layer, makes this sacrificial mask layer not fill up this first grid groove.
18. manufacture method as claimed in claim 17 also comprises an etching process, in order to removing this first mask layer of this sacrificial mask layer, and stays this second mask layer.
19. manufacture method as claimed in claim 15 also comprises an etch-back manufacture craft, in order to remove this partial sacrifice mask layer.
20. manufacture method as claimed in claim 15 also comprises a step that removes this sacrificial mask layer, is carried out to form after this U-shaped workfunction layers.
21. manufacture method as claimed in claim 15, also comprise one the 3rd transistor, be arranged in this substrate, this first transistor and this transistor seconds have the first conductive type, and the 3rd transistor has the second conductive type, and this first conductive type is opposite with this second conductive type.
22. manufacture method as claimed in claim 21, wherein the 3rd transistor also comprises the 3rd gate trench, and the 3rd gate trench and this first grid groove and this second grid groove form simultaneously.
23. manufacture method as claimed in claim 22, wherein the A/F of the 3rd gate trench is identical with the A/F that this first grid groove comprises, and this sacrificial mask layer fills up the 3rd gate trench.
24. manufacture method as claimed in claim 23, wherein this patterning photoresist also covers this sacrificial mask layer in the 3rd gate trench.
25. manufacture method as claimed in claim 22 also comprises one and sequentially form the step that one second workfunction layers and is filled metal level in this first grid groove, this second grid groove and the 3rd gate trench.
26. manufacture method as claimed in claim 25, wherein this second workfunction layers in this first grid groove comprises a shape of reverse omega shape.
27. the semiconductor element with metal gates includes:
Substrate has first grid groove and second grid groove;
Gate dielectric is arranged at respectively in this first grid groove and this second grid groove;
The first workfunction layers is arranged on this gate dielectric in this first grid groove;
The second workfunction layers is arranged at respectively in this second grid groove and this first grid groove, and this second workfunction layers in this first grid groove comprises a shape of reverse omega; And
Fill metal level, be arranged on this first workfunction layers and this second workfunction layers.
28. semiconductor element as claimed in claim 27, wherein this gate dielectric is a high-k (high-K) gate dielectric.
29. semiconductor element as claimed in claim 28, wherein this high dielectric constant gate dielectric layer comprises a U-shaped shape or yi word pattern shape.
30. semiconductor element as claimed in claim 27, also comprise an intermediate layer (inter layer), be arranged between this first workfunction layers and this gate dielectric, this intermediate layer comprises barrier layer (barrier layer), a stressor layers (strained stress layer), work function adjustment metal level (tuning metal layer) or its combination.
31. semiconductor element as claimed in claim 30, wherein this intermediate layer comprises a U-shaped shape or yi word pattern shape.
32. semiconductor element as claimed in claim 27, wherein this first workfunction layers comprises a U word shape.
33. semiconductor element as claimed in claim 27, wherein this second workfunction layers in this first grid groove is arranged between this first workfunction layers and this filling metal level.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795394A (en) * | 2014-01-22 | 2015-07-22 | 联华电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN105047613A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Metal gate forming method |
| CN105280486A (en) * | 2014-07-23 | 2016-01-27 | 联华电子股份有限公司 | Manufacture method of metallic gate structure |
| CN105552116A (en) * | 2014-10-30 | 2016-05-04 | 联华电子股份有限公司 | Metal gate structure and formation method thereof |
| CN105990445A (en) * | 2015-03-23 | 2016-10-05 | 三星电子株式会社 | Semiconductor device and method for fabricating the same |
| CN106298656A (en) * | 2015-05-20 | 2017-01-04 | 联华电子股份有限公司 | Semiconductor device manufacturing method |
| CN106910737A (en) * | 2015-12-23 | 2017-06-30 | 联华电子股份有限公司 | Semiconductor element and forming method thereof |
| CN107731929A (en) * | 2017-09-28 | 2018-02-23 | 信利（惠州）智能显示有限公司 | Thin film transistor (TFT) and preparation method thereof and array base palte and display device |
| CN110504161A (en) * | 2018-05-16 | 2019-11-26 | 力智电子股份有限公司 | Trench-gate metal-oxide half field effect transistor and its manufacturing method |
| CN110828377A (en) * | 2018-08-08 | 2020-02-21 | 联华电子股份有限公司 | Semiconductor element with asymmetric work function metal layer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101438389A (en) * | 2006-05-09 | 2009-05-20 | 英特尔公司 | Recessed workfunction metal in CMOS transistor gates |
| CN101789368A (en) * | 2008-09-12 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacture method thereof |
| CN101924027A (en) * | 2009-06-12 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Metal gate transistor, integrated circuits, systems, and fabrication methods thereof |
| US20110104880A1 (en) * | 2009-10-30 | 2011-05-05 | Jens Heinrich | Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition |
-
2011
- 2011-06-27 CN CN201110174511.1A patent/CN102856255B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101438389A (en) * | 2006-05-09 | 2009-05-20 | 英特尔公司 | Recessed workfunction metal in CMOS transistor gates |
| CN101789368A (en) * | 2008-09-12 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacture method thereof |
| CN101924027A (en) * | 2009-06-12 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Metal gate transistor, integrated circuits, systems, and fabrication methods thereof |
| US20110104880A1 (en) * | 2009-10-30 | 2011-05-05 | Jens Heinrich | Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795394B (en) * | 2014-01-22 | 2019-01-08 | 联华电子股份有限公司 | Semiconductor structure and its production method |
| CN104795394A (en) * | 2014-01-22 | 2015-07-22 | 联华电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN105280486A (en) * | 2014-07-23 | 2016-01-27 | 联华电子股份有限公司 | Manufacture method of metallic gate structure |
| CN105552116A (en) * | 2014-10-30 | 2016-05-04 | 联华电子股份有限公司 | Metal gate structure and formation method thereof |
| CN105990445A (en) * | 2015-03-23 | 2016-10-05 | 三星电子株式会社 | Semiconductor device and method for fabricating the same |
| CN106298656A (en) * | 2015-05-20 | 2017-01-04 | 联华电子股份有限公司 | Semiconductor device manufacturing method |
| CN105047613A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Metal gate forming method |
| CN106910737A (en) * | 2015-12-23 | 2017-06-30 | 联华电子股份有限公司 | Semiconductor element and forming method thereof |
| CN106910737B (en) * | 2015-12-23 | 2021-01-15 | 联华电子股份有限公司 | Semiconductor device and method for forming the same |
| CN107731929A (en) * | 2017-09-28 | 2018-02-23 | 信利（惠州）智能显示有限公司 | Thin film transistor (TFT) and preparation method thereof and array base palte and display device |
| CN110504161A (en) * | 2018-05-16 | 2019-11-26 | 力智电子股份有限公司 | Trench-gate metal-oxide half field effect transistor and its manufacturing method |
| CN110504161B (en) * | 2018-05-16 | 2024-05-07 | 力智电子股份有限公司 | Trench gate metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN110828377A (en) * | 2018-08-08 | 2020-02-21 | 联华电子股份有限公司 | Semiconductor element with asymmetric work function metal layer |
| CN110828377B (en) * | 2018-08-08 | 2022-06-21 | 联华电子股份有限公司 | Semiconductor element with asymmetric work function metal layer |
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