CN102856204B - Transistor and forming method thereof - Google Patents
Transistor and forming method thereof Download PDFInfo
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- CN102856204B CN102856204B CN201110180768.8A CN201110180768A CN102856204B CN 102856204 B CN102856204 B CN 102856204B CN 201110180768 A CN201110180768 A CN 201110180768A CN 102856204 B CN102856204 B CN 102856204B
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Abstract
A formation method for MOS transistor, comprising: provide Semiconductor substrate; Form dielectric layer at described semiconductor substrate surface, described dielectric layer has opening, described opening exposing semiconductor substrate, and described opening both sides form active, drain region; Also comprise: form semiconductor packed layer in described open bottom; Form the grid structure of filling full described opening.The present invention also provides the MOS transistor formed by said method, and the formation method of the CMOS transistor of employing said method, and corresponding CMOS transistor, can be reduced the threshold voltage of PMOS transistor by the present invention.
Description
Technical field
The present invention relates to semiconductor applications, particularly transistor and forming method thereof.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more less.Under MOS transistor characteristic size constantly reduces situation, in order to reduce the parasitic capacitance of MOS transistor grid structure, improve device speed, the metal gate structure be made up of high K gate dielectric layer and metal gate electrode layer is introduced in MOS transistor.
For avoiding the metal material of metal gates on the impact of other structures of transistor, the gate stack structure of described metal gates and high K gate dielectric layer usually adopts grid to substitute (replacementgate) technique and makes.In the process, before source-drain area injects, first form the sacrificial gate be made up of polysilicon in gate location to be formed, with described sacrificial gate for mask forms source, the drain region being positioned at described sacrificial gate both sides.And after formation source-drain area, described sacrificial gate can be removed and form gate openings in the position of sacrificial gate, afterwards, then in described gate openings, fill high K gate dielectric layer and metal gates successively.Because metal gates makes after source-drain area has injected again, this makes the quantity of subsequent technique be reduced, and avoids the problem that metal material is unsuitable for carrying out high-temperature process.
In actual applications, PMOS transistor is not identical with the device property of nmos pass transistor, and therefore its grid structure needs to design based on different threshold voltage demands.Therefore, when adopting described grid structure alternative techniques to make CMOS transistor, need the grid structure forming PMOS transistor and nmos pass transistor respectively, namely, CMOS transistor manufacture craft needs to carry out twice grid structure and replaces technique, to realize the replacement of sacrificial gate.
US Patent No. 6171910 discloses a kind of method adopting grid structure to replace technique making CMOS transistor.Referring to figs. 1 to Fig. 5, show the part run of this manufacture method.
As shown in Figure 1, Semiconductor substrate 101 is provided, PMOS district 103 in described Semiconductor substrate 101 forms sacrificial gate electrode structure 107 and source-drain area respectively with nmos area 105, and described sacrificial gate electrode structure comprises pseudo-gate dielectric layer 109, sacrificial gate 111 and is positioned at the hard mask layer 113 on sacrificial gate 111 surface.
As shown in Figure 2, form the dielectric protection layer 115 of overlies gate structure 107 on pseudo-gate dielectric layer 109 surface, dielectric protection layer 115 described in planarization, until expose sacrificial gate 111 surface.
As shown in Figure 3; form the first photoresist layer 117, graphically described first photoresist layer 117 in described dielectric protection layer 115 and sacrificial gate 111 surface, expose the sacrificial gate surface in PMOS district 103; afterwards, described sacrificial gate is removed to form first grid structural openings 119.
As shown in Figure 4, in described first grid structural openings 119, grid dielectric material and metal gate structure material is filled; Afterwards, carry out planarization, the metal gate structure material that described first grid structural openings 119 retains forms the grid structure of PMOS transistor, and grid dielectric material forms gate dielectric layer; Meanwhile, described planarization makes sacrificial gate 111 surface on nmos area 105 in sacrificial gate electrode structure 107 expose.
As shown in Figure 5, the formation process of PMOS transistor grid structure is next carried out being similar to make the grid structure of nmos pass transistor.
But the threshold voltage of the CMOS transistor formed by said method is larger, a kind of method reducing threshold voltage is, between gate dielectric layer and gate electrode layer, form function metal level, but the threshold voltage of the CMOS transistor formed by this method is still little not.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistor and forming method thereof, reduces the threshold voltage of transistor.
For solving the problem, the invention provides a kind of formation method of MOS transistor, comprising: Semiconductor substrate is provided; Form dielectric layer at described semiconductor substrate surface, described dielectric layer has opening, described opening exposing semiconductor substrate, and described opening both sides form active, drain region; Semiconductor packed layer is formed in described open bottom; Form the grid structure of filling full described opening.
Alternatively, form the step with the dielectric layer of opening at described semiconductor substrate surface to comprise: form grid structure at described semiconductor substrate surface; With described grid structure for mask, Semiconductor substrate is adulterated, form source, drain region; Form the dielectric layer covering described grid structure, and planarization is carried out to described dielectric layer, until expose described grid structure; Remove described grid structure, form the dielectric layer with opening.
Alternatively, described MOS transistor is PMOS transistor, and the material of described semiconductor packed layer is N-shaped Si
xge
y.
Alternatively, described N-shaped Si
xge
yin, the scope of x: y is 50-90: 50-10.
Alternatively, described Si
xge
ysi
55ge
45.
Alternatively, the thickness of described semiconductor packed layer is less than 10nm.
Alternatively, also comprise after forming described semiconductor packed layer, annealing in process or quick high-temp thermal oxidation are carried out to Semiconductor substrate.
Alternatively, also comprise after forming described semiconductor packed layer, in inert gas environment, in the annealing temperature of 600-800 degree Celsius, annealing in process is carried out to Semiconductor substrate.
Alternatively, described annealing temperature is 650-750 degree Celsius, and anneal duration is 30-60 minute.
Alternatively, also comprise after forming described semiconductor packed layer, in the annealing temperature of 950-1050 degree Celsius, carry out laser annealing, anneal duration is 0.1-0.5 second.
Alternatively, in the process forming semiconductor packed layer, semiconductor packed layer surface has oxide layer and is formed, and adopts diluted hydrofluoric acid to remove the oxide layer formed.
Alternatively, the step forming the grid structure of filling full described opening comprises: form high-k dielectric layer on packed layer surface, and carry out annealing in process to described high-k dielectric layer.
Alternatively, the temperature of described annealing in process is 600-700 degree Celsius, and anneal duration is 1 hour.
Correspondingly, the present invention also provides the MOS transistor formed any one of said method, comprising: Semiconductor substrate, and described semiconductor substrate surface is formed with the dielectric layer with opening; Also comprise: the semiconductor packed layer being positioned at described open bottom; Fill the grid structure of full described opening, be positioned at the source of described grid structure semiconductor substrates on two sides, drain region.
Correspondingly, the present invention also provides a kind of CMOS transistor formation method, comprising: provide Semiconductor substrate, and described Semiconductor substrate comprises NMOS area and PMOS area, and isolates the isolation structure of adjacent NMOS area and PMOS area; Form dielectric layer at described semiconductor substrate surface, described dielectric layer has the opening exposing and be positioned at the Semiconductor substrate of PMOS area, and described opening both sides form active, drain region; N-shaped packed layer is formed in described open bottom; The grid structure of filling full described opening is formed on described N-shaped packed layer surface.
Alternatively, form the grid structure of filling full described opening on described N-shaped packed layer surface to comprise: form opening in described NMOS area, described opening exposes the Semiconductor substrate being positioned at NMOS area; Exposing the surface being positioned at the opening of the Semiconductor substrate of NMOS area, and exposing the surface formation high-k dielectric layer being positioned at the opening of the Semiconductor substrate of PMOS area, and annealing in process is being carried out to described high-k dielectric layer.
Correspondingly, the present invention also provides the CMOS transistor formed by said method, comprising: Semiconductor substrate, and described Semiconductor substrate comprises NMOS area and PMOS area, and isolates the isolation structure of adjacent NMOS area and PMOS area; Be positioned at the dielectric layer of described semiconductor substrate surface, described dielectric layer has the opening exposing and be positioned at the Semiconductor substrate of PMOS area; Be positioned at the N-shaped packed layer of described open bottom; Fill the grid structure of full described opening, be positioned at the source of described grid structure semiconductor substrates on two sides, drain region.
Alternatively, also comprise: expose the opening being positioned at the Semiconductor substrate of NMOS area, fill the grid structure of full described opening, be positioned at the source of described grid structure both sides, drain region.
Compared with prior art, the present invention has the following advantages: the MOS transistor formation method that embodiments of the invention provide forms semiconductor packed layer in the bottom of grid structure, described semiconductor packed layer produces stress to channel region, thus has an impact to the threshold voltage of MOS transistor;
Have semiconductor packed layer bottom the grid structure of the MOS transistor that embodiments of the invention provide, described semiconductor packed layer produces stress to channel region, thus has an impact to the threshold voltage of MOS transistor;
Further, in an embodiment of the present invention, semiconductor packed layer is formed on surface, the channel region of PMOS transistor, the material of described semiconductor packed layer is the SiGe of N-shaped, described semiconductor packed layer produces compression to channel region, thus improve the hole mobility of PMOS transistor channel region, the threshold voltage of PMOS transistor is reduced.
Further, embodiments of the invention also provide CMOS transistor formation method, described method forms semiconductor packed layer in the bottom of the grid structure of PMOS transistor, and described semiconductor packed layer produces stress to channel region, thus has an impact to the threshold voltage of MOS transistor;
Further, embodiments of the invention also provide CMOS transistor, the bottom of the grid structure of the PMOS transistor in described CMOS transistor has semiconductor packed layer, and described semiconductor packed layer produces stress to channel region, thus the threshold voltage of pair pmos transistor has an impact.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the generalized section of the formation method of existing CMOS transistor;
Fig. 6 is the schematic flow sheet of the formation method of the MOS transistor that embodiments of the invention provide;
Fig. 7 to Figure 10 is the generalized section of the formation method of the MOS transistor that embodiments of the invention provide;
Figure 11 is the structural representation of the CMOS transistor that embodiments of the invention provide.
Embodiment
Learnt by background technology, the threshold voltage of existing MOS transistor is little not, inventor studies for the problems referred to above, proposes a kind of MOS transistor and forming method thereof in the present invention, and MOS transistor provided by the present invention and forming method thereof can reduce the threshold voltage of MOS transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with drawings and Examples.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
It should be noted that provided by the present invention provided MOS transistor and forming method thereof is applicable to PMOS transistor and nmos pass transistor simultaneously.When forming PMOS transistor and nmos pass transistor, just the material of described semiconductor packed layer is different.In an embodiment of the present invention for PMOS transistor, the present invention is set forth.
Fig. 6 is the schematic flow sheet of the formation method of the MOS transistor that one embodiment of the present of invention provide, and comprising:
Step S101, provides Semiconductor substrate;
Step S102, form dielectric layer at described semiconductor substrate surface, described dielectric layer has opening, described opening exposing semiconductor substrate, and described opening both sides form active, drain region;
Step S103, forms semiconductor packed layer in described open bottom;
Step S104, forms the grid structure of filling full described opening.
With reference to figure 7, provide Semiconductor substrate 300.
Described Semiconductor substrate 300 can be the Semiconductor substrate that any support forms transistor.
As an embodiment, described Semiconductor substrate 300 is silicon substrate.
With reference to figure 6 and Fig. 8, perform step S102, form dielectric layer 310 on described Semiconductor substrate 300 surface, described dielectric layer has opening 320, described opening 320 exposing semiconductor substrate 300, and described opening 320 both sides form active, drain region.
Described opening 320 for forming grid structure in subsequent technique, the formation process of described opening can utilize replacement gate process, be specially: form replacement gate structure on described Semiconductor substrate 300 surface, described replacement gate structure comprises the alternative gate dielectric layer, alternative gate electrode layer and the side wall that are formed successively, and with described replacement gate structure for mask, to described Semiconductor substrate 300 dopant implant ion, and annealing activates described Doped ions, forms source, drain region; Then the dielectric layer covering described replacement gate structure and Semiconductor substrate 300 is formed; Then planarization is carried out to formed dielectric layer, until expose described replacement gate structure; Remove alternative gate dielectric layer, alternative gate electrode layer again, form opening 320, described opening 320 exposing semiconductor substrate 300.In the present embodiment because be formed PMOS transistor, so described in be doped to P type doping.
In other embodiments of the invention, described side wall can also be removed simultaneously.
With reference to figure 6 and Fig. 9, perform step S103, bottom described opening 320, form semiconductor packed layer 330;
Described semiconductor packed layer 330 is stressor layers, because the position of described opening 320 corresponds to the channel region between source, drain region, so the semiconductor packed layer 330 pairs of channel regions be formed in bottom opening 320 produce stress, thus can have an impact to the lattice arrangement of channel region.Pair pmos transistor, described semiconductor packed layer 330 pairs of channel regions produce compression, improve the mobility in hole, reduce threshold voltage.
Described semiconductor packed layer 330 is crystalline state, described crystalline state can be formed by adjusting process parameter in the technique forming described semiconductor packed layer 330, also can, after the described semiconductor packed layer 330 of formation, described semiconductor packed layer 330 crystallization be made to form crystal by annealing.
Specifically in the present embodiment, MOS transistor to be formed is PMOS transistor, and accordingly, the material of described semiconductor packed layer 330 is N-shaped Si
xge
y, N-shaped Si
xge
ycompression can be produced to channel region, improve the mobility of hole in channel region.
In the present embodiment, the formation process of described semiconductor packed layer 330 is selectivity depositing operation, and described semiconductor packed layer 330 can only be formed in bottom opening 320, and can not be formed in the sidewall of opening 320 and the surface of dielectric layer 310.Be 600-700 degree Celsius in temperature, when air pressure is 0.2Torr, the gas passed into comprises SiH
4, GeH
4, AsH
4and H
2, wherein, SiH
4flow be 200sccm, AsH
4flow be 50-150sccm, H
2flow be 50slm, the N-shaped Si formed
xge
ybe positioned at the surface of the Semiconductor substrate 300 that opening 320 exposes.
Described N-shaped Si
xge
yin, if the value of x: y is excessive, then make produced understressing because the content of germanium is too small, large not in the impact of the mobility of channel region on hole, thus the amount that threshold voltage is reduced is smaller; If the value of x: y is too small, then causes lattice between semiconductor packed layer 330 with Semiconductor substrate 300 not mate because the content of germanium is excessive, and therefore cause dislocation.In the present embodiment, described N-shaped Si
xge
yin, the span of x is the span of 50-90, y is 10-50, so the scope of x: y is 50-90: 50-10, the value of such as x is the value of 55, y is 45.
In the present embodiment, the thickness of described semiconductor packed layer 330 is less than 10nm, such as 5nm, 6nm, 7nm or 8nm.At N-shaped Si
xge
ywhen the value of middle x and y is determined, the thickness of described semiconductor packed layer 330 is relevant to the compression being applied to channel region, but, thickness is excessive, lattice between described semiconductor packed layer 330 and Semiconductor substrate 300 not matching degree is also larger, bring negative effect may in addition follow-up grid structure manufacture craft, so in the present embodiment, the thickness of described semiconductor packed layer 330 is less than 10nm.
In the present embodiment, after the described semiconductor packed layer 330 of formation, annealing in process or high temperature oxidation process are carried out to Semiconductor substrate 300, described annealing in process or high-temperature thermal oxidation process (RTO) contribute to germanium diffusion, and germanium diffuses to the effect contributing to improving compression between semiconductor packed layer 330 and Semiconductor substrate 300 surface.
As an embodiment, described annealing in process is in inert gas environment, and annealing temperature is 600-800 degree Celsius; Such as: described annealing temperature is 650-750 degree Celsius, anneal duration is 30-60 minute.
In other embodiments, described annealing in process can also adopt laser annealing, and annealing temperature is 950-1050 degree Celsius, and anneal duration is 0.1-0.5 second.
It should be noted that, in the process forming semiconductor packed layer, semiconductor packed layer surface has oxide layer and is formed, and in one embodiment, adopts diluted hydrofluoric acid to remove the oxide layer formed.
In other embodiments of the invention, cover layer (not shown) can also be formed on described semiconductor packed layer 330 surface, as an embodiment, described tectal material is silicon, the double-decker be made up of cover layer and semiconductor packed layer 330 can improve the stress influence of semiconductor packed layer 330 pairs of channel regions further, to reduce threshold voltage further.
With reference to figure 6 and Figure 10, perform step S104, form the grid structure of filling full described opening.
Described grid structure can be the double-decker comprising gate dielectric layer and metal gate, and wherein gate dielectric layer material is high K medium material; Or be the sandwich construction comprising gate dielectric layer, function metal level (functionmetal), diffusion impervious layer, metal gate.
In the present embodiment, exemplary illustrated is done with the double-decker comprising high-k dielectric layer and metal gate, concrete formation process is: first form high-k dielectric layer on semiconductor packed layer 330 surface, and carry out annealing in process, the temperature of described annealing in process is 600-700 degree Celsius, and anneal duration is 1 hour.In order to avoid the region at the turning at the metal gate near follow-up formation forms leakage current, in optional embodiment of the present invention, high-k dielectric layer can also be formed at the sidewall position of semiconductor packed layer 330 surface and opening 320 simultaneously; Then the metal gate of filling full described opening is formed.
When described grid structure also comprises function metal level, the semiconductor packed layer 330 utilizing selectivity depositing operation to be formed is mutually compatible with function metal layer process, and is conducive to the material of selection function metal level.Because the technique forming grid structure is well known to those skilled in the art, therefore is not described in detail in this.
Correspondingly, the present invention also provides the MOS transistor formed by said method, please refer to Figure 10, comprising:
Semiconductor substrate 300, described Semiconductor substrate 300 surface is formed with the dielectric layer 310 with opening; Be positioned at the semiconductor packed layer 330 of described open bottom; Fill the grid structure of full described opening, be positioned at the source of described grid structure semiconductor substrates on two sides 300, drain region.
Further, the present invention also provides a kind of CMOS transistor formation method, comprising: provide Semiconductor substrate, and described Semiconductor substrate comprises NMOS area and PMOS area, and isolates the isolation structure of adjacent NMOS area and PMOS area; Form dielectric layer at described semiconductor substrate surface, described dielectric layer has the opening exposing and be positioned at the Semiconductor substrate of PMOS area, and described opening both sides form active, drain region; N-shaped packed layer is formed in described open bottom; The grid structure of filling full described opening is formed on described N-shaped packed layer surface.
In an embodiment of the present invention, the grid structure of PMOS transistor and the grid structure of nmos pass transistor can be formed in same step, also the grid structure of PMOS transistor can first be formed, form the grid structure of nmos pass transistor again, or also first can form the grid structure of nmos pass transistor, then form the grid structure of PMOS transistor.
As an embodiment, form the grid structure of filling full described opening on described N-shaped packed layer surface and comprise: form opening in described NMOS area, described opening exposes the Semiconductor substrate being positioned at NMOS area; Exposing the surface being positioned at the opening of the Semiconductor substrate of NMOS area, and exposing the surface formation high-k dielectric layer being positioned at the opening of the Semiconductor substrate of PMOS area, and annealing in process is being carried out to described high-k dielectric layer.
Correspondingly, the present invention also provides the CMOS transistor formed by said method, please refer to Figure 11, comprising: Semiconductor substrate 200, and described Semiconductor substrate is divided into NMOS area 10 and PMOS area 20, separates between adjacent area with isolation structure; Be positioned at the dielectric layer 210 on described Semiconductor substrate 200 surface, described dielectric layer 210 has the opening exposing and be positioned at the Semiconductor substrate 200 of PMOS area 20; Be positioned at the N-shaped packed layer 230 of described open bottom; Fill the grid structure of full described opening, be positioned at the source of described grid structure semiconductor substrates on two sides 200, drain region.
Also comprise, expose the opening being positioned at the Semiconductor substrate 200 of NMOS area 10, fill the grid structure of full described opening, be positioned at the source of described grid structure both sides, drain region.
As an embodiment, the material of described N-shaped packed layer 230 is N-shaped Si
xge
y.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Compared with prior art, the present invention has the following advantages: the MOS transistor formation method that embodiments of the invention provide forms semiconductor packed layer in the bottom of grid structure, described semiconductor packed layer is positioned at surface, channel region, stress is produced to channel region, thus the threshold voltage of MOS transistor is had an impact;
Have semiconductor packed layer bottom the grid structure of the MOS transistor that embodiments of the invention provide, described semiconductor packed layer produces stress to channel region, thus has an impact to the threshold voltage of MOS transistor;
Further, in an embodiment of the present invention, semiconductor packed layer is formed on surface, the channel region of PMOS transistor, the material of described semiconductor packed layer is the SiGe of N-shaped, described semiconductor packed layer produces compression to channel region, thus improve the hole mobility of PMOS transistor channel region, the threshold voltage of PMOS transistor is reduced.
Further, embodiments of the invention also provide a kind of CMOS transistor formation method, described method forms semiconductor packed layer in the bottom of the grid structure of PMOS transistor, and described semiconductor packed layer produces stress to channel region, thus the threshold voltage of pair pmos transistor has an impact;
Further, embodiments of the invention also provide a kind of CMOS transistor, the bottom of the grid structure of the PMOS transistor in described CMOS transistor has semiconductor packed layer, and described semiconductor packed layer produces stress to channel region, thus the threshold voltage of pair pmos transistor has an impact.
Claims (12)
1. a formation method for MOS transistor, described MOS transistor is PMOS transistor, comprising: provide Semiconductor substrate;
Form dielectric layer at described semiconductor substrate surface, described dielectric layer has opening, described opening exposing semiconductor substrate, and described opening both sides form active, drain region;
It is characterized in that, also comprise:
Adopt selectivity depositing operation to form semiconductor packed layer in described open bottom, the material of described semiconductor packed layer is N-shaped Si
xge
y, described N-shaped Si
xge
yin, the scope of x:y is 50-90:50-10, and the thickness of described semiconductor packed layer is less than 10nm, and described selectivity depositing operation is 600-700 degree Celsius in temperature, and when air pressure is 0.2Torr, the gas passed into comprises SiH
4, GeH
4, AsH
4and H
2, wherein, SiH
4flow be 200sccm, AsH
4flow be 50-150sccm, H
2flow be 50slm;
Form the grid structure of filling full described opening;
Wherein, also comprise after forming described semiconductor packed layer, in inert gas environment, in the annealing temperature of 600-800 degree Celsius, annealing in process is carried out to Semiconductor substrate;
Or also comprise after forming described semiconductor packed layer, carry out laser annealing in the annealing temperature of 950-1050 degree Celsius, anneal duration is 0.1-0.5 second;
Or, also comprise after forming described semiconductor packed layer, quick high-temp thermal oxidation is carried out to Semiconductor substrate.
2. according to the formation method of MOS transistor according to claim 1, it is characterized in that, form the step with the dielectric layer of opening at described semiconductor substrate surface and comprise: form grid structure at described semiconductor substrate surface; With described grid structure for mask, Semiconductor substrate is adulterated, form source, drain region; Form the dielectric layer covering described grid structure, and planarization is carried out to described dielectric layer, until expose described grid structure; Remove described grid structure, form the dielectric layer with opening.
3. according to the formation method of MOS transistor according to claim 1, it is characterized in that, described Si
xge
ysi
55ge
45.
4. according to the formation method of MOS transistor according to claim 1, it is characterized in that, in inert gas environment, described annealing temperature is 650-750 degree Celsius, and anneal duration is 30-60 minute.
5. according to the formation method of MOS transistor according to claim 1, it is characterized in that, in the process forming semiconductor packed layer, semiconductor packed layer surface has oxide layer and is formed, and adopts diluted hydrofluoric acid to remove the oxide layer formed.
6. according to the formation method of MOS transistor according to claim 1, it is characterized in that, the step forming the grid structure of filling full described opening comprises: form high-k dielectric layer on packed layer surface, and carry out annealing in process to described high-k dielectric layer.
7. according to the formation method of MOS transistor according to claim 6, it is characterized in that, is 600-700 degree Celsius to the temperature of described high-k dielectric layer annealing in process, and anneal duration is 1 hour.
8. the MOS transistor formed any one of the claims, described MOS transistor is PMOS transistor, comprising: Semiconductor substrate, and described semiconductor substrate surface is formed with the dielectric layer with opening; It is characterized in that, also comprise: the semiconductor packed layer being positioned at described open bottom, the material of described semiconductor packed layer is N-shaped Si
xge
y, described N-shaped Si
xge
yin, the scope of x:y is 50-90:50-10, and the thickness of described semiconductor packed layer is less than 10nm, and described semiconductor packed layer adopts selectivity depositing operation, and be 600-700 degree Celsius in temperature, when air pressure is 0.2Torr, the gas passed into comprises SiH
4, GeH
4, AsH
4and H
2, wherein, SiH
4flow be 200sccm, AsH
4flow be 50-150sccm, H
2flow be 50slm formed; Fill the grid structure of full described opening, be positioned at the source of described grid structure semiconductor substrates on two sides, drain region.
9. a CMOS transistor formation method, comprising: provide Semiconductor substrate, and described Semiconductor substrate comprises NMOS area and PMOS area, and isolates the isolation structure of adjacent NMOS area and PMOS area; Form dielectric layer at described semiconductor substrate surface, described dielectric layer has the opening exposing and be positioned at the Semiconductor substrate of PMOS area, and described opening both sides form active, drain region; It is characterized in that, also comprise:
Adopt selectivity depositing operation to form N-shaped packed layer in described open bottom, the material of described N-shaped packed layer is N-shaped Si
xge
y, described N-shaped Si
xge
yin, the scope of x:y is 50-90:50-10, and the thickness of described semiconductor packed layer is less than 10nm, and described selectivity depositing operation is 600-700 degree Celsius in temperature, and when air pressure is 0.2Torr, the gas passed into comprises SiH
4, GeH
4, AsH
4and H
2, wherein, SiH
4flow be 200sccm, AsH
4flow be 50-150sccm, H
2flow be 50slm;
The grid structure of filling full described opening is formed on described N-shaped packed layer surface;
Wherein, also comprise after forming described semiconductor packed layer, in inert gas environment, in the annealing temperature of 600-800 degree Celsius, annealing in process is carried out to Semiconductor substrate;
Or also comprise after forming described semiconductor packed layer, carry out laser annealing in the annealing temperature of 950-1050 degree Celsius, anneal duration is 0.1-0.5 second;
Or, also comprise after forming described semiconductor packed layer, quick high-temp thermal oxidation is carried out to Semiconductor substrate.
10. according to CMOS transistor formation method according to claim 9, it is characterized in that, form the grid structure of filling full described opening on described N-shaped packed layer surface to comprise: form opening in described NMOS area, described opening exposes the Semiconductor substrate being positioned at NMOS area; Exposing the surface being positioned at the opening of the Semiconductor substrate of NMOS area, and exposing the surface formation high-k dielectric layer being positioned at the opening of the Semiconductor substrate of PMOS area, and annealing in process is being carried out to described high-k dielectric layer.
11. 1 kinds of CMOS transistor formed according to claim 9 or 10, comprising: Semiconductor substrate, described Semiconductor substrate comprises NMOS area and PMOS area, and isolates the isolation structure of adjacent NMOS area and PMOS area; Be positioned at the dielectric layer of described semiconductor substrate surface, described dielectric layer has the opening exposing and be positioned at the Semiconductor substrate of PMOS area; It is characterized in that, also comprise:
Be positioned at the N-shaped packed layer of described open bottom, the material of described N-shaped packed layer is N-shaped Si
xge
y, described N-shaped Si
xge
yin, the scope of x:y is 50-90:50-10, and described N-shaped packed layer adopts selectivity depositing operation, and be 600-700 degree Celsius in temperature, when air pressure is 0.2Torr, the gas passed into comprises SiH
4, GeH
4, AsH
4and H
2, wherein, SiH
4flow be 200sccm, AsH
4flow be 50-150sccm, H
2flow be 50slm formed;
Fill the grid structure of full described opening, be positioned at the source of described grid structure semiconductor substrates on two sides, drain region.
The CMOS transistor of 12. foundation claims 11, is characterized in that, also comprise, expose the opening being positioned at the Semiconductor substrate of NMOS area, fills the grid structure of full described opening, is positioned at the source of described grid structure both sides, drain region.
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