CN102855858B - Bidirectional scanning control switch, grid drive circuit and working method - Google Patents
Bidirectional scanning control switch, grid drive circuit and working method Download PDFInfo
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- CN102855858B CN102855858B CN201210322419.XA CN201210322419A CN102855858B CN 102855858 B CN102855858 B CN 102855858B CN 201210322419 A CN201210322419 A CN 201210322419A CN 102855858 B CN102855858 B CN 102855858B
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Abstract
The embodiment of the invention discloses a bidirectional scanning control switch, a grid drive circuit and a working method. The main content is as follows: a bidirectional scanning control switch is arranged, wherein after using the bidirectional scanning control switch in a gate drive circuit, a high level input from a voltage port is controlled by using a forward scan, the low level input from the voltage port is controlled by using a backward scan; the forward output gate drive signal can carry out the forward scan on a display point of a liquid crystal unit in a thin film transistor (TFT) panel; the high level input from the voltage port is controlled by using the backward scan, the low level input from the voltage port is controlled by using the forward scan, the backward output gate drive signal can carry out the backward scan on the display point of the liquid crystal unit in the TFT panel. The bidirectional scanning control switch can make the display method of the TFT panel flexible relatively.
Description
Technical field
The present invention relates to technical field of liquid crystal display, relate in particular to a kind of bilateral scanning switch, gate driver circuit and method of work.
Background technology
Liquid crystal display has been widely used in each demonstration field, the LCD TV of for example family expenses, the liquid crystal display advertising plate that public place uses, many electronic correlation products that the liquid crystal display of the computer that office is used and individual use etc.Traditional liquid crystal display utilizes electric field to control the transmittance of liquid crystal layer, and then on display panels, show image, this liquid crystal display comprises panel of LCD and driving circuit, and wherein the liquid crystal cells in panel of LCD is arranged with matrix form.
Particularly, liquid crystal display is in the time that energising shows, by the driving circuit output signal of liquid crystal display inside, the demonstration point of each liquid crystal cells of lining by line scan, to reach the object of image demonstration.
The driving circuit of liquid crystal display mainly comprises gate driver circuit and data drive circuit, wherein, data drive circuit is by the demonstration data timing order latch of input, and convert the data line that inputs to liquid crystal panel after simulating signal to, gate driver circuit is by clock signal process SR (the Shift Register of input, shift register) conversion, convert on/off voltage to, be applied to successively on the gate line of liquid crystal panel.In addition, the shift register in gate driver circuit is also for generation of the sweep signal in raster polar curve.
As shown in Figure 1, be traditional gate driver circuit schematic diagram, comprise multiple shift register SR
1~ SR
n, ground voltage V
sSline, the first clock CLK are provided
1line and second clock CLK are provided
2provide line, unbalanced pulse STV that line is provided.Wherein, the first clock signal clk
1with second clock signal CLK
2phase place opposite each other.
The principle of traditional gate driver circuit work is: in the time of STV=1, unbalanced pulse STV provides line to export a high level pulse to SR in gate driver circuit
1input end, therefore SR
1output port Output can be in the time that next pulse arrives to the first row liquid crystal display input high level in TFT panel, make the demonstration point of the first row liquid crystal cells in TFT panel in illuminating state, now, the demonstration point of other row liquid crystal cells in TFT panel is in illuminating state not.
Afterwards, then light the demonstration point of the second row liquid crystal cells in TFT panel, do not light the demonstration point of the first row liquid crystal cells in TFT panel, and the demonstration point that makes other row liquid crystal cells is in illuminating state not, specific practice is:
SR
1output port Output is the SR in gate driver circuit
2input end input high level, make SR
2output port Output end is at next pulse output high level, and to the second row liquid crystal display input high level in TFT panel, the demonstration point of the second row liquid crystal cells in TFT panel is in illuminating state, now, and SR
2output port Output output high level is to SR
1reset end, make SR
1reset, the demonstration point of the first row liquid crystal cells in corresponding TFT panel, in illuminating state not, has guaranteed to have in current TFT display panel the demonstration point of a line liquid crystal cells in illuminating state, and other provisional capitals are in illuminating state not.
According to above method by that analogy, can light successively the demonstration point of every a line liquid crystal cells in TFT panel, and only have the demonstration of a line liquid crystal cells to light at every turn, other are capable does not light, until the demonstration of last column liquid crystal cells point is lit in TFT panel, more again from TFT panel the demonstration of the first row liquid crystal cells point start to repeat.What the traditional gate driver circuit shown in Fig. 1 adopted is that a kind of specific display mode is lit the demonstration point of liquid crystal cells in TFT panel from top to bottom successively, this display mode is relatively single, the very flexible showing, cannot meet the demonstration demand of various different conditions.
Summary of the invention
The embodiment of the invention discloses a kind of bilateral scanning gauge tap, gate driver circuit and method of work, for solving traditional gate driver circuit, the demonstration point of TFT panel liquid crystal cells is lit from top to bottom successively, this display mode is relatively single, the very flexible showing, cannot meet the problem of the demonstration demand of various different conditions.
A kind of bilateral scanning gauge tap, described bilateral scanning gauge tap comprises: forward scan control voltage port (FW
7), reverse scan control voltage port (BW
8), first input end mouth (I
9), the second input port (I
10), the first output port (IN
5), the second output port (RE
6), the first transistor (Tn
1), transistor seconds (Tn
2), the 3rd transistor (Tn
3) and the 4th transistor (Tn
4), wherein:
The first transistor (Tn
1) grid and first input end mouth (I
9) be connected, the first transistor (Tn
1) drain electrode and forward scan control voltage port (FW
7) be connected, the 3rd transistor (Tn
3) grid and the second input port (I
10) be connected, the 3rd transistor (Tn
3) drain electrode and reverse scan control voltage port (BW
8) be connected, the 3rd transistor (Tn
3) source electrode and the first transistor (Tn
1) the connected tie point of source electrode, with the first output port (IN
5) be connected;
Transistor seconds (Tn
2) grid and the second input port (I
10) be connected, transistor seconds (Tn
2) drain electrode and forward scan control voltage port (FW
7) be connected, the 4th transistor (Tn
4) grid and first input end mouth (I
9) be connected, the 4th transistor (Tn
4) drain electrode and reverse scan control voltage port (BW
8) be connected, the 4th transistor (Tn
4) source electrode and transistor seconds (Tn
2) the connected tie point of source electrode, with the second output port (RE
6) be connected.
A kind of gate driver circuit, described gate driver circuit also comprises: unbalanced pulse STV provides line (STV
13), forward scan provides line (L
14), reverse scan provides line (L
15), a n shift register (SR
1~ SR
n), n above-mentioned bilateral scanning gauge tap (CS
1~ CS
n), at least two switch elements, described n is positive integer, wherein:
Forward scan control voltage port (FW in each bilateral scanning gauge tap
7) provide line (L with forward scan
14) be connected, reverse scan control voltage port (BW
8) provide line (L with reverse scan
15) be connected;
Unbalanced pulse STV provides line (STV
13) be connected with the grid of a switch element, the source electrode of this switch element and first bilateral scanning gauge tap (CS
1) in first input end mouth (I
9) be connected, the drain electrode of this switch element and forward scan provide line (L
14) be connected;
M bilateral scanning gauge tap (CS
m) in first input end mouth (I
9) and m-1 shift register (SR
m-1) Output port be connected, m bilateral scanning gauge tap (CS
m) in the second input port (I
10) and m+1 shift register (SR
m+1) Output port be connected, wherein, described m is greater than 1 and be less than the positive integer of n;
Unbalanced pulse STV provides line (STV
13) be connected with the grid of another switch element, the source electrode of this switch element and n bilateral scanning gauge tap (CS
n) in the second input port (I
10) be connected, this switch element (Tn
10) drain electrode and reverse scan line (L is provided
15) be connected;
In described n bilateral scanning gauge tap, the first output port (IN in each bilateral scanning gauge tap
5) be connected with the Input port of corresponding shift register, the second output port (RE in this bilateral scanning gauge tap
6) be connected with the Reset port of corresponding shift register.
A method of work for bilateral scanning gauge tap described above, described method comprises:
As forward scan control voltage port (FW
7) input high level, and first input end mouth (I
9) when input high level, the first transistor (Tn
1) in conducting state, by with the first transistor (Tn
1) source electrode be connected the first output port (IN
5) output high level;
As forward scan control voltage port (FW
7) input high level, and the second input port (I
10) when input high level, transistor seconds (Tn
2) in conducting state, by with transistor seconds (Tn
2) source electrode be connected the second output port (RE
6) output high level;
As reverse scan control voltage port (BW
8) input high level, and the second input port (I
10) when input high level, the 3rd transistor (Tn
3) in conducting state, by with the 3rd transistor (Tn
3) source electrode be connected the first output port (IN
5) output high level;
As reverse scan control voltage port (BW
8) input high level, and first input end mouth (I
9) when input high level, the 4th transistor (Tn
4) in conducting state, by with the 4th transistor (Tn
4) source electrode be connected the second output port (RE
6) output high level.
A method of work for gate driver circuit, described method comprises:
When unbalanced pulse STV provides line (STV
13) while being high level, provide line (L in forward scan
14) provide high level, reverse scan that line (L is provided
15) when low level is provided, forward output gate drive signal;
Provide line (L in reverse scan
15) provide high level, forward scan that line (L is provided
14) when low level is provided, oppositely export gate drive signal.
Beneficial effect of the present invention is as follows:
In embodiment of the present invention gate driver circuit, use after two-way gauge tap, utilize the high level of forward scan voltage port input and unbalanced pulse STV that the high level of line is provided, forward output gate drive signal, realizes the forward scan of the demonstration point to the liquid crystal cells in TFT panel; Utilize the high level of reverse scan voltage port input and unbalanced pulse STV that the high level of line is provided, oppositely output gate drive signal, realize the reverse scan of the demonstration point to the liquid crystal cells in TFT panel, this bilateral scanning gauge tap is simple in structure, as long as adding this switch arrays on pcb board just can realize, and such display mode makes the dirigibility of the display mode comparison of the demonstration point of liquid crystal cells in TFT panel, meet the demonstration demand of various different conditions simultaneously.
Accompanying drawing explanation
Fig. 1 is traditional gate driver circuit schematic diagram;
Fig. 2 is the structural representation of a kind of bilateral scanning gauge tap in the embodiment of the present invention one;
Fig. 3 is a kind of structural representation of bilateral scanning gauge tap;
Fig. 4 is a kind of schematic flow sheet of method of work of bilateral scanning gauge tap;
Fig. 5 is the structural representation of a kind of gate driver circuit of the present embodiment three;
Fig. 6 is a kind of structural representation of gate driver circuit;
Fig. 7 is the schematic flow sheet of the method for work of a kind of gate driver circuit of the present embodiment four.
Embodiment
In order to realize object of the present invention, the embodiment of the invention discloses a kind of bilateral scanning gauge tap, gate driver circuit and method of work, described bilateral scanning gauge tap comprises: forward scan control voltage port FW
7, reverse scan control voltage port BW
8, first input end mouth I
9, the second input port I
10, the first output port IN
5, the second output port RE
6, the first transistor Tn
1, transistor seconds Tn
2, the 3rd transistor T n
3with the 4th transistor T n
4, wherein:
The first transistor Tn
1grid and first input end mouth I
9be connected, the first transistor Tn
1drain electrode and forward scan control voltage port FW
7be connected, the 3rd transistor T n
3grid and the second input port I
10be connected, the 3rd transistor T n
3drain electrode and reverse scan control voltage port BW
8be connected, the 3rd transistor T n
3source electrode and the first transistor Tn
1the connected tie point of source electrode, with the first output port IN
5be connected;
Transistor seconds Tn
2grid and the second input port I
10be connected, transistor seconds Tn
2drain electrode and forward scan control voltage port FW
7be connected, the 4th transistor T n
4grid and first input end mouth I
9be connected, the 4th transistor T n
4drain electrode and reverse scan control voltage port BW
8be connected, the 4th transistor T n
4source electrode and transistor seconds Tn
2the connected tie point of source electrode, with the second output port RE
6be connected.
This bilateral scanning gauge tap is applied in gate driver circuit to the first output port IN of each bilateral scanning gauge tap
5be connected with the Input port of each shift register in gate driver circuit, the second output port RE of each bilateral scanning gauge tap
6be connected with the Reset port of each shift register in gate driver circuit, what realized like this access of forward scan control voltage port in first bilateral scanning gauge tap is high level, what reverse scan control voltage port accessed is low level, and when what first input end mouth accessed is high level, first shift register output high level in gate driver circuit, the demonstration point of the first row liquid crystal cells in TFT panel is lighted, light successively the demonstration point of next line liquid crystal cells, close the demonstration point of lastrow liquid crystal cells simultaneously, realize the forward scan of the demonstration point of liquid crystal cells in TFT panel, the in the end reverse scan control voltage port in bilateral scanning gauge tap access be high level, the access of forward scan control voltage port be low level, and when what the second input port accessed is high level, last shift register output high level in gate driver circuit, the demonstration point of last column liquid crystal cells in TFT panel is lighted, light successively the demonstration point of lastrow liquid crystal cells, close the demonstration point of next line liquid crystal cells simultaneously, realize the reverse scan of the demonstration point of liquid crystal cells in TFT panel.Such display mode makes the dirigibility of the display mode comparison of the demonstration point of liquid crystal cells in TFT panel, meets the demonstration demand of various different conditions simultaneously.
Below in conjunction with Figure of description, various embodiments of the present invention are described in detail.
Embodiment mono-:
As shown in Figure 2, be the structural representation of a kind of bilateral scanning gauge tap in the embodiment of the present invention one.Described bilateral scanning gauge tap comprises: forward scan control voltage port FW
7, reverse scan control voltage port BW
8, first input end mouth I
9, the second input port I
10, the first output port IN
5, the second output port RE
6, the first transistor Tn
1, transistor seconds Tn
2, the 3rd transistor T n
3with the 4th transistor T n
4, wherein:
The first transistor Tn
1grid and first input end mouth I
9be connected, the first transistor Tn
1drain electrode and forward scan control voltage port FW
7be connected, the 3rd transistor T n
3grid and the second input port I
10be connected, the 3rd transistor T n
3drain electrode and reverse scan control voltage port BW
8be connected, the 3rd transistor T n
3source electrode and the first transistor Tn
1the connected tie point of source electrode, with the first output port IN
5be connected;
Transistor seconds Tn
2grid and the second input port I
10be connected, transistor seconds Tn
2drain electrode and forward scan control voltage port FW
7be connected, the 4th transistor T n
4grid and first input end mouth I
9be connected, the 4th transistor T n
4drain electrode and reverse scan control voltage port BW
8be connected, the 4th transistor T n
4source electrode and transistor seconds Tn
2the connected tie point of source electrode, with the second output port RE
6be connected.
More preferably, as shown in Figure 3, be a kind of structural representation of bilateral scanning gauge tap.Described bilateral scanning gauge tap also comprises: the 5th transistor T n
5, wherein:
The 5th transistor T n
5grid and the first transistor Tn
1source electrode be connected, the 5th transistor T n
5drain electrode and first input end mouth I
9be connected, the 5th transistor T n
5source electrode and the first output port IN
5be connected.
Described bilateral scanning gauge tap also comprises: the 6th transistor T n
6, wherein:
The 6th transistor T n
6grid and the 3rd transistor T n
3source electrode be connected, the 6th transistor T n
6drain electrode and the second input port I
10be connected, the 6th transistor T n
6source electrode and the first output port IN
5be connected.
Described bilateral scanning gauge tap also comprises: the 7th transistor T n
7, wherein:
The 7th transistor T n
7grid and transistor seconds Tn
2source electrode be connected, the 7th transistor T n
7drain electrode and the second input port I
10be connected, the 7th transistor T n
7source electrode and the second output port RE
6be connected.
Described bilateral scanning gauge tap also comprises: the 8th transistor T n
8, wherein:
The 8th transistor T n
8grid and the 4th transistor T n
4source electrode be connected, the 8th transistor T n
8drain electrode and first input end mouth I
9be connected, the 8th transistor T n
8source electrode and the second output port RE
6be connected.
It should be noted that, the number of the 5th transistor to the eight transistors in bilateral scanning gauge tap do not limit, as long as meet above-mentioned connected mode.
Embodiment bis-:
As shown in Figure 4, be a kind of process flow diagram of method of work of bilateral scanning gauge tap.In the present embodiment two, describe as example to there are 4 transistorized bilateral scanning gauge tap.The method of work of this bilateral scanning gauge tap is:
Step 101: at forward scan control voltage port FW
7input high level, performs step 102; At reverse scan control voltage port BW
8input high level, performs step 105.
Step 102: at first input end mouth I
9input high level, performs step 103; At the second input port I
10input high level, performs step 104.
Step 103: the first transistor Tn
1in conducting state, by with the first transistor Tn
1source electrode be connected the first output port IN
5output high level.
Step 104: transistor seconds Tn
2in conducting state, by with transistor seconds Tn
2source electrode be connected the second output port RE
6output high level.
Step 105: at first input end mouth I
9when input high level, perform step 106; At the second input port I
10when input high level, perform step 107.
Step 106: the 4th transistor T n
4in conducting state, by with the 4th transistor T n
4source electrode be connected the second output port RE
6output high level.
Step 107: the 3rd transistor T n
3in conducting state, by with the 3rd transistor T n
3source electrode be connected the first output port IN
5output high level.
Embodiment tri-:
As shown in Figure 5, be the structural representation of a kind of gate driver circuit of the present embodiment three.Described gate driver circuit also comprises: unbalanced pulse STV provides line STV
13, forward scan provides line L
14, reverse scan provides line L
15, a n shift register SR
1~ SR
n, a n bilateral scanning gauge tap CS
1~ CS
n, at least two switch elements, described n is positive integer, wherein:
Forward scan control voltage port FW in each bilateral scanning gauge tap
7provide line L with forward scan
14be connected, reverse scan control voltage port BW
8provide line L with reverse scan
15be connected;
Unbalanced pulse STV provides line STV
13be connected with the grid of a switch element, the source electrode of this switch element and first bilateral scanning gauge tap CS
1in first input end mouth I
9be connected, the drain electrode of this switch element and forward scan provide line L
14be connected;
M bilateral scanning gauge tap CS
min first input end mouth I
9with m-1 shift register SR
m-1output port be connected, m bilateral scanning gauge tap CS
min the second input port I
10with m+1 shift register SR
m+1output port be connected, wherein, described m is greater than 1 and be less than the positive integer of n;
Unbalanced pulse STV provides line STV
13be connected with the grid of another switch element, the source electrode of this switch element and n bilateral scanning gauge tap CS
nin the second input port I
10be connected, the drain electrode of this switch element and reverse scan provide line L
15be connected;
In described n bilateral scanning gauge tap, the first output port IN in each bilateral scanning gauge tap
5be connected with the Input port of corresponding shift register, the second output port RE in this bilateral scanning gauge tap
6be connected with the Reset port of corresponding shift register.
When a switch element is the 9th transistor, when another switch element is the tenth transistor, unbalanced pulse STV provides line STV
13with the 9th transistor T n
9grid be connected, the 9th transistor T n
9source electrode and first bilateral scanning gauge tap CS
1in first input end mouth I
9be connected, the 9th transistor T n
9drain electrode and forward scan line L is provided
14be connected;
M bilateral scanning gauge tap CS
min first input end mouth I
9with m-1 shift register SR
m-1output port be connected, m bilateral scanning gauge tap CS
min the second input port I
10with m+1 shift register SR
m+1output port be connected, wherein, described m is greater than 1 and be less than the positive integer of n;
Unbalanced pulse STV provides line STV
13with the tenth transistor T n
10grid be connected, the tenth transistor T n
10source electrode and n bilateral scanning gauge tap CS
nin the second input port I
10be connected, the tenth transistor T n
10drain electrode and reverse scan line L is provided
15be connected;
In described n bilateral scanning gauge tap, the first output port IN in each bilateral scanning gauge tap
5be connected with the Input port of corresponding shift register, the second output port RE in this bilateral scanning gauge tap
6be connected with the Reset port of corresponding shift register.
Described gate driver circuit also comprises: the first clock signal clk 1, second clock signal CLK2 and ground voltage Vss provide line.Wherein, the first clock signal clk 1 is opposite each other with the phase place of second clock signal CLK2, is respectively forward scan line L is provided
14provide line L with reverse scan
15the high level providing can be identical with the high level phase place of the first clock signal clk 1 and second clock signal CLK2, can be not identical yet, do not limit here.
More preferably, as shown in Figure 6, when a switch element is the 9th transistor and the 11 transistor, when another switch element is the tenth transistor and the tenth two-transistor, unbalanced pulse STV provides line STV
13with the 11 transistor T n
11drain electrode be connected, the 9th transistor T n
9source electrode and the 11 transistor T n
11grid be connected, the 11 transistor T n
11source electrode and first bilateral scanning gauge tap CS
1in first input end mouth I
9be connected;
Unbalanced pulse STV provides line STV
13with the tenth two-transistor Tn
12drain electrode be connected, the tenth transistor T n
10source electrode and the tenth two-transistor Tn
12grid be connected, the tenth two-transistor Tn
12source electrode and n bilateral scanning gauge tap CS
nin the second input port I
10be connected.
It should be noted that, the number of switch element is not done concrete restriction, as long as can realize the above-mentioned function of the present invention.
Embodiment tetra-:
As shown in Figure 7, be the schematic flow sheet of the method for work of a kind of gate driver circuit of the present embodiment four.The bilateral scanning gauge tap using in the present embodiment is the bilateral scanning gauge tap shown in Fig. 2, and gate driver circuit is the gate driver circuit shown in Fig. 5.Described method comprises:
Step 201: when unbalanced pulse STV provides line STV
13during for high level, provide line L in forward scan
14high level is provided, and reverse scan provides line L
15when low level is provided, perform step 202; Provide line L in reverse scan
15high level is provided, and forward scan provides line L
14when low level is provided, perform step 203.
Step 202: forward output gate drive signal.
Particularly, the mode of forward output gate drive signal comprises:
The first step: output the first row gate drive signal, the first row display switch triggering in TFT panel is opened.
When unbalanced pulse STV provides line STV
13for high level, and forward scan provides line L
14high level is provided, and reverse scan provides line L
15when low level is provided, the 9th transistor T n
9in conducting state, by the 9th transistor T n
9source electrode to first bilateral scanning gauge tap CS
1in first input end mouth I
9input high level, makes first bilateral scanning gauge tap CS
1in the first transistor Tn
1in conducting state;
By first bilateral scanning gauge tap CS
1in the first output port IN
5to first shift register (SR
1) in Input port input high level, after a pulse duration, Output port output high level in first shift register, export the first row gate drive signal, triggering the first row display switch of TFT panel opens, the demonstration point that causes the first row liquid crystal cells is lighted, and to second bilateral scanning gauge tap CS
2in first input end mouth I
9input high level, makes second bilateral scanning gauge tap CS
2in the first transistor Tn
1in conducting state;
By second bilateral scanning gauge tap CS
2in the first output port IN
5to second shift register SR
2in the high level of second pulse of Input port input, after a pulse duration, second shift register SR
2in Output port output high level, export the second row gate drive signal, trigger the second row display switch of TFT panel and open, cause that the demonstration point of the second row liquid crystal cells is lighted, and to first bilateral scanning gauge tap CS
1in the second input port I
10input high level, makes first bilateral scanning gauge tap CS
1in transistor seconds Tn
2in conducting state;
By first bilateral scanning gauge tap CS
1in the second output port RE
6to first shift register SR
1in Reset port input high level, make first shift register SR
1reset, trigger the first row display switch of TFT panel and close, cause that the demonstration point of the first row liquid crystal cells is closed.
Second step: the capable gate drive signal of output m, the capable display switch of m triggering in TFT panel is opened.
When forward scan provides line L
14high level is provided, and reverse scan provides line L
15when low level is provided, by m-1 shift register SR
m-1in Output port to m bilateral scanning gauge tap CS
mfirst input end mouth I
9input high level, makes m bilateral scanning gauge tap CS
min the first transistor Tn
1in conducting state;
By m bilateral scanning gauge tap CS
min the first output port IN
5to m shift register SR
min Input port input high level, after a pulse duration, m shift register SR
min Output port output high level, export the capable gate drive signal of m, trigger the capable display switch of m of TFT panel and open, cause that the demonstration point of the capable liquid crystal cells of m is lighted, and to m+1 bilateral scanning gauge tap CS
m+1in first input end mouth I
9input high level, makes m+1 bilateral scanning gauge tap CS
m+1in the first transistor Tn
1in conducting state;
By m+1 bilateral scanning gauge tap CS
m+1in the first output port IN
5to m+1 shift register SR
m+1in Input port input high level, after a pulse duration, m+1 shift register SR
m+1in Output port output high level, export the capable gate drive signal of m+1, trigger the capable display switch of m+1 of TFT panel and open, cause that the demonstration point of the capable liquid crystal cells of m+1 is lighted, and to m bilateral scanning gauge tap CS
min the second input port I
10input high level, makes m bilateral scanning gauge tap CS
min transistor seconds Tn
2in conducting state;
By m bilateral scanning gauge tap CS
min the second output port RE
6to m shift register SR
min Reset port input high level, make m shift register SR
mreset, trigger the capable display switch of m of TFT panel and close.
Need brightly, in the time that m+1 equals n, the demonstration point that represents the liquid crystal cells in whole TFT panel travels through successively from top to bottom formula and was all lighted.
Step 203: oppositely export gate drive signal.
Particularly, the mode of oppositely exporting gate drive signal comprises:
The first step: the capable gate drive signal of output n, the capable display switch of n triggering in TFT panel is opened.
When unbalanced pulse STV provides line STV
13for high level, and reverse scan provides line L
15high level is provided, and forward scan provides line L
14when low level is provided, the tenth transistor T n
10in conducting state, by the tenth transistor T n
10source electrode to n bilateral scanning gauge tap CS
nthe second input port I
10input high level, makes n bilateral scanning gauge tap CS
nin the 3rd transistor T n
3in conducting state;
By n bilateral scanning gauge tap CS
nin the first output port IN
5to n shift register SR
nin Input port input high level, after a pulse duration, Output port output high level in n shift register, export the capable gate drive signal of n, triggering the capable display switch of n of TFT panel opens, the demonstration point that causes the capable liquid crystal cells of n is lighted, and to n-1 bilateral scanning gauge tap CS
n-1in the second input port I
10input high level, makes n-1 bilateral scanning gauge tap CS
n-1in the 3rd transistor T n
3in conducting state;
By n-1 bilateral scanning gauge tap CS
n-1in the first output port IN
5to n-1 shift register SR
n-1in Input port input high level, after a pulse duration, n-1 shift register SR
n-1in Output port output high level, export the capable gate drive signal of n-1, trigger the capable display switch of n-1 of TFT panel and open, cause that the demonstration point of the capable liquid crystal cells of n-1 is lighted, and to n bilateral scanning gauge tap CS
nin first input end mouth I
9input high level, makes n bilateral scanning gauge tap CS
nin the 4th transistor T n
4in conducting state;
By n bilateral scanning gauge tap CS
nin the second output port RE
6to n shift register SR
nin Reset port input high level, make n shift register SR
nreset, trigger the capable display switch of n of TFT panel and close.
Second step: the capable gate drive signal of output m, the capable display switch of m triggering in TFT panel is opened.
When reverse scan provides line L
15provide high level, and forward scan provides line L
14when low level is provided, by m+1 shift register SR
m+1in Output port to m bilateral scanning gauge tap CS
mthe second input port I
10input high level, makes m bilateral scanning gauge tap CS
min the 3rd transistor T n
3in conducting state;
By m bilateral scanning gauge tap CS
min the first output port IN
5to m shift register SR
min Input port input high level, after a pulse duration, m shift register SR
min Output port output high level, export the capable gate drive signal of m, trigger the capable display switch of m of TFT panel and open, cause that the demonstration point of the capable liquid crystal cells of m is lighted, to m-1 bilateral scanning gauge tap CS
m-1in the second input port I
10input high level, makes m-1 bilateral scanning gauge tap CS
m-1in the 3rd transistor T n
3in conducting state;
By m-1 bilateral scanning gauge tap CS
m-1in the first output port IN
5to m-1 shift register SR
m-1in Input port input high level, after a pulse duration, m-1 shift register SR
m-1in Output port output high level, export the capable gate drive signal of m-1, trigger the capable display switch of m-1 of TFT panel and open, cause that the demonstration point of the capable liquid crystal cells of m-1 is lighted, and to m bilateral scanning gauge tap CS
min first input end mouth I
9input the high level of the second pulse, make m bilateral scanning gauge tap CS
min the 4th transistor T n
4in conducting state;
By m bilateral scanning gauge tap CS
min the second output port RE
6to the Reset port input high level in m shift register, make m shift register SR
mreset, trigger the capable display switch of m of TFT panel and close.
By the scheme of embodiment mono-to embodiment tetra-, in gate driver circuit, use after two-way gauge tap, utilize the high level of forward scan voltage port input, the low level of reverse scan voltage port input, and unbalanced pulse STV provides the high level of line, realize the forward scan of the demonstration point to the liquid crystal cells in TFT panel; Utilize the high level of reverse scan voltage port input, the low level of forward scan voltage port input, and unbalanced pulse STV provides the high level of line, realize the reverse scan of the demonstration point to the liquid crystal cells in TFT panel, such display mode makes the dirigibility of the display mode comparison of the demonstration point of liquid crystal cells in TFT panel, meets the demonstration demand of various different conditions simultaneously.
Embodiment five:
The present embodiment has 4 shift registers and 4 bilateral scanning gauge tap as example take gate driver circuit, specifically describes the process of forward scan and reverse scan.Concrete grammar comprises:
Step 1: when unbalanced pulse STV provides line STV
13during for high level, provide line L in forward scan
14provide high level and reverse scan that line L is provided
15when low level is provided, execution step two; Provide line L in reverse scan
15provide high level and forward scan that line L is provided
14when low level is provided, execution step three.
Step 2: forward output gate drive signal.
Particularly, the process that forward is exported gate drive signal successively comprises:
The first step: successively the display switch of the first row in TFT panel and the second row is opened.
When unbalanced pulse STV provides line STV
13for high level, and forward scan provides line L
14high level is provided, and reverse scan provides line L
15when low level is provided, the 9th transistor T n
9in conducting state, by the 9th transistor T n
9source electrode to first bilateral scanning gauge tap CS
1in first input end mouth I
9input high level, makes first bilateral scanning gauge tap CS
1in the first transistor Tn
1in conducting state;
By first bilateral scanning gauge tap CS
1in the first output port IN
5to first shift register SR
1in Input port input high level, after a pulse duration, Output port output high level in first shift register, export the first row gate drive signal, triggering the first row display switch of TFT panel opens, the demonstration point that causes the first row liquid crystal cells is lighted, and to second bilateral scanning gauge tap CS
2in first input end mouth I
9input high level, makes second bilateral scanning gauge tap CS
2in the first transistor Tn
1in conducting state;
By second bilateral scanning gauge tap CS
2in the first output port IN
5to second shift register SR
2in Input port input high level, after a pulse duration, second shift register SR
2in Output port output high level, export the second row gate drive signal, trigger the second row display switch of TFT panel and open, cause that the demonstration point of the second row liquid crystal cells is lighted, and to first bilateral scanning gauge tap CS
1in the second input port I
10input high level, makes first bilateral scanning gauge tap CS
1in transistor seconds Tn
2in conducting state;
By first bilateral scanning gauge tap CS
1in the second output port RE
6to first shift register SR
1in Reset port input high level, make first shift register SR
1reset, trigger the first row display switch of TFT panel and close.
Second step: the third line display switch of TFT panel is opened.
Passing through second shift register SR
2in Ouput port output high level after trigger the second row liquid crystal cells of TFT panel demonstration point light, and to the 3rd bilateral scanning gauge tap CS
3in first input end mouth I
9input high level, makes the 3rd bilateral scanning gauge tap CS
3in the first transistor Tn
1in conducting state;
By the 3rd bilateral scanning gauge tap CS
3in the first output port IN
5to the 3rd shift register SR
3in Input port input high level, after a pulse duration, the 3rd shift register SR
3in Output port output high level, export the third line gate drive signal, trigger the third line display switch of TFT panel and open, cause that the demonstration point of the third line liquid crystal cells is lighted, to second bilateral scanning gauge tap CS
2in the second input port I
10input high level, makes second bilateral scanning gauge tap CS
2in transistor seconds Tn
2in conducting state;
By second bilateral scanning gauge tap CS
2in the second output port RE
6to second shift register SR
2in Reset port input high level, after a pulse duration, make second shift register SR
2reset, trigger the second row display switch of TFT panel and close.
The 3rd step: the fourth line display switch in TFT panel is opened.
Passing through the 3rd shift register SR
3in Ouput port output high level after trigger the third line liquid crystal cells of TFT panel demonstration point light, and to the 4th bilateral scanning gauge tap CS
4in first input end mouth I
9input high level, makes the 4th bilateral scanning gauge tap CS
4in the first transistor Tn
1in conducting state;
By the 4th bilateral scanning gauge tap CS
4in the first output port IN
5to the 4th shift register SR
4in Input port input high level, after a pulse duration, the 4th shift register SR
4in Output port output high level, export fourth line gate drive signal, trigger the fourth line display switch of TFT panel and open, cause that the demonstration point of fourth line liquid crystal cells is lighted, to the 3rd bilateral scanning gauge tap CS
3in the second input port RE
6input high level, makes the 3rd bilateral scanning gauge tap CS
3in transistor seconds Tn
2in conducting state;
By the 3rd bilateral scanning gauge tap CS
3in the second output port RE
6to the 3rd shift register SR
3in Reset port input high level, make the 3rd shift register SR
3reset, trigger the third line display switch of TFT panel and close.
Step 3: oppositely export gate drive signal.
Particularly, the reverse process of exporting successively gate drive signal comprises:
The first step: successively the display switch of the fourth line in TFT panel and the third line is opened.
When unbalanced pulse STV provides line STV
13for high level, and reverse scan provides line L
15high level is provided, and forward scan provides line L
14when low level is provided, the tenth transistor T n
10in conducting state, by the tenth transistor T n
10source electrode to the 4th bilateral scanning gauge tap CS
4the second input port I
10input high level, makes the 4th bilateral scanning gauge tap CS
4in the 3rd transistor T n
3in conducting state;
By the 4th bilateral scanning gauge tap CS
4in the first output port IN
5to the 4th shift register SR
4in Input port input high level, after a pulse duration, Output port output high level in the 4th shift register, export fourth line gate drive signal, triggering the fourth line display switch of TFT panel opens, the demonstration point that causes fourth line liquid crystal cells is lighted, and to the 3rd bilateral scanning gauge tap CS
3in the second input port I
10input high level, makes the 3rd bilateral scanning gauge tap CS
3in the 3rd transistor T n
3in conducting state;
By the 3rd bilateral scanning gauge tap CS
3in the first output port IN
5to the 3rd shift register SR
3in Input port input high level, make the 3rd shift register SR
3in Output port output high level, export the third line gate drive signal, trigger the third line display switch of TFT panel and open, cause that the demonstration point of the third line liquid crystal cells is lighted, and to the 4th bilateral scanning gauge tap CS
4in first input end mouth I
9input high level, makes the 4th bilateral scanning gauge tap CS
4in the 4th transistor T n
4in conducting state;
By the 4th bilateral scanning gauge tap CS
4in the second output port RE
6to the 4th shift register SR
4in Reset port input high level, make the 4th shift register SR
4reset, trigger the fourth line display switch of TFT panel and close.
Second step: the second row display switch in TFT panel is opened.
Passing through the 3rd shift register SR
3in Output port output high level after trigger the third line liquid crystal cells of TFT panel demonstration point light, and to second bilateral scanning gauge tap CS
2in the second input port Ix input high level, make second bilateral scanning gauge tap CS
2in the 3rd transistor T n
3in conducting state;
By second bilateral scanning gauge tap CS
2in the first output port IN
5to second shift register SR
2in Input port input high level, after a pulse duration, second shift register SR
2in Output port output high level, export the second row gate drive signal, trigger the second row display switch of TFT panel and open, cause that the demonstration point of the second row liquid crystal cells is lighted, and to the 3rd bilateral scanning gauge tap CS
3in first input end mouth I
9input high level, makes the 3rd bilateral scanning gauge tap CS
3in the 4th transistor T n
4in conducting state;
By the 3rd bilateral scanning gauge tap CS
3in the second output port RE
6to the Reset port input high level in the 3rd shift register, make the 3rd shift register SR
3reset, trigger the third line display switch of TFT panel and close.
The 3rd step: the first row display switch in TFT panel is opened.
Passing through second shift register SR
2in Ouput port output high level after trigger the second row liquid crystal cells of TFT panel demonstration point light, and to first bilateral scanning gauge tap CS
1in the second input port I
10input high level, makes first bilateral scanning gauge tap CS
1in the 3rd transistor T n
3in conducting state;
By first bilateral scanning gauge tap CS
1in the first output port IN
5to first shift register SR
1in Input port input high level, after a pulse duration, first shift register SR
1in Output port output high level, export the first row gate drive signal, trigger the first row display switch of TFT panel and open, cause that the demonstration point of the first row liquid crystal cells is lighted, and to second bilateral scanning gauge tap CS
2in first input end mouth I
9input high level, makes second bilateral scanning gauge tap CS
2in the 4th transistor T n
4in conducting state;
By second bilateral scanning gauge tap CS
2in the second output port RE
6to the Reset port input high level in second shift register, make second shift register SR
2reset, trigger the second row display switch of TFT panel and close.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. a bilateral scanning gauge tap, is characterized in that, described bilateral scanning gauge tap comprises: forward scan control voltage port (FW
7), reverse scan control voltage port (BW
8), first input end mouth (I
9), the second input port (I
10), the first output port (IN
5), the second output port (RE
6), the first transistor (Tn
1), transistor seconds (Tn
2), the 3rd transistor (Tn
3) and the 4th transistor (Tn
4), wherein:
The first transistor (Tn
1) grid and first input end mouth (I
9) be connected, the first transistor (Tn
1) drain electrode and forward scan control voltage port (FW
7) be connected, the 3rd transistor (Tn
3) grid and the second input port (I
10) be connected, the 3rd transistor (Tn
3) drain electrode and reverse scan control voltage port (BW
8) be connected, the 3rd transistor (Tn
3) source electrode and the first transistor (Tn
1) the connected tie point of source electrode, with the first output port (IN
5) be connected;
Transistor seconds (Tn
2) grid and the second input port (I
10) be connected, transistor seconds (Tn
2) drain electrode and forward scan control voltage port (FW
7) be connected, the 4th transistor (Tn
4) grid and first input end mouth (I
9) be connected, the 4th transistor (Tn
4) drain electrode and reverse scan control voltage port (BW
8) be connected, the 4th transistor (Tn
4) source electrode and transistor seconds (Tn
2) the connected tie point of source electrode, with the second output port (RE
6) be connected.
2. bilateral scanning gauge tap as claimed in claim 1, is characterized in that, described bilateral scanning gauge tap also comprises: the 5th transistor (Tn
5), the 6th transistor (Tn
6), the 7th transistor (Tn
7), the 8th transistor (Tn
8), wherein:
The 5th transistor (Tn
5) grid and the first transistor (Tn
1) source electrode be connected, the 5th transistor (Tn
5) drain electrode and first input end mouth (I
9) be connected, the 5th transistor (Tn
5) source electrode and the first output port (IN
5) be connected;
The 6th transistor (Tn
6) grid and the 3rd transistor (Tn
3) source electrode be connected, the 6th transistor (Tn
6) drain electrode and the second input port (I
10) be connected, the 6th transistor (Tn
6) source electrode and the first output port (IN
5) be connected;
The 7th transistor (Tn
7) grid and transistor seconds (Tn
2) source electrode be connected, the 7th transistor (Tn
7) drain electrode and the second input port (I
10) be connected, the 7th transistor (Tn
7) source electrode and the second output port (RE
6) be connected;
The 8th transistor (Tn
8) grid and the 4th transistor (Tn
4) source electrode be connected, the 8th transistor (Tn
8) drain electrode and first input end mouth (I
9) be connected, the 8th transistor (Tn
8) source electrode and the second output port (RE
6) be connected.
3. a gate driver circuit, is characterized in that, described gate driver circuit also comprises: unbalanced pulse STV provides line (STV
13), forward scan provides line (L
14), reverse scan provides line (L
15), a n shift register (SR
1～SR
n), the bilateral scanning gauge tap (CS of n as described in as arbitrary in claim 1～2
1～CS
n), at least two switch elements, described n is positive integer, wherein:
Forward scan control voltage port (FW in each bilateral scanning gauge tap
7) provide line (L with forward scan
14) be connected, reverse scan control voltage port (BW
8) provide line (L with reverse scan
15) be connected;
Unbalanced pulse STV provides line (STV
13) be connected with the grid of a switch element, the source electrode of this switch element and first bilateral scanning gauge tap (CS
1) in first input end mouth (I
9) be connected, the drain electrode of this switch element and forward scan provide line (L
14) be connected;
M bilateral scanning gauge tap (CS
m) in first input end mouth (I
9) and m-1 shift register (SR
m-1) Output port be connected, m bilateral scanning gauge tap (CS
m) in the second input port (I
10) and m+1 shift register (SR
m+
1) Output port be connected, wherein, described m is greater than 1 and be less than the positive integer of n;
Unbalanced pulse STV provides line (STV
13) be connected with the grid of another switch element, the source electrode of this switch element and n bilateral scanning gauge tap (CS
n) in the second input port (I
10) be connected, the drain electrode of this switch element and reverse scan provide line (L
15) be connected;
In described n bilateral scanning gauge tap, the first output port (IN in each bilateral scanning gauge tap
5) be connected with the Input port of corresponding shift register, the second output port (RE in this bilateral scanning gauge tap
6) be connected with the Reset port of corresponding shift register.
4. gate driver circuit as claimed in claim 3, is characterized in that,
When a switch element comprises the 9th transistor, when another switch element comprises the tenth transistor, unbalanced pulse STV provides line (STV
13) and the 9th transistor (Tn
9) grid be connected, the 9th transistor (Tn
9) source electrode and first bilateral scanning gauge tap (CS
1) in first input end mouth (I
9) be connected, the 9th transistor (Tn
9) drain electrode and forward scan line (L is provided
14) be connected;
Unbalanced pulse STV provides line (STV
13) and the tenth transistor (Tn
10) grid be connected, the tenth transistor (Tn
10) source electrode and n bilateral scanning gauge tap (CS
n) in the second input port (I
10) be connected, the tenth transistorized drain electrode and reverse scan provide line (L
15) be connected;
When a switch element comprises the 9th transistor and the 11 transistor, when another switch element comprises the tenth transistor and the tenth two-transistor, unbalanced pulse STV provides line (STV
13) and the 11 transistor (Tn
11) drain electrode be connected, the 9th transistor (Tn
9) source electrode and the 11 transistor (Tn
11) grid be connected, the 11 transistor (Tn
11) source electrode and first bilateral scanning gauge tap (CS
1) in first input end mouth (I
9) be connected;
Unbalanced pulse STV provides line (STV
13) and the tenth two-transistor (Tn
12) drain electrode be connected, the tenth transistor (Tn
10) source electrode and the tenth two-transistor (Tn
12) grid be connected, the 11 transistor (Tn
12) source electrode and n bilateral scanning gauge tap (CS
n) in the second input port (I
10) be connected.
5. a method of work for bilateral scanning gauge tap as claimed in claim 1, is characterized in that, described method comprises:
As forward scan control voltage port (FW
7) input high level, and first input end mouth (I
9) when input high level, the first transistor (Tn
1) in conducting state, by with the first transistor (Tn
1) source electrode be connected the first output port (IN
5) output high level;
As forward scan control voltage port (FW
7) input high level, and the second input port (I
10) when input high level, transistor seconds (Tn
2) in conducting state, by with transistor seconds (Tn
2) source electrode be connected the second output port (RE
6) output high level;
As reverse scan control voltage port (BW
8) input high level, and the second input port (I
10) when input high level, the 3rd transistor (Tn
3) in conducting state, by with the 3rd transistor (Tn
3) source electrode be connected the first output port (IN
5) output high level;
As reverse scan control voltage port (BW
8) input high level, and first input end mouth (I
9) when input high level, the 4th transistor (Tn
4) in conducting state, by with the 4th transistor (Tn
4) source electrode be connected the second output port (RE
6) output high level.
6. a method of work for gate driver circuit as claimed in claim 3, is characterized in that, described method comprises:
When unbalanced pulse STV provides line (STV
13) while being high level, provide line (L in forward scan
14) provide high level, reverse scan that line (L is provided
15) when low level is provided, forward output gate drive signal;
Provide line (L in reverse scan
15) provide high level, forward scan that line (L is provided
14) when low level is provided, oppositely export gate drive signal.
7. method as claimed in claim 6, is characterized in that, forward output gate drive signal, specifically comprises:
When unbalanced pulse STV provides line (STV
13) be high level, and forward scan provides line (L
14) provide high level, reverse scan that line (L is provided
15) when low level is provided, a switch element is in conducting state, the source electrode by this switch element is to first bilateral scanning gauge tap (CS
1) in first input end mouth (I
9) input high level, make first bilateral scanning gauge tap (CS
1) in the first transistor (Tn
1) in conducting state;
By first bilateral scanning gauge tap (CS
1) in the first output port (IN
5) to first shift register (SR
1) in Input port input high level, after a pulse duration, the Output port output high level in first shift register, exports the first row gate drive signal, trigger the first row display switch of TFT panel and open, and to second bilateral scanning gauge tap (CS
2) in first input end mouth (I
9) input high level, make second bilateral scanning gauge tap (CS
2) in the first transistor (Tn
1) in conducting state;
By second bilateral scanning gauge tap (CS
2) in the first output port (IN
5) to second shift register (SR
2) in Input port input high level, after a pulse duration time, second shift register (SR
2) in Output port output high level, export the second row gate drive signal, trigger the second row display switch of TFT panel and open, and to first bilateral scanning gauge tap (CS
1) in the second input port (I
10) input high level, make first bilateral scanning gauge tap (CS
1) in transistor seconds (Tn
2) in conducting state;
By first bilateral scanning gauge tap (CS
1) in the second output port (RE
6) to first shift register (SR
1) in Reset port input high level, make first shift register (SR
1) reset, trigger the first row display switch of TFT panel and close.
8. method as claimed in claim 6, is characterized in that, forward output gate drive signal, specifically also comprises:
Provide line (STV in forward scan
13) high level is provided, and reverse scan provides line (L
15) when low level is provided, by m-1 shift register (SR
m-1) in Output port to m bilateral scanning gauge tap (CS
m) first input end mouth (I
9) input high level, make m bilateral scanning gauge tap (CS
m) in the first transistor (Tn
1) in conducting state;
By m bilateral scanning gauge tap (CS
m) in the first output port (IN
5) to m shift register (SR
m) in Input port input high level, after a pulse duration, m shift register (SR
m) in Output port output high level, export the capable gate drive signal of m, trigger the capable display switch of m of TFT panel and open, and to m+1 bilateral scanning gauge tap (CS
m+1) in first input end mouth (I
9) input high level, make m+1 bilateral scanning gauge tap (CS
m+1) in the first transistor (Tn
1) in conducting state;
By m+1 bilateral scanning gauge tap (CS
m+1) in the first output port (IN
5) to m+1 shift register (SR
m+1) in Input port input high level, after a pulse duration, m+1 shift register (SR
m+1) in Output port output high level, export the capable gate drive signal of m+1, trigger the capable display switch of m+1 of TFT panel and open, and to m bilateral scanning gauge tap (CS
m) in the second input port (I
10) input high level, make m bilateral scanning gauge tap (CS
m) in transistor seconds (Tn
2) in conducting state;
By m bilateral scanning gauge tap (CS
m) in the second output port (RE
6) to m shift register (SR
m) in Reset port input high level, make m shift register (SR
m) reset, trigger the capable display switch of m of TFT panel and close.
9. method as claimed in claim 6, is characterized in that, oppositely exports gate drive signal, specifically comprises:
When unbalanced pulse STV provides line (STV
13) be high level, and reverse scan provides line (L
15) provide high level, forward scan that line (L is provided
14) when low level is provided, another switch element is in conducting state, the source electrode by this switch element is to n bilateral scanning gauge tap (CS
n) the second input port (I
10) input high level, make n bilateral scanning gauge tap (CS
n) in the 3rd transistor (Tn
3) in conducting state;
By n bilateral scanning gauge tap (CS
n) in the first output port (IN
5) to n shift register (SR
n) in Input port input high level, after a pulse duration, the Output port output high level in n shift register, exports the capable gate drive signal of n, trigger the capable display switch of n of TFT panel and open, and to n-1 bilateral scanning gauge tap (CS
n-1) in the second input port (I
10) input high level, make n-1 bilateral scanning gauge tap (CS
n-1) in the 3rd transistor (Tn
3) in conducting state;
By n-1 bilateral scanning gauge tap (CS
n-1) in the first output port (IN
5) to n-1 shift register (SR
n-1) in Input port input high level, after a pulse duration, n-1 shift register (SR
n-1) in Output port output high level, export the capable gate drive signal of n-1, trigger the capable display switch of n-1 of TFT panel and open, and to n bilateral scanning gauge tap (CS
n) in first input end mouth (I
9) input high level, make n bilateral scanning gauge tap (CS
n) in the 4th transistor (Tn
4) in conducting state;
By n bilateral scanning gauge tap (CS
n) in the second output port (RE
6) to n shift register (SR
n) in Reset port input high level, make n shift register (SR
n) reset, trigger the capable display switch of n of TFT panel and close.
10. method as claimed in claim 6, is characterized in that, oppositely exports gate drive signal, specifically also comprises:
When reverse scan provides line (L
15) high level is provided, and forward scan provides line (L
14) when low level is provided, by m+1 shift register (SR
m+1) in Output port to m bilateral scanning gauge tap (CS
m) the second input port (I
10) input high level, make m bilateral scanning gauge tap (CS
m) in the 3rd transistor (Tn
3) in conducting state;
By m bilateral scanning gauge tap (CS
m) in the first output port (IN
5) to m shift register (SR
m) in Input port input high level, after a pulse duration, by m shift register (SR
m) in Output port output high level, export the capable gate drive signal of m, trigger the capable display switch of m of TFT panel and open, and to m-1 bilateral scanning gauge tap (CS
m-1) in the second input port (I
10) input high level, make m-1 bilateral scanning gauge tap (CS
m-1) in the 3rd transistor (Tn
3) in conducting state;
By m-1 bilateral scanning gauge tap (CS
m-1) in the first output port (IN
5) to m-1 shift register (SR
m-1) in Input port input high level, after a pulse duration, m-1 shift register (SR
m-1) in Output port output high level, export the capable gate drive signal of m-1, trigger the capable display switch of m-1 of TFT panel and open, and to m bilateral scanning gauge tap (CS
m) in first input end mouth (I
9) input high level, make m bilateral scanning gauge tap (CS
m) in the 4th transistor (Tn
4) in conducting state;
By m bilateral scanning gauge tap (CS
m) in the second output port (RE
6) to the Reset port input high level in m shift register, make m shift register (SR
m) reset, trigger the capable display switch of m of TFT panel and close.
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| CN201210322419.XA CN102855858B (en) | 2012-09-03 | 2012-09-03 | Bidirectional scanning control switch, grid drive circuit and working method |
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Families Citing this family (8)
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| CN103761954B (en) | 2014-02-17 | 2016-10-19 | 友达光电(厦门)有限公司 | Display floater and gate drivers |
| CN104183210B (en) * | 2014-09-17 | 2016-08-17 | 厦门天马微电子有限公司 | A kind of gate driver circuit and driving method thereof and display device |
| CN106356019B (en) * | 2016-11-28 | 2019-05-17 | 京东方科技集团股份有限公司 | Select connection unit, shift register and display panel |
| CN107490884B (en) * | 2017-09-04 | 2020-04-03 | 昆山龙腾光电股份有限公司 | Selector, array substrate, liquid crystal display device and driving method |
| CN107978277B (en) | 2018-01-19 | 2019-03-26 | 昆山国显光电有限公司 | Scanner driver and its driving method, organic light emitting display |
| CN109389927B (en) * | 2018-02-09 | 2020-04-24 | 京东方科技集团股份有限公司 | Shift register, driving method thereof and grid driving circuit |
| CN108682380B (en) * | 2018-07-26 | 2021-01-08 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| CN110111717B (en) * | 2019-05-06 | 2021-04-09 | 京东方科技集团股份有限公司 | Gate drive circuit, gate drive method, array substrate and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101237232A (en) * | 2008-02-25 | 2008-08-06 | 友达光电股份有限公司 | Bidirectional control device for improving component voltage resistance |
| CN101515446A (en) * | 2008-09-17 | 2009-08-26 | 友达光电股份有限公司 | Bidirectional scanning shift register |
| CN101894588A (en) * | 2010-01-11 | 2010-11-24 | 友达光电股份有限公司 | Bidirectional shift register and its driving method |
| CN102087827A (en) * | 2010-05-11 | 2011-06-08 | 友达光电股份有限公司 | Shift register |
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| CN101237232A (en) * | 2008-02-25 | 2008-08-06 | 友达光电股份有限公司 | Bidirectional control device for improving component voltage resistance |
| CN101515446A (en) * | 2008-09-17 | 2009-08-26 | 友达光电股份有限公司 | Bidirectional scanning shift register |
| CN101894588A (en) * | 2010-01-11 | 2010-11-24 | 友达光电股份有限公司 | Bidirectional shift register and its driving method |
| CN102087827A (en) * | 2010-05-11 | 2011-06-08 | 友达光电股份有限公司 | Shift register |
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