CN107490884B

CN107490884B - Selector, array substrate, liquid crystal display device and driving method

Info

Publication number: CN107490884B
Application number: CN201710787739.5A
Authority: CN
Inventors: 乔艳冰; 何钰莹; 吕晶; 李森龙; 张军; 张好好
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2017-09-04
Filing date: 2017-09-04
Publication date: 2020-04-03
Anticipated expiration: 2037-09-04
Also published as: CN107490884A

Abstract

The invention discloses a selector, an array substrate, a liquid crystal display device and a driving method, wherein the array substrate is provided with a plurality of scanning lines, a plurality of data lines, a plurality of pixel units arranged in an array, a first voltage line, a second voltage line, a third voltage line, a fourth voltage line, a plurality of first common electrode strips, a plurality of second common electrode strips, a plurality of first selectors and a plurality of second selectors, each common electrode strip extends along the scanning line direction, the plurality of first common electrode strips and the plurality of second common electrode strips are arranged at intervals in the data line direction, each first common electrode strip is connected with the first voltage line, the second voltage line, the third voltage line and the fourth voltage line through one first selector, and each second common electrode strip is connected with the first voltage line through one second selector, The second voltage line, the third voltage line, the fourth voltage line are connected to a corresponding scanning line.

Description

Selector, array substrate, liquid crystal display device and driving method

Technical Field

The invention relates to the technical field of liquid crystal display, in particular to a selector, an array substrate, a liquid crystal display device and a driving method.

Background

A Liquid Crystal Display (LCD) has advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, and is dominant in the field of flat panel displays.

With the continuous progress of the liquid crystal display technology, the viewing angle of the display has been widened from about 120 ° to over 160 °, and people want to effectively protect business confidentiality and personal privacy while enjoying visual experience brought by a large viewing angle, so as to avoid business loss or embarrassment caused by the leakage of screen information. There is therefore a need for a display device that can be switched to a narrow viewing angle in addition to a wide viewing angle.

At present, the switching between the wide viewing angle and the narrow viewing angle is generally realized by the shielding function of the shutter, which requires an additional shielding film outside the display device, and is inconvenient to use.

Recently, it has been proposed to apply a vertical electric field to liquid crystal molecules by using a viewing angle control electrode on the color filter substrate (CF) side to switch between a wide viewing angle and a narrow viewing angle. Referring to fig. 1 and 2, the lcd device includes an upper substrate 11, a lower substrate 12, and a liquid crystal layer 13 disposed between the upper substrate 11 and the lower substrate 12, wherein the upper substrate 11 is provided with a viewing angle control electrode 111, and the lower substrate 12 is provided with a common electrode 121 and a pixel electrode 122. As shown in fig. 1, in the wide viewing angle display, the viewing angle control electrode 111 of the upper substrate 11 does not apply a voltage, and the liquid crystal display device realizes the wide viewing angle display. As shown in fig. 2, when a narrow viewing angle display is required, the viewing angle control electrode 111 of the upper substrate 11 applies a large voltage, the liquid crystal molecules in the liquid crystal layer 13 tilt due to the vertical electric field E (as shown by the arrow in the figure), and the contrast of the liquid crystal display device is reduced due to light leakage, thereby finally realizing a narrow viewing angle.

In order to prevent polarization of liquid crystal molecules, the voltage applied to the viewing angle control electrode 111 is generally an ac voltage in narrow viewing angle display. The viewing angle control electrode 111 is a planar electrode on the whole surface, that is, the viewing angle control electrode 111 covers all the pixel units on the whole surface, for the liquid crystal display device, only one row of pixel units is charged at each moment, the rest uncharged pixel units are in a suspended state for holding charges, the voltage change on the viewing angle control electrode 111 can change the pixel voltage in the suspended state through capacitive coupling, the voltage difference between the pixel electrode 122 and the common electrode 121 and the voltage difference between the pixel electrode 122 and the viewing angle control electrode 111 change, the arrangement state of liquid crystal molecules changes, and the penetration rate of the pixel units changes correspondingly. At the same time, the difference of the penetration rates of the pixel units at different positions can cause uneven brightness of the display panel; at different times, the display panel flickers due to the difference of the penetration rates of the same pixel unit, and the image quality of the panel is reduced due to the superposition of the difference of the penetration rates in space and time, so that the display panel is prone to display unevenness, flickers and other problems.

In order to solve this problem, the prior art optimizes the driving waveform and driving voltage of the ac voltage applied to the viewing angle control electrode 111 to reduce the influence of the display unevenness, but the effect of improving the image quality is limited; alternatively, the flicker of the picture is reduced by doubling the frame frequency of the liquid crystal display device (i.e., increasing the frame frequency from 60Hz to 120Hz), but this increases the logic power consumption, and the time for turning on each scan line is halved, which reduces the pixel charging time and affects the pixel charging effect.

As shown in fig. 3, in order to realize the polarity inversion display, the polarities of the data voltages (Vdata) applied to the two adjacent pixel cells P1 and P2 are different, but in the narrow viewing angle display, since the viewing angle control electrode 111 is a planar electrode, the voltage difference between the pixel electrode 122 and the viewing angle control electrode 111 of the two adjacent pixel cells is also different at the same time, so that the vertical electric field voltage difference generated by the two adjacent pixel cells P1 and P2 with different polarities is different, which easily causes the brightness of the two adjacent pixel cells P1 and P2 to be different, and as shown in fig. 4, the pixel cell on the left side is darker than the pixel cell on the right side.

Disclosure of Invention

The invention aims to provide a selector, an array substrate, a liquid crystal display device and a driving method, which can realize wide and narrow visual angle switching in different occasions and solve the problems of uneven screen display and flicker.

An embodiment of the present invention provides a selector, including a first switching element, a second switching element, a third switching element, a fourth switching element, a first storage capacitor and a second storage capacitor, a control terminal of the first switching element is connected to a control terminal of the second switching element and is configured to receive a scan signal, a first path terminal of the first switching element is configured to receive one of a first ac control voltage and a second ac control voltage, a first path terminal of the second switching element is configured to receive the other of the first ac control voltage and the second ac control voltage, a second path terminal of the first switching element is connected to the control terminal of the third switching element and is connected to a first node, a second path terminal of the second switching element is connected to the control terminal of the fourth switching element and is connected to a second node, a first path terminal of the third switching element is configured to receive a first dc common voltage, the first path end of the fourth switching element is used for receiving a second direct current common voltage, the second path end of the third switching element is connected with the second path end of the fourth switching element and used for outputting the common voltage, the first storage capacitor is connected with the first node, and the second storage capacitor is connected with the second node.

The embodiment of the invention further provides an array substrate, the array substrate is provided with a plurality of scanning lines, a plurality of data lines and a plurality of pixel units arranged in an array, the array substrate is further provided with a first voltage line, a second voltage line, a third voltage line, a fourth voltage line, a plurality of common electrode strips and a plurality of selectors, each common electrode strip extends along the scanning line direction, the plurality of common electrode strips comprise a plurality of first common electrode strips and a plurality of second common electrode strips, the plurality of first common electrode strips and the plurality of second common electrode strips are arranged at intervals in the data line direction, the plurality of selectors comprise a plurality of first selectors and a plurality of second selectors, each first common electrode strip is connected with the first voltage line, the second voltage line, the third voltage line, the fourth voltage line and a corresponding scanning line through one first selector, each of the second common electrode bars is connected to the first voltage line, the second voltage line, the third voltage line, the fourth voltage line, and a corresponding one of the scanning lines through a second selector.

The embodiment of the invention also provides a liquid crystal display device, which comprises an array substrate, a color film substrate arranged opposite to the array substrate and a liquid crystal layer positioned between the array substrate and the color film substrate, wherein the array substrate is the array substrate, and the color film substrate is provided with an upper electrode on the whole surface.

An embodiment of the present invention further provides a driving method for driving the liquid crystal display device, including:

in a first viewing angle mode, applying a reference voltage to the upper electrode, applying a first common voltage with a smaller amplitude relative to the reference voltage to each first common electrode bar through the first selector, and applying a second common voltage with a smaller amplitude relative to the reference voltage to each second common electrode bar through the second selector, so that the voltage difference between all the common electrode bars and the upper electrode is smaller than a first preset value;

in a second viewing angle mode, applying a reference voltage to the upper electrode, applying a first common voltage with a larger amplitude relative to the reference voltage to each first common electrode bar through the first selector, and applying a second common voltage with a larger amplitude relative to the reference voltage to each second common electrode bar through the second selector, so that the voltage difference between all the common electrode bars and the upper electrode is larger than a second preset value; and the second preset value is greater than or equal to the first preset value.

The array substrate, the liquid crystal display device and the driving method provided by the embodiment of the invention are realized by switching the voltage for controlling the switching of the wide and narrow visual angles from the visual angle control electrode on the color film substrate side to the common electrode strip on the array substrate side, the common electrode on the array substrate is divided into a plurality of mutually independent common electrode strips, each common electrode strip is correspondingly connected with one scanning line through one control switch, when each line of scanning lines is opened, the common electrode strip covering the line of pixel units is charged with the common voltage through the selector, the common electrode strips are independently endowed with voltage signals during pixel scanning, the charged common electrode strips of each line and the common electrode strips to be charged are not influenced mutually, the voltage signals endowed to the common electrode strips of each line are not influenced by the charging of the common electrode strips of the adjacent lines, and the problems of uneven display and flicker in a display panel caused by the coupling effect are solved, the display image quality is improved.

Drawings

Fig. 1 is a partial cross-sectional view of a conventional liquid crystal display device at a wide viewing angle.

Fig. 2 is a partial cross-sectional view of the liquid crystal display device of fig. 1 at a narrow viewing angle.

Fig. 3 is a voltage diagram of two pixel units of the liquid crystal display device in fig. 1 under a narrow viewing angle.

Fig. 4 is a diagram illustrating display effects of two pixel units of the liquid crystal display device in fig. 1 under a narrow viewing angle.

Fig. 5 is a schematic circuit diagram of a liquid crystal display device according to a first embodiment of the invention.

Fig. 6 is a schematic plan view of the common electrode bar on the liquid crystal display device of fig. 5.

Fig. 7 is a circuit structure and a driving schematic diagram of the first selector and the second selector in fig. 5.

Fig. 8 is a partial cross-sectional view of the liquid crystal display device of fig. 5 taken along line VIII-VIII.

Fig. 9 is a schematic view of the liquid crystal display device in fig. 8 at a narrow viewing angle.

Fig. 10 is a schematic diagram of driving waveforms of the first selector in the narrow viewing angle of the lcd device in fig. 5.

FIG. 11 is a schematic diagram of driving waveforms of the second selector in the narrow viewing angle of the LCD device in FIG. 5.

Fig. 12 is a voltage diagram of two pixel units of the lcd device in fig. 8 under a narrow viewing angle.

Fig. 13 is a diagram of display effects of two pixel units of the liquid crystal display device in fig. 8 under a narrow viewing angle.

Fig. 14a and 14b are schematic plan views of the lcd device of fig. 8.

Fig. 15 is a schematic circuit diagram of a liquid crystal display device according to a second embodiment of the invention.

Fig. 16 is a schematic circuit diagram of a liquid crystal display device according to a third embodiment of the invention.

Fig. 17 is a schematic circuit diagram of a liquid crystal display device according to a fourth embodiment of the invention.

Fig. 18 is a schematic circuit diagram of a liquid crystal display device according to a fifth embodiment of the invention.

Fig. 19 is a schematic plan view illustrating a structure of a common electrode bar on the liquid crystal display device of fig. 18.

FIG. 20 is a partial cross-sectional view of a liquid crystal display device in a sixth embodiment of the present invention.

Fig. 21 is a schematic view of the liquid crystal display device in fig. 20 at a wide viewing angle.

Detailed Description

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the present invention will be made with reference to the accompanying drawings and examples.

[ first embodiment ]

Referring to fig. 5 to 8, a liquid crystal display device according to a first embodiment of the present invention includes a display panel 50, where the display panel 50 includes an array substrate 20, a color filter substrate 30 disposed opposite to the array substrate 20, and a liquid crystal layer 40 disposed between the array substrate 20 and the color filter substrate 30.

The array substrate 20 is provided with a plurality of scan lines 21 and a plurality of data lines 22. The plurality of scanning lines 21 and the plurality of data lines 22 are insulated and crossed to define a plurality of pixel units arranged in an array. Each pixel unit is provided with a pixel electrode 23 and a thin film transistor 26, and the pixel electrode 23 is connected to the scanning line 21 and the data line 22 adjacent to the thin film transistor 26 through the thin film transistor 26. Specifically, the thin film transistor 26 includes a gate electrode, a source electrode and a drain electrode, wherein the gate electrode is electrically connected to the corresponding scan line 21, the gate electrode may be independently disposed or may be a part of the scan line 21, the source electrode is electrically connected to the corresponding data line 22, and the drain electrode is electrically connected to the corresponding pixel electrode 23.

The array substrate 20 is further provided with a plurality of common electrode strips 24 arranged in parallel at intervals, each common electrode strip 24 extends along the direction of the scanning line 21, and in this embodiment, each common electrode strip 24 correspondingly covers a whole row of pixel units. The plurality of common electrode bars 24 include a plurality of first common electrode bars 24a and a plurality of second common electrode bars 24b, and the plurality of first common electrode bars 24a and the plurality of second common electrode bars 24b are disposed to be spaced apart from each other in the direction of the data line 22. In the embodiment, in the direction of the data line 22, each of the first common electrode stripes 24a and each of the second common electrode stripes 24b are alternately disposed, wherein the plurality of first common electrode stripes 24a correspondingly cover the pixel cells in the odd-numbered rows (i.e., rows 1, 3, 5, …), and the plurality of second common electrode stripes 24b correspondingly cover the pixel cells in the even-numbered rows (i.e., rows 2, 4, 6, …).

As shown in fig. 8, on the array substrate 20, the pixel electrode 23 and the common electrode bar 24 may be located at different layers with an insulating layer 29 interposed therebetween, and the pixel electrode 23 may be located above the common electrode bar 24, so that the liquid crystal display device forms a Fringe Field Switching (FFS) structure. In the liquid crystal display device, during normal display, a fringe electric field is generated between the common electrode stripes 24 and the pixel electrodes 23, so that liquid crystal molecules rotate in a plane substantially parallel to the substrate to obtain a wide viewing angle.

The color filter substrate 30 is provided with a color resist layer 31, a Black Matrix (BM)32, and an upper electrode 33. The color resist layer 31 is, for example, R, G, B color resist. The upper electrode 33 is a planar electrode over the entire surface, i.e., the entire surface of the upper electrode 33 covers the display region. The color resist layer 31 and the black matrix 32 are disposed on the surface of the color filter substrate 30 facing the liquid crystal layer 40, and other film structures are disposed on the color resist layer 31 and the black matrix 32. At least one insulating layer or planarization layer may be further disposed on the color filter substrate 30. In this embodiment, a planarization layer 35 is further disposed on the color filter substrate 30, the planarization layer 35 covers the color resist layer 32 and the black matrix 31, and the upper electrode 33 is formed on the planarization layer 35.

As shown in fig. 5, the array substrate 20 is further provided with a first voltage line 201, a second voltage line 202, a third voltage line 203, a fourth voltage line 204, and a plurality of selectors 27, the plurality of selectors 27 include a plurality of first selectors 27a and a plurality of second selectors 27b, each first common electrode bar 24a is connected to the first voltage line 201, the second voltage line 202, the third voltage line 203, the fourth voltage line 204, and a corresponding scanning line 21 through one first selector 27a, and each second common electrode bar 24b is connected to the first voltage line 201, the second voltage line 202, the third voltage line 203, the fourth voltage line 204, and a corresponding scanning line 21 through one second selector 27 b. Specifically, the first voltage line 201, the second voltage line 202, the third voltage line 203, the fourth voltage line 204, and the plurality of

selectors

27a, 27b are disposed in the non-display area of the display panel 50.

Specifically, referring to fig. 5 and 7, each first selector 27a and each second selector 27b have the same structure. Each of the first and second selectors 27a and 27b includes a first switching element T1, a second switching element T2, a third switching element T3, a fourth switching element T4, a first storage capacitor Cst1, and a second storage capacitor Cst2, a control terminal of the first switching element T1 is connected to the control terminal of the second switching element T2 and connected to the corresponding scan line 21, a first pass terminal of the first switching element T1 is connected to one of the first and second voltage lines 201 and 202, a first pass terminal of the second switching element T2 is connected to the other of the first and second voltage lines 201 and 202, a second pass terminal of the first switching element T1 is connected to the control terminal of the third switching element T3 and connected to the first node Q1, a second pass terminal of the second switching element T2 is connected to the fourth switching element and to the control terminal of the T4 and connected to the third pass terminal Q2 of the second switching element T3, a first path terminal of the fourth switching element T4 is connected to the fourth voltage line 204, a second path terminal of the third switching element T3 is connected to a second path terminal of the fourth switching element T4 and to the corresponding common electrode bar 24, a first storage capacitor Cst1 is connected to the first node Q1, and a second storage capacitor Cst2 is connected to the second node Q2.

In the present embodiment, for each first selector 27a, the first pass terminal of the first switching element T1 is connected to the first voltage line 201, and the first pass terminal of the second switching element T2 is connected to the second voltage line 202; for each second selector 27b, the first pass terminal of the first switching element T1 is connected to the second voltage line 202, and the first pass terminal of the second switching element T2 is connected to the first voltage line 201.

Specifically, the first switching element T1, the second switching element T2, the third switching element T3, and the fourth switching element T4 may be thin film transistors, the control terminal is a gate, one of the first path terminal and the second path terminal is a source, and the other is a drain.

In this embodiment, each pixel unit in each row is respectively connected to two scanning lines 21 on the upper and lower sides of the pixel unit in the row, and the common electrode bar 24 in each row is connected to the scanning line 21 on the upper side or the lower side of the pixel unit in the row through the corresponding selector 27. In this embodiment, the common electrode bar 24 of each row is connected to the scan line 21 on the lower side of the pixel units of the row through the corresponding selector 27, as shown in fig. 5, but is not limited thereto, and in other embodiments, the common electrode bar 24 of each row may also be connected to the scan line 21 on the upper side of the pixel units of the row through the corresponding selector 27 (not shown).

In this embodiment, each pixel unit in each row is alternately connected to two scan lines 21 located at the upper and lower sides of the pixel unit in the row, and each pixel unit in each column is alternately connected to two data lines 22 located at the left and right sides of the pixel unit in the column. For example, for the first row of pixel cells, each pixel cell at the odd number position is connected to the scan line Gate0 at the upper side, and each pixel cell at the even number position is connected to the scan line Gate1 at the lower side; for the second row of pixel units, each pixel unit at the odd number position is connected with the scanning line Gate1 at the upper side, and each pixel unit at the even number position is connected with the scanning line Gate2 at the lower side; the above arrangement is repeated every two subsequent rows. For the pixel units in the first column, the pixel units in the odd number are connected with the Data line Data1 on the left side, and the pixel units in the even number are connected with the Data line Data2 on the right side; for the second column of pixel units, each pixel unit at the odd number position is connected with the Data line Data3 at the right side, and each pixel unit at the even number position is connected with the Data line Data2 at the left side; the above arrangement is repeated every two subsequent columns.

Also, the respective pixel cells in each row are charged through only the data lines 22 of the odd-numbered columns or only the even-numbered columns. For example, each pixel cell in the first row is connected to only the odd-numbered Data line 22(Data1, Data3, Data5, etc.), so each pixel cell in the first row is charged only through the Data line 22 of the odd-numbered column, and the pixel cells in the remaining odd-numbered rows are also charged only through the Data line 22 of the odd-numbered column; each pixel cell in the second row is connected to only the Data line 22 of the even bit (Data2, Data4, Data6, etc.), so each pixel cell in the second row is charged only through the Data line 22 of the even column, and the pixel cells in the remaining even rows are also charged only through the Data line 22 of the even column. In this way, the polarity of the Data voltage (Vdata) applied to each Data line 22 can be maintained in the same frame, and for example, in the same frame, the Data1 applies the Data voltage (Vdata-) of negative polarity and the Data2 applies the Data voltage (Vdata +), thereby realizing row inversion display by driving the Data lines and columns, and saving power consumption.

In one frame of picture, when all the scanning lines 21 are sequentially turned on to charge the pixel units in each row, because each first common electrode bar 24a is connected with the first voltage line 201, the second voltage line 202, the third voltage line 203 and the fourth voltage line 204 through the first selector 27a, each first common electrode bar 24a is charged with the first common voltage in the charging time period of the pixel units in one row correspondingly covered by the first common electrode bar 24 a; since each of the second common electrode bars 24b is connected to the first voltage line 201, the second voltage line 202, the third voltage line 203 and the fourth voltage line 204 through the second selector 27b, each of the second common electrode bars 24b will be charged with the second common voltage during the charging period of the pixel cells of the row that it correspondingly covers.

For example, when the scan lines Gate0 and Gate1 are sequentially turned on to charge the pixel cells in the first row, the first common electrode bar 24a covering the pixel cells in the first row is charged by the first selector 27a connected to the scan line Gate1 and charged with the first common voltage. When the scan line Gate1 is turned off, the first common voltage charged in the first common electrode bar 24a of the first row is in a charge holding state until the scan line Gate1 of the next frame is turned on again. When the scan lines Gate1 and Gate2 are sequentially turned on to charge the pixel cells in the second row, the second common electrode bar 24b covering the pixel cells in the second row is charged by the second selector 27b connected to the scan line Gate2 and charged with the second common voltage. When the scan line Gate2 is turned off, the second common voltage charged in the second common electrode bar 24b of the second row is in a charge holding state until the scan line Gate2 is turned on again for the next frame.

In this embodiment, the liquid crystal molecules in the liquid crystal layer 40 are positive liquid crystal molecules, and the positive liquid crystal molecules have the advantage of fast response. As shown in fig. 8, in an initial state (i.e., a state where no voltage is applied to the liquid crystal display device), the positive liquid crystal molecules in the liquid crystal layer 40 assume a lying posture substantially parallel to the

substrates

20, 30, i.e., a long axis direction of the positive liquid crystal molecules is substantially parallel to the surfaces of the

substrates

20, 30. In practical applications, however, the positive liquid crystal molecules in the liquid crystal layer 40 and the

substrates

20 and 30 may have a small initial pretilt angle, which may range from 10 degrees or less, that is: 0 DEG ≦ theta ≦ 10 deg.

In this embodiment, the liquid crystal display device can be switched between the wide viewing angle mode and the narrow viewing angle mode by controlling the voltage signals applied to the upper electrode 33 of the color film substrate 30 and the common electrode stripes 24 of the array substrate 20.

Wide view angle mode: referring to fig. 5, 7 and 8, in the embodiment, in the wide viewing angle mode, a reference voltage is applied to the upper electrode 33 of the color filter substrate 30, a first common voltage having a smaller amplitude than the reference voltage is applied to each first common electrode stripe 24a on the array substrate 20 through the first selector 27a, and a second common voltage having a smaller amplitude than the reference voltage is applied to each second common electrode stripe 24b on the array substrate 20 through the second selector 27b, so that voltage differences between all the common electrode stripes 24 and the upper electrode 33 are smaller than a first preset value (for example, smaller than 1V). At this time, since the voltage difference between all the common electrode bars 24 and the upper electrodes 33 is small, the tilt angle of the liquid crystal molecules in the liquid crystal layer 40 hardly changes, and the liquid crystal display device still maintains the lying posture, so that the liquid crystal display device realizes normal wide viewing angle display.

Specifically, in the wide viewing angle mode, the reference voltage applied to the upper electrode 33 may be a constant 0V, the first common voltage applied to each first common electrode bar 24a through the first selector 27a may be the same as the reference voltage, and the second common voltage applied to each second common electrode bar 24b through the second selector 27b may be the same as the reference voltage, that is, the voltage applied to each first common electrode bar 24a and each second common electrode bar 24b is 0V, so that the voltage difference between each common electrode bar 24 and the upper electrode 33 is zero, and a good wide viewing angle effect may be achieved. However, the present embodiment is not limited thereto, and in the wide viewing angle mode, the voltage applied to each of the first and second

common electrode bars

24a and 24b may be a direct current voltage or an alternating current voltage other than 0V, as long as the voltage difference between each of the first common electrode bars 24a and the upper electrode 33 and the voltage difference between each of the second common electrode bars 24b and the upper electrode 33 are made smaller than the first preset value.

Narrow view angle mode: referring to fig. 5, 7 and 9, in the embodiment, in the narrow viewing angle mode, a reference voltage is applied to the upper electrode 33 of the color filter substrate 30, a first common voltage having a larger amplitude than the reference voltage is applied to each first common electrode stripe 24a on the array substrate 20 through the first selector 27a, and a second common voltage having a larger amplitude than the reference voltage is applied to each second common electrode stripe 24b on the array substrate 20 through the second selector 27b, so that voltage differences between all the common electrode stripes 24 and the upper electrode 33 are greater than a second preset value (for example, greater than 2V), where the second preset value is greater than or equal to the first preset value. At this time, since the voltage difference between all the common electrode stripes 24 and the upper electrodes 33 is large, a strong vertical electric field E (as shown by arrows in fig. 9) is generated between the array substrate 20 and the color film substrate 30 in the liquid crystal cell, and the positive liquid crystal molecules rotate in a direction parallel to the electric field lines under the action of the electric field, so that the positive liquid crystal molecules are deflected under the action of the vertical electric field E, the tilt angle between the liquid crystal molecules and the

substrates

20 and 30 is increased and tilted, the liquid crystal molecules are changed from the lying posture to the inclined posture, the liquid crystal display device generates large-angle observation light leakage, the contrast is reduced and the viewing angle is narrowed in the oblique viewing direction, and the liquid crystal display device finally realizes narrow viewing angle display.

Referring to fig. 5, 7 and 10-11, specifically, in the narrow viewing angle mode, the reference voltage applied by the upper electrode 33 may be a constant 0V, the first ac control voltage V1 is applied to the first voltage line 201, the second ac control voltage V2 is applied to the second voltage line 202, the first dc common voltage Vcom + is applied to the third voltage line 203, and the second dc common voltage Vcom + is applied to the fourth voltage line 204. In fig. 10 and 11, Gate (2N-1) represents the odd-numbered scan line 21, Gate (2N) represents the even-numbered scan line 21, V1 represents the first ac control voltage applied to the first voltage line 201, V2 represents the second ac control voltage applied to the second voltage line 202, Q1 represents the node voltage between the second pass terminal of the first switching element T1 and the control terminal of the third switching element T3, Q2 represents the node voltage between the second pass terminal of the second switching element T2 and the control terminal of the fourth switching element T4, Vcom1_ (2N-1) represents the first common voltage waveform charged to each first common electrode bar 24a, and Vcom2_ (2N) represents the second common voltage waveform charged to each second common electrode bar 24 b.

In this embodiment, the first ac control voltage V1 and the second ac control voltage V2 are in inverse complementary relationship, and the first dc common voltage Vcom-and the second dc common voltage Vcom + have the same amplitude but opposite polarity. Also, the polarities of the first ac control voltage V1 and the second ac control voltage V2 are inverted every frame between Vcom-and Vcom +.

In the nth frame, when the scan line Gate (2N-1) outputs a high voltage to the first selector 27a, T2 is turned on, since V2 is a high voltage, Q2 is pulled up by V2, T4 is turned on, and Vcom + is output to the first common electrode bar 24a through T4; when the scan line Gate (2N-1) is turned off, the high voltage of Q2 is stored by Cst2, and T4 remains on to stabilize the first common voltage charged on the first common electrode bar 24 a; during this time, V1 is low, Q1 is pulled low by V1, and T3 is off.

In the nth frame, when the scan line Gate (2N) outputs a high voltage to the second selector 27b, T1 is turned on, Q1 is pulled up by V2 due to V2 being a high voltage, T3 is turned on, and Vcom-is output to the second common electrode bar 24b through T3; when the scan line Gate (2N) is turned off, the high voltage of Q1 is stored by Cst1, and T3 remains on to make the second common voltage charged on the second common electrode bar 24b more stable; during this time, V1 is low, Q2 is pulled low by V1, and T4 is off.

In the (N + 1) th frame, when the scan line Gate (2N-1) outputs a high voltage to the first selector 27a, T1 is turned on, Q1 is pulled up by V1 since V1 is a high voltage, T3 is turned on, and Vcom-is output to the first common electrode bar 24a through T3; when the scan line Gate (2N-1) is turned off, the high voltage of Q1 is stored by Cst1, and T3 remains on to stabilize the first common voltage charged on the first common electrode bar 24 a; during this time, V2 is low, Q2 is pulled low by V2, and T4 is off.

In the (N + 1) th frame, when the scan line Gate (2N) outputs a high voltage to the second selector 27b, T2 is turned on, Q2 is pulled up by V1 due to V1 being a high voltage, T4 is turned on, and Vcom + is output to the second common electrode bar 24b through T4; when the scan line Gate (2N) is turned off, the high voltage of Q2 is stored by Cst2, and T4 remains on to make the second common voltage charged on the second common electrode bar 24b more stable; during this time, V2 is low, Q1 is pulled low by V2, and T3 is off.

The driving method of the (N + 2) th frame is the same as that of the Nth frame, and the process is repeated.

The Cst1 and Cst2 function as storage capacitors, and respectively maintain the voltages at the nodes Q1 and Q2 when the scan line 21 is turned off and the nodes T1 and T2 are turned off, and respectively maintain the on or off states of T3 and T4.

In the present embodiment, with the circuit configuration of the above selector, when the scanning signals are applied to the plurality of scanning lines 21, the plurality of first selectors 27a output the first common voltages to the plurality of first common electrode bars 24a, respectively, and the plurality of second selectors 27b output the second common voltages to the plurality of second common electrode bars 24b, respectively, and the polarities of the first common voltages and the second common voltages are opposite. In the nth frame, the charged first common voltage of each first common electrode stripe 24a is Vcom +, and the charged first common voltage of each second common electrode stripe 24b is Vcom-, which have opposite polarities; in the (N + 1) th frame, the charged first common voltage of each first common electrode stripe 24a is Vcom +, and the charged first common voltage of each second common electrode stripe 24b is Vcom +, which are opposite in polarity; and repeating the process of the N frame picture again by the N +2 frame picture, and circulating the process.

Specifically, in the narrow viewing angle mode, the magnitudes of the first common voltage applied to each first common electrode bar 24a and the second common voltage applied to each second common electrode bar 24b can be selected to be greater than 3V (i.e., | Vcom- | ≧ 3V, | Vcom + | ≧ 3V), e.g., Vcom-equal to-3.6V, Vcom + equal to +3.6V, so that the voltage difference between each common electrode bar 24 and the upper electrode 33 is greater than 3V, and a good narrow viewing angle effect can be achieved.

As shown in fig. 5 and fig. 10 to fig. 11, the liquid crystal display device adopts row inversion (row inversion) during displaying, and the polarity of the data voltage applied to a row of pixel cells covered by each first common electrode bar 24a is the same as the polarity of the first common voltage charged on the first common electrode bar 24a, and the polarity of the data voltage charged to a row of pixel cells covered by each second common electrode bar 24b is the same as the polarity of the second common voltage charged on the second common electrode bar 24 b. Specifically, in the nth frame, when the positive first common voltage Vcom + is charged in each of the first common electrode bars 24a, the positive data voltage is also applied to the pixel cells located in the odd-numbered rows through the data lines 22, and when the negative second common voltage Vcom-is charged in each of the second common electrode bars 24b, the negative data voltage is also applied to the pixel cells located in the even-numbered rows through the data lines 22; in the (N + 1) th frame, when the first common electrode stripes 24a are charged with the first common voltage Vcom-, having the negative polarity, the data lines 22 are used to apply the data voltage having the negative polarity to the pixel cells in the odd-numbered rows, and when the second common electrode stripes 24b are charged with the second common voltage Vcom +, the data lines 22 are used to apply the data voltage having the positive polarity to the pixel cells in the even-numbered rows. And repeating the process of the N frame picture again by the N +2 frame picture, and circulating the process.

As shown in fig. 12, in the present embodiment, each common electrode bar 24 arranged along the row direction is displayed by using row inversion, and the polarity of the common voltage applied to each common electrode bar 24 is the same as the polarity of the data voltage applied to the pixel unit in the row correspondingly covered by the common electrode bar 24, so that the voltage difference between the pixel electrode 23 and the common electrode bar 24 in two adjacent pixel units with different polarities is the same in the upper and lower rows, thereby improving the problem of inconsistent brightness between the two adjacent pixel units. As shown in fig. 13, the display brightness of two adjacent pixel units with different polarities is relatively uniform.

As shown in fig. 8 and 9, the liquid crystal display device further includes a driving circuit 60, and the driving circuit 60 applies required voltage signals to the upper electrode 33 of the color filter substrate 30 and the common electrode stripes 24 of the array substrate 20, respectively. In order to apply voltage signals to the upper electrodes 33 of the color filter substrate 30, the array substrate 20 may be conducted to the color filter substrate 30 through the conductive adhesive 70 in the peripheral non-display region of the display panel 50, the driving circuit 60 provides the voltage signals to the array substrate 20, and the array substrate 20 applies the voltage signals to the upper electrodes 33 of the color filter substrate 30 through the conductive adhesive 70.

As shown in fig. 14a and 14b, the liquid crystal display device is further provided with a viewing angle switching key 80 for switching different viewing angle modes of the liquid crystal display device. The view angle switching key 80 may be a mechanical key (as shown in fig. 14a) or a virtual key (as shown in fig. 14b, set by software control or application program). When a user needs to switch the wide and narrow viewing angles, a viewing angle switching request can be sent to the liquid crystal display device by operating the viewing angle switching key 80, and finally the driving circuit 60 controls voltage signals applied to the upper electrode 33 of the color film substrate 30 and the common electrode strips 24 of the array substrate 20 to realize the switching of the wide and narrow viewing angles, so that the user can freely select and switch the wide and narrow viewing angles according to different peep-proof requirements.

In this embodiment, the voltage for controlling the switching of the wide and narrow viewing angles is switched from the viewing angle control electrode on the color film substrate side to the common electrode stripes 24 on the array substrate side, the common electrode on the array substrate 20 is divided into a plurality of mutually independent common electrode stripes 24, each common electrode stripe 24 is correspondingly connected with one scanning line 21 through one

selector

27a, 27b, when each row of scanning lines 21 is opened, the common electrode stripes 24 covering the pixel units of the row are charged with the common voltage through the

selectors

27a, 27b, so that the common electrode stripes 24 are independently endowed with voltage signals during pixel scanning, the charged common electrode stripes 24 of each row and the common electrode stripes 24 to be charged are not influenced by each other, the voltage signals endowed to the common electrode stripes 24 of each row are not influenced by the charging of the common electrode stripes 24 of the adjacent row, and therefore, the problems of uneven display and flicker in the display panel caused by the coupling effect are improved, the display image quality is improved.

In this embodiment, the polarity of the first common voltage charged in each first common electrode bar 24a is opposite to the polarity of the second common voltage charged in each second common electrode bar 24b, and the polarity of the common voltage applied to each common electrode bar 24 is the same as the polarity of the data voltage (Vdata) applied to the pixel unit in the row covered by the common electrode bar 24, so that when the row inversion is used in combination for displaying, the voltage difference between the pixel electrode 23 and the common electrode bar 24 in two adjacent pixel units with different polarities can be the same, thereby improving the problem of inconsistent brightness of the two adjacent pixel units.

[ second embodiment ]

Referring to fig. 15, the difference between the liquid crystal display device provided in this embodiment and the first embodiment is that, in this embodiment, the plurality of first common electrode bars 24a and the plurality of second common electrode bars 24b are disposed at intervals in the direction of the data line 22: in the direction of the data line 22, every two first common electrode strips 24a and every two second common electrode strips 24b are alternately arranged, that is, the pixel units in the 1 st and 2 nd rows are covered by the first common electrode strips 24a, the pixel units in the 3 rd and 4 th rows are covered by the second common electrode strips 24b, and the arrangement is repeated every four subsequent rows.

Other structures of this embodiment can be seen from the first embodiment, and are not described herein again.

[ third embodiment ]

Referring to fig. 16, the difference between the liquid crystal display device provided in this embodiment and the first embodiment is that, in this embodiment, each pixel unit in each row is connected to the same scan line 21 and controlled by the same scan line 21, and the common electrode bar 24 in each row is connected to the scan line 21 controlling the pixel units in the row through the corresponding selector 27. For example, each pixel cell in the first row is connected to a scan line Gate0 located at the upper side of the pixel cell in the row, and the common electrode bar 24a located in the first row is connected to a scan line Gate0 controlling the pixel cells in the row through the selector 27 a; each pixel cell in the second row is connected to a scan line Gate1 located at the upper side of the pixel cell in the row, and the common electrode bar 24b located in the second row is connected to a scan line Gate1 controlling the pixel cells in the row through the selector 27 b; the connection mode of the pixel units in other rows is similar.

[ fourth embodiment ]

Referring to fig. 17, the difference between the liquid crystal display device provided in this embodiment and the first embodiment is that the common electrode bar 24 in the nth row is connected to the nth-x scanning lines 21 through the corresponding selector 27, where n is an integer greater than or equal to 1, and x may be 1,2, or 3. In the present embodiment, the value of x is taken as 1 for example, that is, each selector 27 is connected to the scanning line of the previous stage, that is, Gn-1 (the selector 27 of the front row may be controlled by the STV signal). Thus, when the scan line Gn-1 is at a high level, the common voltage is charged to the common electrode bar 24 of the nth row by the selector 27 connected to the scan line Gn-1, and when the scan line Gn-1 is at a low level, the charged common voltage to the common electrode bar 24 of the nth row is maintained. Before each pixel unit in the nth row is charged, the Gn-1 scanning line is adopted to control the common electrode strip 24 in the nth row to be charged with the common voltage in advance, so that the phenomenon that after the pixel units in the nth row are charged, the common electrode strip 24 in the nth row is charged with the common voltage to generate coupling influence on the charging voltage of the pixel units in the nth row can be avoided.

That is, it may be selected that the charging of the common electrode bar 24 of the nth row with the common voltage is synchronously completed when the pixel cells of the nth row are charged (as shown in fig. 5 and 15-16), or the charging of the common electrode bar 24 of the nth row with the common voltage is completed in advance before the pixel cells of the nth row are charged (as shown in fig. 17), so that the coupling influence of the charging of the common electrode bar 24 of the nth row with the common voltage after the pixel cells of the nth row are charged on the charging voltage of the pixel cells of the nth row can be avoided.

[ fifth embodiment ]

Referring to fig. 18, the difference between the liquid crystal display device provided in this embodiment and the first embodiment is that, in this embodiment, the first common electrode strip 24a covers the pixel units located at the even-numbered positions in a row correspondingly, and the second common electrode strip 24b covers the pixel units located at the odd-numbered positions in a row correspondingly; alternatively, the first common electrode bar 24a covers the pixel units located at odd bits in one row correspondingly, and the second common electrode bar 24b covers the pixel units located at even bits in one row correspondingly. That is, the pixel cells of an entire row are collectively covered by one first common electrode bar 24a and one second common electrode bar 24 b. For example, for a first row of pixel units, the first common electrode bar 24a corresponds to and covers the pixel units located at even-numbered positions in the first row, and the second common electrode bar 24b corresponds to and covers the pixel units located at odd-numbered positions in the first row; for the second row of pixel units, the first common electrode strip 24a correspondingly covers the pixel units positioned at odd bits in the second row, and the second common electrode strip 24b correspondingly covers the pixel units positioned at even bits in the second row; the above arrangement is repeated every two subsequent rows.

Specifically, referring to fig. 19, each first common electrode bar 24a and each second common electrode bar 24b are formed by connecting a plurality of electrode blocks 240 spaced from each other in series, two adjacent electrode blocks 240 are spaced by a width of one pixel unit, and each electrode block 240 correspondingly covers one pixel unit.

In this embodiment, the first common electrode bar 24a and the second common electrode bar 24b are charged with the common voltages with opposite polarities, so that the dot inversion driving of the pixel unit can be realized, thereby improving the display image quality.

[ sixth embodiment ]

Referring to fig. 20 and 21, the difference between the liquid crystal display device of the present embodiment and the first embodiment is that the liquid crystal layer 40 of the present embodiment uses negative liquid crystal molecules. With the technical progress, the performance of the negative liquid crystal is remarkably improved, and the application is more and more extensive. In the present embodiment, as shown in fig. 20, in the initial state (i.e., the liquid crystal display device is not applied with any voltage), the negative liquid crystal molecules in the liquid crystal layer 40 have a large initial pretilt angle with respect to the

substrates

20 and 30, i.e., the negative liquid crystal molecules are in an inclined posture with respect to the

substrates

20 and 30 in the initial state.

Narrow view angle mode: referring to fig. 20, in the embodiment, in the narrow viewing angle mode, a reference voltage is applied to the upper electrode 33 of the color filter substrate 30, a first common voltage having a smaller amplitude than the reference voltage is applied to each first common electrode stripe 24a on the array substrate 20 through the first selector 27a, and a second common voltage having a smaller amplitude than the reference voltage is applied to each second common electrode stripe 24b on the array substrate 20 through the second selector 27b, so that voltage differences between all the common electrode stripes 24 and the upper electrode 33 are smaller than a first preset value (for example, smaller than 1V). At this time, since the voltage difference between all the common electrode bars 24 and the upper electrodes 33 is small, the tilt angle of the liquid crystal molecules in the liquid crystal layer 40 is almost unchanged and remains in a tilt posture, so that the liquid crystal display device has large-angle viewing light leakage, the contrast ratio is reduced in the oblique viewing direction, and the viewing angle is narrowed, and at this time, the liquid crystal display device realizes narrow viewing angle display.

Specifically, in the narrow viewing angle mode, the reference voltage applied to the upper electrode 33 may be a constant 0V, the first common voltage applied to each first common electrode bar 24a through the first selector 27a may be the same as the reference voltage, and the second common voltage applied to each second common electrode bar 24b through the second selector 27b may be the same as the reference voltage, that is, the voltage applied to each first common electrode bar 24a and each second common electrode bar 24b is 0V, so that the voltage difference between each common electrode bar 24 and the upper electrode 33 is zero, and a good narrow viewing angle effect may be achieved.

Wide view angle mode: referring to fig. 21, in the embodiment, in the wide view angle mode, a reference voltage is applied to the upper electrode 33 of the color filter substrate 30, a first common voltage having a larger amplitude than the reference voltage is applied to each first common electrode stripe 24a on the array substrate 20 through the first selector 27a, and a second common voltage having a larger amplitude than the reference voltage is applied to each second common electrode stripe 24b on the array substrate 20 through the second selector 27b, so that voltage differences between all the common electrode stripes 24 and the upper electrode 33 are greater than a second preset value (for example, greater than 2V), where the second preset value is greater than or equal to the first preset value. At this time, because the voltage difference between all the common electrode stripes 24 and the upper electrodes 33 is large, a strong vertical electric field E (as shown by arrows in fig. 21) is generated in the liquid crystal cell between the array substrate 20 and the color film substrate 30, and because the negative liquid crystal molecules are deflected in the direction perpendicular to the electric field lines under the action of the electric field, the negative liquid crystal molecules are deflected under the action of the vertical electric field E, so that the inclination angle between the liquid crystal molecules and the

substrates

20 and 30 is reduced, the light leakage phenomenon of the liquid crystal display device at an oblique angle is correspondingly reduced, the contrast is improved and the viewing angle is increased in the oblique viewing direction, and the liquid crystal display device finally realizes wide viewing angle display.

Specifically, in the wide viewing angle mode, the reference voltage applied to the upper electrode 33 may be a constant 0V, the first ac control voltage V1 may be applied to the first voltage line 201, the second ac control voltage V2 may be applied to the second voltage line 202, the first dc common voltage Vcom + may be applied to the third voltage line 203, and the second dc common voltage Vcom + may be applied to the fourth voltage line 204. The magnitude of the first common voltage applied to each first common electrode bar 24a by the first selector 27a and the magnitude of the second common voltage applied to each second common electrode bar 24b by the second selector 27b can be selected to be greater than 3V (i.e., | Vcom- | ≧ 3V, | Vcom + | ≧ 3V), e.g., Vcom-equals-3.6V, Vcom + equals +3.6V, so that the voltage difference between each common electrode bar 24 and the upper electrode 33 is greater than 3V, and a good wide viewing angle effect can be achieved.

Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A selector comprising a first switching element (T1), a second switching element (T2), a third switching element (T3), a fourth switching element (T4), a first storage capacitor (Cst1) and a second storage capacitor (Cst2), a control terminal of the first switching element (T1) being connected to a control terminal of the second switching element (T2) for receiving a scan signal, a first path terminal of the first switching element (T1) being arranged to receive one of a first alternating control voltage (V1) and a second alternating control voltage (V2), a first path terminal of the second switching element (T2) being arranged to receive the other of the first alternating control voltage (V1) and the second alternating control voltage (V2), a second path terminal of the first switching element (T1) being connected to a control terminal of the third switching element (T3) and being connected to a first node (Q1), a second path terminal of the second switching element (T2) is connected to the control terminal of the fourth switching element (T4) and to the second node (Q2), a first path terminal of the third switching element (T3) is for receiving a first dc common voltage (Vcom +), a first path terminal of the fourth switching element (T4) is for receiving a second dc common voltage (Vcom +), a second path terminal of the third switching element (T3) is connected to the second path terminal of the fourth switching element (T4) and for outputting a common voltage, the first storage capacitor (Cst1) is connected to the first node (Q1), and the second storage capacitor (Cst2) is connected to the second node (Q2).

2. The selector of claim 1, wherein the first AC control voltage (V1) and the second AC control voltage (V2) are in inverse-phase complementary relationship, and the first DC common voltage (Vcom-) and the second DC common voltage (Vcom +) have the same magnitude but opposite polarity.

3. An array substrate (20), the array substrate (20) being provided with a plurality of scanning lines (21), a plurality of data lines (22), and a plurality of pixel units arranged in an array, the array substrate (20) being further provided with a first voltage line (201), a second voltage line (202), a third voltage line (203), a fourth voltage line (204), a plurality of common electrode bars (24), and a plurality of selectors (27), each common electrode bar (24) extending along the scanning lines (21), the plurality of common electrode bars (24) including a plurality of first common electrode bars (24a) and a plurality of second common electrode bars (24b), the plurality of first common electrode bars (24a) and the plurality of second common electrode bars (24b) being arranged at intervals in the data lines (22), the plurality of selectors (27) including a plurality of first selectors (27a) and a plurality of second selectors (27b), each first common electrode bar (24a) is connected to the first voltage line (201), the second voltage line (202), the third voltage line (203), the fourth voltage line (204) and a corresponding scanning line (21) through a first selector (27a), and each second common electrode bar (24b) is connected to the first voltage line (201), the second voltage line (202), the third voltage line (203), the fourth voltage line (204) and a corresponding scanning line (21) through a second selector (27 b).

4. The array substrate (20) of claim 3, wherein each of the first selector (27a) and the second selector (27b) comprises a first switching element (T1), a second switching element (T2), a third switching element (T3), a fourth switching element (T4), a first storage capacitor (Cst1) and a second storage capacitor (Cst2), a control terminal of the first switching element (T1) is connected to a control terminal of the second switching element (T2) and connected to the corresponding scan line (21), a first pass terminal of the first switching element (T1) is connected to one of the first voltage line (201) and the second voltage line (202), a first pass terminal of the second switching element (T2) is connected to the other of the first voltage line (201) and the second voltage line (202), a second pass terminal of the first switching element (T1) is connected to the control terminal of the second switching element (T3) and connected to the control terminal of the second voltage line (T3) (Q1), a second path terminal of the second switching element (T2) is connected to the control terminal of the fourth switching element (T4) and to a second node (Q2), a first path terminal of the third switching element (T3) is connected to the third voltage line (203), a first path terminal of the fourth switching element (T4) is connected to the fourth voltage line (204), a second path terminal of the third switching element (T3) is connected to the second path terminal of the fourth switching element (T4) and to a corresponding common electrode bar (24), the first storage capacitor (Cst1) is connected to the first node (Q1), and the second storage capacitor (Cst2) is connected to the second node (Q2).

5. The array substrate (20) of claim 4, wherein for each first selector (27a), the first pass terminal of the first switching element (T1) is connected to the first voltage line (201), and the first pass terminal of the second switching element (T2) is connected to the second voltage line (202); for each second selector (27b), the first pass terminal of the first switching element (T1) is connected to the second voltage line (202), and the first pass terminal of the second switching element (T2) is connected to the first voltage line (201).

6. The array substrate (20) of claim 3, wherein each common electrode strip (24) covers an entire row of pixel cells.

7. The array substrate (20) of claim 6, wherein each of the first common electrode stripes (24a) and each of the second common electrode stripes (24b) are alternately arranged with each other in a data line (22) direction; or, in the direction of the data line (22), every two first common electrode stripes (24a) and every two second common electrode stripes (24b) are arranged alternately.

8. The array substrate (20) of claim 3, wherein the first common electrode bar (24a) covers the even numbered pixel cells in a row, and the second common electrode bar (24b) covers the odd numbered pixel cells in a row; or the first common electrode strip (24a) correspondingly covers the pixel units positioned at odd numbers in one row, and the second common electrode strip (24b) correspondingly covers the pixel units positioned at even numbers in one row.

9. The array substrate (20) according to claim 3, wherein each pixel unit in each row is connected to two scanning lines (21) on the upper and lower sides of the pixel unit in the row, and the common electrode bar (24) in each row is connected to the scanning line (21) on the upper side or the lower side of the pixel unit in the row through the corresponding selector (27); or each pixel unit in each row is connected to the same scanning line (21), and the common electrode strip (24) in each row is connected with the scanning line (21) for controlling the pixel units in the row through a corresponding selector (27); or, the pixel units in each row are alternately connected to two scanning lines (21) positioned at the upper side and the lower side of the pixel units in the row, the pixel units in each column are alternately connected to two data lines (22) positioned at the left side and the right side of the pixel units in the column, and the pixel units in each row are charged only through the odd-numbered columns or only through the data lines (22) of the even-numbered columns.

10. The array substrate (20) of claim 3, wherein the common electrode bar (24) in the nth row is connected to the (n-1) th scan line (21) through a corresponding selector (27), where n is an integer greater than 1; or the common electrode strip (24) positioned in the nth row is connected with the (n-2) th scanning line (21) through a corresponding selector (27), wherein n is an integer larger than 2; or the common electrode strip (24) positioned in the nth row is connected with the (n-3) th scanning line (21) through a corresponding selector (27), wherein n is an integer larger than 3; and the common electrode bars (24) not connected to the scanning lines (21) are connected to the STV signal through the corresponding selectors (27).

11. A liquid crystal display device, comprising an array substrate (20), a color filter substrate (30) disposed opposite to the array substrate (20), and a liquid crystal layer (40) disposed between the array substrate (20) and the color filter substrate (30), wherein the array substrate (20) is the array substrate (20) according to any one of claims 3 to 10, and the color filter substrate (30) is provided with an entire upper electrode (33).

12. A driving method for driving the liquid crystal display device according to claim 11, characterized in that the driving method comprises:

in a first viewing angle mode, applying a reference voltage to the upper electrode (33), applying a first common voltage having a smaller magnitude than the reference voltage to each first common electrode bar (24a) through the first selector (27a), and applying a second common voltage having a smaller magnitude than the reference voltage to each second common electrode bar (24b) through the second selector (27b), so that voltage differences between all the common electrode bars (24) and the upper electrode (33) are smaller than a first preset value;

in a second viewing angle mode, applying a reference voltage to the upper electrode (33), applying a first common voltage having a larger magnitude to each first common electrode bar (24a) through the first selector (27a), and applying a second common voltage having a larger magnitude to each second common electrode bar (24b) through the second selector (27b), such that voltage differences between all common electrode bars (24) and the upper electrode (33) are greater than a second preset value; and the second preset value is greater than or equal to the first preset value.

13. A driving method according to claim 12, wherein in the first viewing angle mode, the first common voltage applied to each of the first common electrode stripes (24a) and the second common voltage applied to each of the second common electrode stripes (24b) are the same as the reference voltage.

14. The driving method according to claim 12, wherein in the second viewing angle mode, the first voltage line (201) is applied with a first AC control voltage (V1), the second voltage line (202) is applied with a second AC control voltage (V2), the third voltage line (203) is applied with a first DC common voltage (Vcom-), the fourth voltage line (204) is applied with a second DC common voltage (Vcom +), the first AC control voltage (V1) and the second AC control voltage (V2) are in an inverted complementary relationship, the first DC common voltage (Vcom-) and the second DC common voltage (Vcom +) have the same magnitude but opposite polarity, and when the plurality of scanning lines (21) are applied with scanning signals, respectively, the first common voltage is output to the plurality of first common electrode bars (24a) through the plurality of first selectors (27a), second common voltages are respectively output to the second common electrode bars (24b) through the second selectors (27b), and the polarities of the first common voltages and the second common voltages are opposite.

15. The driving method according to claim 14, wherein the polarity of the charged data voltage of the pixel unit covered by each first common electrode bar (24a) is the same as the polarity of the first common voltage, and the polarity of the charged data voltage of the pixel unit covered by each second common electrode bar (24b) is the same as the polarity of the second common voltage.

16. The driving method according to claim 12, wherein the liquid crystal layer (40) employs positive liquid crystal molecules, the first viewing angle mode is a wide viewing angle mode, and the second viewing angle mode is a narrow viewing angle mode; alternatively, the liquid crystal layer (40) uses negative liquid crystal molecules, and the first viewing angle mode is a narrow viewing angle mode and the second viewing angle mode is a wide viewing angle mode.