CN102855192A - Storage erasing method, storage controller and storage storing device - Google Patents
Storage erasing method, storage controller and storage storing device Download PDFInfo
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Abstract
The invention provides a storage erasing method, a storage controller and a storage storing device. The storage erasing method includes logically grouping entity blocks of a reproducible non-volatile storage module of the storage storing device into a data area and an idle area; configuring an erasing mark for each entity block of the idle area and initially setting each erasing mark as a non-erased state after the storage storing device is powered; and judging whether to perform an erasing instruction to the entity blocks of the idle area or not according to the erasing marks after the storage storing device is in a standby state. Therefore, the storage erasing method can effectively shorten time of entering the standby state when the storage storing device is powered.
Description
Technical field
The present invention relates to a kind of storer erasing method, relate in particular to a kind of Memory Controller and memorizer memory devices of effectively memory cell that stores invalid data being carried out the storer erasing method of the instruction of erasing and using the method.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, so that the consumer is to the also rapidly increase of demand of Storage Media.Because the characteristics such as duplicative nonvolatile memory (rewritable non-volatile memory) has that data are non-volatile, power saving, volume are little, machinery-free structure, read or write speed are fast, be suitable for most portable electronic product, for example notebook computer.Solid state hard disc is exactly a kind of with the storage device of flash memory as Storage Media.Therefore, the flash memory industry becomes a ring quite popular in the electronic industry in recent years.
The storer submodule group of duplicative nonvolatile memory module has a plurality of physical blocks, and each physical blocks has a plurality of physical page (physical page), wherein must be according to the order of physical page data writing in order during data writing in physical blocks.In addition, after must being erased first, the physical page that has been written into data could again be used for data writing.Particularly, physical blocks is the least unit of erasing, and physical page is the programming minimum unit of (also claiming to write).Therefore, in the management of flash memory module, physical blocks can be divided into data field (data area) and idle district (free area).
The physical blocks of data field (also being called the data entity block) is storage data and be mapped to the physical blocks of logical block.Specifically, the logic access address that the memory management circuitry of memorizer memory devices can be wanted host computer system to write is converted to the logical page (LPAGE) of logical blocks, and the data of wanting to write are write to the physical page of some physical blocks and the logical page (LPAGE) of this logical block is shone upon the so far physical page of physical blocks.That is to say that in the management of duplicative nonvolatile memory module, the physical blocks of data field is the physical blocks (for example, having stored the data that host computer system writes) that is regarded as being used.For example, memory management circuitry can be put down in writing the mapping relations of the physical blocks of logical blocks and data field with logical blocks-physical blocks mapping table, and wherein the logical page (LPAGE) in the logical blocks is the physical page of the physical blocks of shining upon of correspondence sequentially.
The physical blocks (also being called idle physical blocks) in idle district is the physical blocks in the data field of rotating.Specifically, as mentioned above, the physical blocks of written data must be erased just can be used for data writing again afterwards, and therefore, the idle physical blocks of distinguishing is to be designed to write more new data to replace the physical blocks of original mapping logic block.
That is to say that in the management of duplicative nonvolatile memory module, the data field is the logical page (LPAGE) that the mode of rotating is come the mapping logic block with the physical page of the physical blocks in idle district, to store the data that host computer system was write.Particularly, in the operation of memorizer memory devices, may cause because of abnormal power-down to write failure and so that the physical blocks in idle district has incomplete data.Therefore, in present design, the Memory Controller of memorizer memory devices can the physical blocks to idle district be carried out the instruction of erasing when power initiation, to guarantee that the physical blocks in the idle district is erased all, avoid thus causing the mistake of overprogram (double programming).
Yet along with the capacity of duplicative nonvolatile memory module is increasing, the time of all physical blocks in the idle district being carried out the instruction of erasing is also more and more longer.Therefore, the user must wait for that still considerable time could the access memory storage device after starting memorizer memory devices.
Summary of the invention
The invention provides a kind of storer erasing method and Memory Controller, it can effectively shorten memorizer memory devices and enter the time of awaiting orders behind power initiation.
The invention provides a kind of memorizer memory devices, it can enter armed state rapidly behind power initiation.
One example of the present invention embodiment provides a kind of storer erasing method, is used for the duplicative nonvolatile memory module of memorizer memory devices, and wherein this duplicative nonvolatile memory module has a plurality of physical blocks.This storer erasing method comprises that these physical blocks logically are grouped into the data field at least to be distinguished with idle; And be erased status not for erase mark and the flag settings of initially each being erased of each physical blocks configuration one in idle district at memorizer memory devices afterwards by power initiation (power on).
In one embodiment of this invention, above-mentioned storer erasing method also comprises: when extracting the first instance block among the physical blocks in idle district, judge that erasing of first instance block marks whether to be set to not erased status; And when the mark of erasing of first instance block is set to not erased status, to the erase instruction and the mark of erasing of first instance block is reset to erased status of first instance onblock executing.
In one embodiment of this invention, above-mentioned storer erasing method also comprises: judge whether do not receive any instruction that comes from host computer system after the schedule time; And if when after this schedule time, not receiving any instruction that comes from host computer system, then to erase instruction and the mark of erasing of second instance block is reset to erased status of the second instance onblock executing among the physical blocks in idle district.
In one embodiment of this invention, above-mentioned storer erasing method also comprises: the mark of erasing of the physical blocks in the district of will leaving unused is stored in the memory buffer of memorizer memory devices.
One example of the present invention embodiment provides a kind of storer erasing method, is used for the duplicative nonvolatile memory module of memorizer memory devices, and wherein duplicative nonvolatile memory module has a plurality of physical blocks.This storer erasing method comprises that these physical blocks logically are grouped into the data field at least to be distinguished with idle.This storer erasing method also comprises according to the physical blocks in idle district to be set up link (link) inventory and linked list is stored in the duplicative nonvolatile memory module, and wherein the physical blocks in idle district is to put in order according to one to be recorded in the linked list.This storer erasing method also is included in memorizer memory devices by after the power initiation, select a plurality of the 3rd physical blocks and respectively these a little the 3rd physical blocks are carried out the instruction of erasing among those physical blocks in idle district according to this linked list and predetermined number, wherein the 3rd physical blocks is to be arranged in foremost in the linked list and the number of the 3rd physical blocks is above-mentioned predetermined number.
In one embodiment of this invention, above-mentioned storer erasing method also comprises: when wish is used the physical blocks in idle district, extract in order the physical blocks in idle district according to linked list.
In one embodiment of this invention, above-mentioned storer erasing method also comprises: when the 4th physical blocks among the physical blocks of data field being associated to idle district, the 4th physical blocks is carried out the instruction and the 4th physical blocks is recorded in the linked list backmost of erasing.
One example of the present invention embodiment provides a kind of Memory Controller, and in order to control duplicative nonvolatile memory module, wherein this duplicative nonvolatile memory module has a plurality of physical blocks.This Memory Controller comprises host interface, memory interface and memory management circuitry.Host interface is in order to be electrically connected to host computer system.Memory interface is in order to be electrically connected so far duplicative nonvolatile memory module.Memory management circuitry is electrically connected so far host interface and memory interface, and in order to these physical blocks logically are grouped at least data field and idle district.In addition, after memory management circuitry was by power initiation, memory management circuitry was erased status not for erase mark and the flag settings of initially each being erased of each physical blocks configuration in idle district.
In one embodiment of this invention, when extracting the first instance block among the physical blocks in idle district, then above-mentioned memory management circuitry can judge that erasing of first instance block marks whether to be set to not erased status.And when the mark of erasing of first instance block was set to not erased status, above-mentioned memory management circuitry can be to the erase instruction and the mark of erasing of first instance block is reset to erased status of first instance onblock executing.
In one embodiment of this invention, above-mentioned memory management circuitry judges whether do not receive any instruction that comes from host computer system after the schedule time.And, if when not receiving any instruction that comes from host computer system after the schedule time, then above-mentioned memory management circuitry is to erase instruction and the mark of erasing of second instance block is reset to erased status of the second instance onblock executing among the physical blocks in idle district.
In one embodiment of this invention, above-mentioned Memory Controller also comprises a memory buffer, and wherein will the leave unused mark of erasing of physical blocks in district of above-mentioned memory management circuitry is stored in this memory buffer.
One example of the present invention embodiment provides a kind of Memory Controller, and in order to control duplicative nonvolatile memory module, wherein this duplicative nonvolatile memory module has a plurality of physical blocks.This Memory Controller comprises host interface, memory interface and memory management circuitry.Host interface is in order to be electrically connected to host computer system.Memory interface is in order to be electrically connected so far duplicative nonvolatile memory module.Memory management circuitry is electrically connected so far host interface and memory interface, and in order to these physical blocks logically are grouped at least data field and idle district.In addition, memory management circuitry is set up link (link) inventory according to the physical blocks in idle district and this linked list is stored in the duplicative nonvolatile memory module, and wherein the physical blocks in idle district is to put in order according to one to be recorded in the linked list.Moreover, after memory management circuitry is by power initiation, memory management circuitry is selected a plurality of the 3rd physical blocks and respectively these a little the 3rd physical blocks is carried out the instruction of erasing among the physical blocks in idle district according to linked list and predetermined number, and wherein the 3rd physical blocks is to be arranged in foremost in the linked list and the number of the 3rd physical blocks is above-mentioned predetermined number.
In one embodiment of this invention, when wish was used the physical blocks in idle district, memory management circuitry was extracted the physical blocks in idle district in order according to linked list.
In one embodiment of this invention, when memory management circuitry was associated to idle district with the 4th physical blocks among the physical blocks of data field, above-mentioned memory management circuitry can be carried out the instruction and the 4th physical blocks is recorded in the linked list backmost of erasing to the 4th physical blocks.
One example of the present invention embodiment provides a kind of memorizer memory devices, and it comprises connector, duplicative nonvolatile memory module and Memory Controller.Connector is in order to be electrically connected to host computer system.Duplicative nonvolatile memory module has a plurality of physical blocks.Memory Controller is electrically connected to duplicative nonvolatile memory module, and in order to these physical blocks logically are grouped at least data field and idle district.In addition, Memory Controller is by after the power initiation, and Memory Controller is erased status not for erase mark and the flag settings of initially each being erased of each physical blocks configuration in idle district.
In one embodiment of this invention, when extracting the first instance block among the physical blocks in idle district, above-mentioned Memory Controller can judge that erasing of first instance block marks whether to be set to not erased status.And when the mark of erasing of first instance block was set to not erased status, above-mentioned Memory Controller can be to the erase instruction and the mark of erasing of first instance block is reset to erased status of first instance onblock executing.
In one embodiment of this invention, above-mentioned Memory Controller judges whether do not receive any instruction that comes from host computer system after the schedule time.And, if when not receiving any instruction that comes from host computer system after the schedule time, above-mentioned Memory Controller is to erase instruction and the mark of erasing of second instance block is reset to erased status of the second instance onblock executing among the physical blocks in idle district.
In one embodiment of this invention, will the leave unused mark of erasing of physical blocks in district of above-mentioned Memory Controller is stored in the memory buffer.
One example of the present invention embodiment provides a kind of memorizer memory devices, and it comprises connector, duplicative nonvolatile memory module and Memory Controller.Connector is in order to be electrically connected to host computer system.Duplicative nonvolatile memory module has a plurality of physical blocks.Memory Controller is electrically connected to duplicative nonvolatile memory module, and in order to these physical blocks logically are grouped at least data field and idle district.In addition, Memory Controller is set up linked list according to the physical blocks in idle district and this linked list is stored in the duplicative nonvolatile memory module, and wherein the physical blocks in idle district is to put in order according to one to be recorded in the linked list.In addition, after Memory Controller is by power initiation, Memory Controller is selected a plurality of the 3rd physical blocks and respectively these a little the 3rd physical blocks is carried out the instruction of erasing among the physical blocks in idle district according to linked list and predetermined number, and wherein the 3rd physical blocks is to be arranged in foremost in the linked list and the number of the 3rd physical blocks is above-mentioned predetermined number.
In one embodiment of this invention, when wish was used the physical blocks in idle district, above-mentioned Memory Controller extracted the physical blocks in idle district in order according to linked list.
In one embodiment of this invention, when the 4th physical blocks among the physical blocks of data field being associated to idle district, above-mentioned Memory Controller can be carried out the instruction and the 4th physical blocks is recorded in the linked list backmost of erasing to the 4th physical blocks.
Based on above-mentioned, storer erasing method, Memory Controller and the memorizer memory devices of exemplary embodiment of the present invention can effectively shorten the time that enters armed state after power initiation and effectively avoid the mistake of overprogram (double programming).
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate accompanying drawing to be described in detail below.
Description of drawings
Figure 1A is according to host computer system and the memorizer memory devices shown in the first exemplary embodiment.
Figure 1B is the synoptic diagram of the computing machine shown in the exemplary embodiment, input/output device and memorizer memory devices according to the present invention.
Fig. 1 C is the synoptic diagram of the host computer system shown in another exemplary embodiment and memorizer memory devices according to the present invention.
Fig. 2 is the summary block scheme according to the memorizer memory devices shown in the first exemplary embodiment.
Fig. 3 is the summary block scheme according to the Memory Controller shown in the first exemplary embodiment.
Fig. 4 A and Fig. 4 B are the synoptic diagram according to the physical blocks of the duplicative of management shown in the first exemplary embodiment nonvolatile memory module.
Fig. 5 is the example of erasing and showing according to the idle physical blocks shown in the first exemplary embodiment.
Fig. 6 is the process flow diagram according to the storer erasing method shown in the first exemplary embodiment.
Fig. 7 is the process flow diagram according to the storer erasing method shown in the second exemplary embodiment.
Fig. 8 is the example according to the linked list shown in the 3rd exemplary embodiment.
Fig. 9 is the process flow diagram according to the storer erasing method shown in the 3rd exemplary embodiment.
Reference numeral:
1000: host computer system
1100: computing machine
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: Portable disk
1214: memory card
1216: solid state hard disc
1310: digital camera
The 1312:SD card
The 1314:MMC card
1316: memory stick
The 1318:CF card
1320: embedded storage device
100: memorizer memory devices
102: connector
104: Memory Controller
106: duplicative nonvolatile memory module
202: memory management circuitry
204: host interface
206: memory interface
252: memory buffer
254: electric power management circuit
256: bug check and correcting circuit
502: the data field
504: idle district
506: system region
508: replace the district
410 (0)～410 (N): physical blocks
610 (0)～610 (H): logical blocks
710 (0)～710 (K): logic access address
600: the idle physical blocks table of erasing
S601, S603, S605, S607, S609, S611: the step of storer erasing method
S701, S703, S705, S707, S709, S711, S713, S715, S717: the step of storer erasing method
800: linked list
S901, S903, S905: the step of storer erasing method
Embodiment
Storer erasing method proposed by the invention is when power initiation (power on), just make memorizer memory devices enter armed state after only first the physical blocks in idle district being carried out just making memorizer memory devices enter armed state behind the mark or only the part physical blocks in the idle district carried out the instruction of erasing, avoid thus tackling a large amount of physical blocks and carry out erase instruction and the startup of delay memory storage device.In order to more clearly understand the present invention, below describe with several exemplary embodiment.
[the first exemplary embodiment]
Generally speaking, memorizer memory devices (also claiming memory storage system) comprises duplicative nonvolatile memory module and controller (also claiming control circuit).Usually memorizer memory devices is to use with host computer system, so that host computer system can write to data memorizer memory devices or reading out data from memorizer memory devices.
Figure 1A is according to host computer system and the memorizer memory devices shown in the first exemplary embodiment.
Please refer to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 such as Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memorizer memory devices 100 is to be electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memorizer memory devices 100 or reading out data from memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106.For example, memorizer memory devices 100 can be the duplicative non-volatile memory storage device of Portable disk 1212, memory card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 1B.
Generally speaking, host computer system 1000 can be any system that can cooperate with memorizer memory devices 100 with storage data substantially.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.For example, be digital camera (video camera) 1310 o'clock in host computer system, duplicative non-volatile memory storage device then is its employed SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (shown in Fig. 1 C).Embedded storage device 1320 comprises embedded multimedia card (Embedded MMC, eMMC).It is worth mentioning that embedded multimedia card is directly to be electrically connected on the substrate of host computer system.
Fig. 2 is the summary block scheme according to the memorizer memory devices shown in the first exemplary embodiment.
Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and duplicative nonvolatile memory module 106.
In this exemplary embodiment, connector 102 is to be compatible to Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard.Yet, it must be appreciated, the invention is not restricted to this, connector 102 can also be to meet Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment, PATA) standard, USB (universal serial bus) (Universal Serial Bus, USB) standard, safe digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (MultiMedia Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form drives electrical interface (Integrated Device Electronics, IDE) standard or other standards that is fit to.
Duplicative nonvolatile memory module 106 is to be electrically connected to Memory Controller 104, and has the data that a plurality of physical blocks are write to store host computer system 1000.In this exemplary embodiment, each physical blocks has respectively a plurality of physical page, and the physical page that wherein belongs to same physical blocks can be write and side by side be erased independently.For example, each physical blocks is comprised of 128 physical page, and the capacity of each physical page is 4 kilobit tuples (Kilobyte, KB).Yet, it must be appreciated that the invention is not restricted to this, each physical blocks can be comprised of 64 physical page, 256 physical page or other arbitrarily individual physical page.
In more detail, physical blocks is the least unit of erasing.That is each physical blocks contains the storage unit of being erased in the lump of minimal amount.Physical page is the minimum unit of programming.That is, physical page is the minimum unit of data writing.Yet, it must be appreciated that in another exemplary embodiment of the present invention, the least unit of data writing can also be entity sector or other sizes.Each physical page generally includes data bit element district and redundant bit district.The data bit element district is in order to storing user's data, and redundant bit district is in order to the data (for example, bug check and correcting code) of stocking system.
In this exemplary embodiment, duplicative nonvolatile memory module 106 is multi-level cell memory (Multi Level Cell, MLC) NAND flash memory module.Yet, the invention is not restricted to this, also single-order storage unit (Single Level Cell, SLC) NAND flash memory module, other flash memory modules or other have the memory module of identical characteristics to duplicative nonvolatile memory module 106.
Fig. 3 is the summary block scheme according to the Memory Controller shown in the first exemplary embodiment.
Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
In this exemplary embodiment, the steering order of memory management circuitry 202 is to come implementation with the firmware pattern.For example, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and these a little steering orders are to be burned onto in this ROM (read-only memory).When memorizer memory devices 100 running, these a little steering orders can be carried out to carry out by microprocessor unit the runnings such as writing, read and erase of data.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also the program pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the memory module) of duplicative nonvolatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has the code of driving section, and when Memory Controller 104 was enabled, microprocessor unit can be carried out first this driving code section steering order that will be stored in the duplicative nonvolatile memory module 106 and be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can turn round these a little steering orders to carry out the runnings such as writing, read and erase of data.In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also a hardware pattern be come implementation.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises memory buffer 252.Memory buffer 252 is to be electrically connected to memory management circuitry 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from duplicative nonvolatile memory module 106.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises electric power management circuit 254.Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and in order to the power supply of control store storage device 100.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises bug check and correcting circuit 256.Bug check and correcting circuit 256 be electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives from host computer system 1000 when writing instruction, bug check can produce corresponding bug check and correcting code (Error Checking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 256, ECC Code), and memory management circuitry 202 the corresponding data that this writes instruction can be write in the duplicative nonvolatile memory module 106 with corresponding bug check and correcting code.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code during reading out data simultaneously from duplicative nonvolatile memory module 106, and bug check and correcting circuit 256 can be according to this bug check and correcting code data execution error inspection and the correction program to reading.
Fig. 4 A and Fig. 4 B are the synoptic diagram according to the physical blocks of the duplicative of management shown in the first exemplary embodiment nonvolatile memory module.
Please refer to Fig. 4 A, duplicative nonvolatile memory module 106 has physical blocks 410 (0)～410 (N), and the memory management circuitry 202 of Memory Controller 104 can logically be grouped into physical blocks 410 (0)～410-(N) data field (data area) 502, idle district (free area) 504, system region (system area) 506 and replace district (replacement area) 508.
The physical blocks that belongs in logic data field 502 and idle district 504 is the data that come from host computer system 1000 in order to storage.Specifically, the physical blocks of data field 502 (also being called the data entity block) is to be regarded as the physical blocks of storage data, and the physical blocks (also being called idle physical blocks) in idle district 504 is the physical blocks that write new data.For example, when receiving the data that write instruction and want to write from host computer system 1000, memory management circuitry 202 can be extracted physical blocks as daily record (log) physical blocks from idle district 504, and data are write in the so far daily record physical blocks.Again for example, when to a certain logical blocks executing data consolidation procedure, memory management circuitry 202 can be extracted physical blocks and come data writing as the new data physical blocks of corresponding this logical blocks from idle district 504, and replaces the data entity block of original this logical blocks of mapping.Particularly, after finishing the data consolidation procedure, this stores the data entity block of invalid data or daily record physical blocks a bit can be by again related (or recovery) to idle district 504, with as the usefulness that writes new data next time.
The physical blocks that belongs in logic system region 506 is in order to the register system data.For example, system data comprises about the manufacturer of duplicative nonvolatile memory module and model, the physical blocks number of duplicative nonvolatile memory module, physical page number of each physical blocks etc.
Belonging in logic the physical blocks that replaces in the district 508 is to replace program for bad physical blocks, with replacing damaged physical blocks.Specifically, if when replacing the physical blocks damage that still has normal physical blocks and data field 502 in the district 508, memory management circuitry 202 can be extracted the physical blocks that normal physical blocks is changed damage from replace district 508.
Based on above-mentioned, in the running of memorizer memory devices 100, data field 502, idle district 504, system region 506 can dynamically change with the physical blocks that replaces district 508.For example, the physical blocks in order to the storage data of rotating can belong to data field 502 or idle district 504 with changing.
It is worth mentioning that in this exemplary embodiment, memory management circuitry 202 is to manage take each physical blocks as unit.Yet, the invention is not restricted to this, in another exemplary embodiment, memory management circuitry 202 also can be grouped into physical blocks a plurality of solid elements, and manages take solid element as unit.For example, each solid element can be comprised of at least one physical blocks in same storer submodule group or the different memory submodule group.
Please refer to Fig. 4 B, memory management circuitry 202 can configuration logic blocks 610 (0)～610 (H) with the physical blocks in mapping (enum) data district 502, wherein each logical blocks has a plurality of logical page (LPAGE)s and this a little logical page (LPAGE)s are the physical page of shining upon in order corresponding data entity block.For example, when memorizer memory devices 100 was formatted, logical blocks 610 (0)～610 (H) is the physical blocks 410 (0)～410 (F-1) in mapping (enum) data district 502 initially.
In exemplary embodiment of the present invention, memory management circuitry 202 meeting service logic block-physical blocks mapping tables (logical block-physical block mapping table) are with the mapping relations between the physical blocks of record logical blocks 610 (0)～610 (H) and data field 502.In addition, because host computer system 1000 with the logic access address (for example is, sector (Sector)) for unit comes access data, memory management circuitry 202 can convert the logic access address 710 (0)～710 (K) of corresponding stored device storage device 100 to corresponding logical page (LPAGE) when host computer system 1000 access data.For example, when host computer system 1000 is wanted a certain logic of access access address, memory management circuitry 202 can be converted to the logic access address of 1000 accesses of host computer system the multi-dimensional address that logical blocks and logical page (LPAGE) with correspondence are consisted of, and passes through logical blocks-physical blocks mapping table access data in the physical page of correspondence.
In this exemplary embodiment, at memorizer memory devices 100 by power initiation (power on) afterwards, memory management circuitry 202 can be each physical blocks configuration one in idle district 504 mark of erasing.
For example, when memorizer memory devices 100 was enabled, memory management circuitry 202 can carry out relevant initialization operations so that memorizer memory devices 100 enters can receive and the armed state of processing the instruction that comes from host computer system 1000.Carry out this initialization operation during, memory management circuitry 202 can set up an idle physical blocks erase table (idle physical blocks as shown in Figure 5 erase table 600) with erase mark and the flag settings of initially idle all that distinguish 504 physical blocks of correspondence being erased of each physical blocks of recording corresponding idle district 504 for erased status not.
Particularly, during this initialization operation of execution, memory management circuitry 202 can not carried out the instruction of erasing to the physical blocks in idle district 504, shortens thus memorizer memory devices 100 and enters and can receive the time required with the armed state of processing the instruction that comes from host computer system 1000.
For example, memorizer memory devices 100 enter can receive with the armed state of processing the instruction that comes from host computer system 1000 after, memory management circuitry 202 both can have been come according to the instruction of host computer system 1000 the non-volatile note phantom of access duplicative group 106.Particularly, when coming data writing from the physical blocks of extracting idle district 504, memory management circuitry 202 can judge that corresponding erasing of physical blocks of extracting marks whether to be set to not erased status.When if the mark of erasing of the corresponding physical blocks of extracting is set to not erased status, memory management circuitry 202 can so far be carried out this physical blocks before the physical blocks at data writing and erase instruction and the mark of erasing of corresponding this physical blocks is reset to erased status.
For example, in idle physical blocks was erased the mark of erasing of table 600, " 0 " represented that not erased status and " 1 " represent erased status, but the invention is not restricted to this.In addition, in this exemplary embodiment, memory management circuitry 202 only can be erased the physical blocks of leaving unused, and table 600 is stored in the memory buffer 254 and upgrade constantly this mark of erasing during memorizer memory devices 100 runnings.That is to say, when memorizer memory devices 100 power initiation, idle physical blocks erase that table 600 can be established again and during the running of memorizer memory devices 100 memory management circuitry 202 can determine whether the physical blocks in idle district 504 is carried out the instruction of erasing according to this mark of erasing a bit.The base this, the memorizer memory devices 100 of this exemplary embodiment and Memory Controller 104 thereof enter the required time of armed state in the time of can effectively shortening power initiation, simultaneously also can guarantee can not occur to carry out the mistake of overprogram to there is the physical blocks of deficiency of data because of abnormal power-down.
Fig. 6 is the process flow diagram according to the storer erasing method shown in the first exemplary embodiment.
Please refer to Fig. 6, in step S601, memory management circuitry 202 can logically be grouped into the physical blocks of duplicative nonvolatile memory module 106 data field 502, idle district 504, system region 506 and replace district 508.It must be appreciated, although in exemplary embodiment of the present invention, physical blocks can logically be grouped into data field 502, idle district 504, system region 506 and be replaced district 508, yet, in another illustrative examples of the present invention, physical blocks can only be grouped into data field 502 and idle district 504.
In step S603, erase mark and the flag settings of initially each being erased that can be set up each physical blocks in corresponding idle district 504 at memorizer memory devices 100 by memory management circuitry after the power initiation 202 are erased status not.
Afterwards, in step S605, memory management circuitry 202 can judge whether that need to extract physical blocks from idle district 504 carries out the instruction that comes from host computer system 1000.
If in the time of need not extracting physical blocks from idle district 504, then in step S607, memory management circuitry 202 can be carried out the instruction of host computer system 1000.And afterwards, step S605 can be performed.
If in the time of need to from idle district 504, extracting physical blocks, in step S609, memory management circuitry 202 can be extracted physical blocks (hereinafter referred to as the first instance block) and judge that erasing of first instance block marks whether to be set to not erased status from idle district 504.
If when the mark of erasing of first instance block was not set to not erased status, then step S607 can be performed.When if the mark of erasing of first instance block is set to not erased status, then in step S611, memory management circuitry 202 can be to the erase instruction and the mark of erasing of first instance block is reset to erased status of first instance onblock executing.Afterwards, step S607 can be performed.
[the second exemplary embodiment]
The difference part of the second exemplary embodiment and the first exemplary embodiment only is that Memory Controller 104 can when host computer system 1000 continues not assign any instruction, begin the physical blocks in idle district 504 is carried out the instruction of erasing.Base this, can more effectively shorten and carry out the time write instruction and the usefulness that promotes memorizer memory devices 1000.Below will utilize the diagram of the first exemplary embodiment, only the difference part of the second exemplary embodiment and the first exemplary embodiment will be described.
In the second exemplary embodiment, when memorizer memory devices 100 entered armed state and continue not receive instruction from host computer system 1000, memory management circuitry 202 can begin the physical blocks in idle district 504 carried out erased instruction and the erased mark of erasing of physical blocks of correspondence is reset to erased status.
For example, memory management circuitry 202 comprises a timer (not shown) and when memorizer memory devices 100 entered armed state, this timer can begin timing.If (for example arrive the schedule time at timer, 3 seconds) afterwards, when memorizer memory devices 100 does not receive any instruction that comes from host computer system 1000 yet, memory management circuitry 202 can be selected the physical blocks running of erasing from idle district 504, until receive the instruction that comes from host computer system 1000.That is to say, memory management circuitry 202 can utilize need not to process the instruction that comes from host computer system 1000 during, the physical blocks in idle district 504 carried out erases instruction and the erased mark of erasing of physical blocks of correspondence is reset to erased status.If before timer arrives the schedule time or the physical blocks in idle district 504 is being carried out when erasing that memorizer memory devices 100 receives the instruction that comes from host computer system 1000 between order period, memory management circuitry 202 can be carried out this instruction and replacement timer (for example, timer being made zero).
Fig. 7 is the process flow diagram according to the storer erasing method shown in the second exemplary embodiment.
Please refer to Fig. 7, in step S701, memory management circuitry 202 can logically be grouped into the physical blocks of duplicative nonvolatile memory module 106 data field 502, idle district 504, system region 506 and replace district 508.It must be appreciated, although in exemplary embodiment of the present invention, physical blocks can logically be grouped into data field 502, idle district 504, system region 506 and be replaced district 508, yet, in another illustrative examples of the present invention, physical blocks can only be grouped into data field 502 and idle district 504.
In step S703, erase mark and the flag settings of initially each being erased that can be set up each physical blocks in corresponding idle district 504 at memorizer memory devices 100 by memory management circuitry after the power initiation 202 are erased status not.
Afterwards, in step S705, memory management circuitry 202 can judge whether not receive any instruction that comes from host computer system 1000 at predetermined time period.
If when predetermined time period does not receive any instruction that comes from host computer system 1000, then in step S707, memory management circuitry 202 can be labeled as to erasing in the idle district 504 the part physical blocks of erased status (hereinafter referred to as the second instance block) not and carry out and erase instruction and the mark of erasing of second instance block is reset to erased status.
Afterwards, in step S709, memory management circuitry 202 can judge whether to receive any instruction that comes from host computer system 1000.
If when not receiving any instruction that comes from host computer system 1000, then step S707 can be performed.If when receiving the instruction that comes from host computer system 1000, in step S711, memory management circuitry 202 can judge whether that need to extract physical blocks from idle district 504 carries out this instruction.
If in the time of need not extracting physical blocks from idle district 504, then in step S713, memory management circuitry 202 can be carried out the instruction of host computer system 1000.And afterwards, step S707 can be performed.If in the time of need to from idle district 504, extracting physical blocks, in step S715, memory management circuitry 202 can be extracted physical blocks (hereinafter referred to as the first instance block) and judge that erasing of first instance block marks whether to be set to not erased status from idle district 504.
If when the mark of erasing of first instance block was not set to not erased status, then step S713 can be performed.When if the mark of erasing of first instance block is set to not erased status, then in step S717, memory management circuitry 202 can be to the erase instruction and the mark of erasing of first instance block is reset to erased status of first instance onblock executing.Afterwards, step S713 can be performed.
If when predetermined time period receives any instruction that comes from host computer system 1000, then step S711 can be performed.
[the 3rd exemplary embodiment]
The hardware structure of the 3rd exemplary embodiment is the hardware structure that is similar to the first exemplary embodiment, below utilizes Figure 1A, Fig. 2, Fig. 3, Fig. 4 A and Fig. 4 B of the first exemplary embodiment that the 3rd exemplary embodiment is described.
In this exemplary embodiment, memory management circuitry 202 meetings of Memory Controller 104 are set up linked list (link list) and are used idle 504 the physical blocks of distinguishing according to this linked list according to the physical blocks in idle district 504.
Fig. 8 is the example according to the linked list shown in the 3rd exemplary embodiment.
Please refer to Fig. 8, when memorizer memory devices 100 initialization (for example, format), memory management circuitry 202 can will be left unused the physical blocks 410 (F)～410 (S-1) in district 504 with the series winding that puts in order.At this moment, the physical blocks that records in the linked list 800 is all not storage data.
Afterwards, when need extracted physical blocks from idle district 504, memory management circuitry 202 can be extracted physical blocks according to linked list 800, was arranged in wherein that top physical blocks can be extracted first in the linked list.And, to write fashionablely when finishing, the physical blocks of extracting can remove from linked list 800.In addition, when the physical blocks that will store invalid data (hereinafter referred to as the 4th physical blocks) was recycled to idle district 504, memory management circuitry 202 can be carried out the 4th physical blocks and erase instruction and the 4th physical blocks come linked list 800 backmost.
It is worth mentioning that, in this exemplary embodiment, whenever memorizer memory devices 100 during by power initiation, memory management circuitry 202 only can be carried out the instruction of erasing to the physical blocks that is arranged in top predetermined number in the linked list 800, shortens thus memorizer memory devices 100 and is entered the required time of armed state behind the power initiation.
Specifically, as mentioned above, memorizer memory devices 100 may write failure because abnormal power-down causes, and the physical blocks that is being written into may have incomplete data.In this exemplary embodiment, because the physical blocks in idle district 504 is to be extracted according to linked list 800, therefore, only have that top several physical blocks may have deficiency of data in the linked list 800 of arrangement.Base this, in this exemplary embodiment, whenever memorizer memory devices 100 during by power initiation, memory management circuitry 202 is only carried out the instruction of erasing to being arranged in the linked list 800 top several physical blocks, can avoid the mistake of overprogram.
In this exemplary embodiment, above-mentioned predetermined number is to set according to the number that memory management circuitry 202 can simultaneously treated physical blocks.That is to say, when abnormal power-down, all may the producing write error of these a little simultaneously treated physical blocks and have incomplete data.For example, above-mentioned predetermined number is set to 6, but the invention is not restricted to this.
It is worth mentioning that in this exemplary embodiment, linked list 800 can be stored in the duplicative nonvolatile memory module 106 (for example, system region 506).When memorizer memory devices 100 during by power initiation, memory management circuitry 202 can be loaded into memory buffer 252 with linked list 800, is beneficial to upgrade.Afterwards, when receiving the power-off signal, memory management circuitry 202 can restore to linked list 800 in the duplicative nonvolatile memory module 106.
Fig. 9 is the process flow diagram according to the storer erasing method shown in the 3rd exemplary embodiment.
Please refer to Fig. 9, in step S901, memory management circuitry 202 can logically be grouped into the physical blocks of duplicative nonvolatile memory module 106 data field 502, idle district 504, system region 506 and replace district 508.It must be appreciated, although in exemplary embodiment of the present invention, physical blocks can logically be grouped into data field 502, idle district 504, system region 506 and be replaced district 508, yet, in another illustrative examples of the present invention, physical blocks can only be grouped into data field 502 and idle district 504.
In step S903, memory management circuitry 202 meetings are set up linked list 800 according to the physical blocks in idle district 504 and linked list 800 are stored in the duplicative nonvolatile memory module 106.
In step S905, after memorizer memory devices 100 was by power initiation, memory management circuitry 202 can be selected several physical blocks (hereinafter referred to as several the 3rd physical blocks) and respectively several the 3rd physical blocks be carried out the instruction of erasing among the physical blocks in idle district 504 according to linked list 800 and predetermined number.At this, the number of several the 3rd physical blocks is to equal above-mentioned predetermined number.
In sum, storer erasing method, Memory Controller and the memorizer memory devices of above-mentioned exemplary embodiment only carries out mark to the physical blocks in idle district after power initiation, can effectively shorten the time that enters armed state after power initiation thus.In addition, storer erasing method, Memory Controller and the memorizer memory devices of above-mentioned exemplary embodiment only carried out the instruction of erasing to the idle part physical blocks of distinguishing after power initiation, can effectively shorten the time that enters armed state after power initiation thus.Moreover storer erasing method, Memory Controller and the memorizer memory devices of above-mentioned exemplary embodiment can be avoided the mistake of overprogram effectively.
Although the present invention discloses as above with embodiment, so it is not to limit the present invention, and any person of an ordinary skill in the technical field when can doing a little change and retouching, and does not break away from the spirit and scope of the present invention.
Claims (21)
1. storer erasing method is used for a duplicative nonvolatile memory module of a memorizer memory devices, and wherein this duplicative nonvolatile memory module has a plurality of physical blocks, and this storer erasing method comprises:
Those physical blocks logically are grouped into a data field and an idle district at least; And
Be afterwards erase mark and initially those flag settings of erasing are an erased status not with each of each those physical blocks configuration one in this idle district at this memorizer memory devices by power initiation (power on).
2. storer erasing method according to claim 1 wherein also comprises:
When extracting a first instance block among those physical blocks in idle district from this, this that then judge this first instance block erased and marked whether to be set to this not erased status; And
When this mark of erasing of this first instance block is set to this not during erased status, to the erase instruction and this mark of erasing of this first instance block is reset to an erased status of this first instance onblock executing one.
3. storer erasing method according to claim 1 wherein also comprises:
Whether judgement does not receive any instruction that comes from a host computer system at a predetermined time period; And
If when after this schedule time, not receiving any instruction that comes from this host computer system, then to erase instruction and this mark of erasing of this second instance block is reset to an erased status of the second instance onblock executing one among those physical blocks in this idle district.
4. storer erasing method according to claim 1 wherein also comprises:
Those marks of erasing of these idle those physical blocks of distinguishing are stored in the memory buffer of this memorizer memory devices.
5. storer erasing method is used for a duplicative nonvolatile memory module of a memorizer memory devices, and wherein this duplicative nonvolatile memory module has a plurality of physical blocks, and this storer erasing method comprises:
Those physical blocks logically are grouped into a data field and an idle district at least;
Set up link (link) inventory and this linked list is stored in this duplicative nonvolatile memory module according to those physical blocks in this idle district, those physical blocks that wherein should idle district be to put in order according to one to be recorded in this linked list; And
After this memorizer memory devices is by power initiation, select a plurality of the 3rd physical blocks among those physical blocks in this idle district and respectively those the 3rd physical blocks are carried out the instruction of erasing according to this linked list and a predetermined number, wherein those the 3rd physical blocks are to be arranged in foremost in this linked list and a number of the 3rd physical blocks is this predetermined number.
6. storer erasing method according to claim 5 wherein also comprises:
When wish is used those physical blocks in this idle district, extract in order those physical blocks in this idle district according to this linked list.
7. storer erasing method according to claim 5 wherein also comprises:
When one the 4th physical blocks among those physical blocks of this data field being associated to this idle district, the 4th physical blocks is carried out this instruction and the 4th physical blocks is recorded in this linked list backmost of erasing.
8. Memory Controller, in order to control a duplicative nonvolatile memory module, wherein this duplicative nonvolatile memory module has a plurality of physical blocks, and this Memory Controller comprises:
One host interface is in order to be electrically connected to a host computer system;
One memory interface is in order to be electrically connected to this duplicative nonvolatile memory module;
One memory management circuitry is electrically connected to this host interface and this memory interface, and in order to those physical blocks logically are grouped at least a data field and an idle district;
Wherein in this memory management circuitry by power initiation (power on) afterwards, this memory management circuitry is erase mark and initially those flag settings of erasing are an erased status not with each of each those physical blocks configuration one in this idle district.
9. Memory Controller according to claim 8,
Wherein when extracting a first instance block among those physical blocks in idle district from this, then this memory management circuitry can judge this first instance block this erase and mark whether to be set to this not erased status,
Wherein be set to this not during erased status when this mark of erasing of this first instance block, this memory management circuitry can be to the erase instruction and this mark of erasing of this first instance block is reset to an erased status of this first instance onblock executing one.
10. Memory Controller according to claim 8,
Wherein this memory management circuitry judges whether do not receive any instruction that comes from this host computer system at a predetermined time period,
If when not receiving any instruction that comes from this host computer system after this schedule time, then this memory management circuitry is to erase instruction and this mark of erasing of this second instance block is reset to an erased status of the second instance onblock executing one among those physical blocks in this idle district.
11. Memory Controller according to claim 8 wherein also comprises a memory buffer, wherein will leave unused those marks of erasing of those physical blocks in district of this memory management circuitry are stored in this memory buffer.
12. a Memory Controller, in order to control a duplicative nonvolatile memory module, wherein this duplicative nonvolatile memory module has a plurality of physical blocks, and this Memory Controller comprises:
One host interface is in order to be electrically connected to a host computer system;
One memory interface is in order to be electrically connected to this duplicative nonvolatile memory module;
One memory management circuitry is electrically connected to this host interface and this memory interface, and in order to those physical blocks logically are grouped at least a data field and an idle district;
Wherein this memory management circuitry is set up link (link) inventory according to those physical blocks in the district of should leaving unused and this linked list is stored in this duplicative nonvolatile memory module, should idle those physical blocks of distinguishing be to put in order according to one to be recorded in this linked list wherein
Wherein after this memory management circuitry is by power initiation, this memory management circuitry is selected a plurality of the 3rd physical blocks among those physical blocks in this idle district and respectively those the 3rd physical blocks is carried out the instruction of erasing according to this linked list and a predetermined number, and wherein those the 3rd physical blocks are to be arranged in foremost in this linked list and a number of the 3rd physical blocks is this predetermined number.
13. Memory Controller according to claim 12, wherein when wish was used those physical blocks in this idle district, this memory management circuitry was extracted those physical blocks in this idle district in order according to this linked list.
14. Memory Controller according to claim 12, wherein when this memory management circuitry is associated to this idle district with one the 4th physical blocks among those physical blocks of this data field, this memory management circuitry can be carried out this instruction and the 4th physical blocks is recorded in this linked list backmost of erasing to the 4th physical blocks.
15. a memorizer memory devices comprises:
A connector is in order to be electrically connected to a host computer system;
One duplicative nonvolatile memory module has a plurality of physical blocks; And
One Memory Controller is electrically connected to this duplicative nonvolatile memory module, and in order to those physical blocks logically being grouped at least a data field and an idle district,
Wherein at this Memory Controller by power initiation (power on) afterwards, this Memory Controller is erase mark and initially those flag settings of erasing are an erased status not with each of each those physical blocks configuration one in this idle district.
16. memorizer memory devices according to claim 15,
Wherein when extracting a first instance block among those physical blocks in idle district from this, then this Memory Controller can judge this first instance block this erase and mark whether to be set to this not erased status,
Wherein be set to this not during erased status when this mark of erasing of this first instance block, this Memory Controller can be to the erase instruction and this mark of erasing of this first instance block is reset to an erased status of this first instance onblock executing one.
17. memorizer memory devices according to claim 15,
Wherein this Memory Controller judges whether do not receive any instruction that comes from this host computer system at a predetermined time period,
If when not receiving any instruction that comes from this host computer system after this schedule time, then this Memory Controller is to erase instruction and this mark of erasing of this second instance block is reset to an erased status of the second instance onblock executing one among those physical blocks in this idle district.
18. memorizer memory devices according to claim 15, wherein will leave unused those marks of erasing of those physical blocks in district of this Memory Controller are stored in the memory buffer.
19. a memorizer memory devices comprises:
A connector is in order to be electrically connected to a host computer system;
One duplicative nonvolatile memory module has a plurality of physical blocks; And
One Memory Controller is electrically connected to this duplicative nonvolatile memory module, and in order to those physical blocks logically being grouped at least a data field and an idle district,
Wherein this Memory Controller is set up link (link) inventory according to those physical blocks in the district of should leaving unused and this linked list is stored in this duplicative nonvolatile memory module, should idle those physical blocks of distinguishing be to put in order according to one to be recorded in this linked list wherein
Wherein after this Memory Controller is by power initiation, this Memory Controller is selected a plurality of the 3rd physical blocks among those physical blocks in this idle district and respectively those the 3rd physical blocks is carried out the instruction of erasing according to this linked list and a predetermined number, and wherein those the 3rd physical blocks are to be arranged in foremost in this linked list and a number of the 3rd physical blocks is this predetermined number.
20. memorizer memory devices according to claim 19, wherein when wish was used those physical blocks in this idle district, this Memory Controller extracted those physical blocks in this idle district in order according to this linked list.
21. memorizer memory devices according to claim 19, wherein when one the 4th physical blocks among those physical blocks of this data field being associated to this idle district, this Memory Controller can be carried out this instruction and the 4th physical blocks is recorded in this linked list backmost of erasing to the 4th physical blocks.
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| CN201510015982.6A CN104598167B (en) | 2011-06-27 | 2011-06-27 | Memory erasing method, Memory Controller and memorizer memory devices |
| CN201110174852.9A CN102855192B (en) | 2011-06-27 | 2011-06-27 | Storer erasing method, Memory Controller and memorizer memory devices |
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