CN102842574A - Semiconductor packaging structure for stacking - Google Patents
Semiconductor packaging structure for stacking Download PDFInfo
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- CN102842574A CN102842574A CN201210228180XA CN201210228180A CN102842574A CN 102842574 A CN102842574 A CN 102842574A CN 201210228180X A CN201210228180X A CN 201210228180XA CN 201210228180 A CN201210228180 A CN 201210228180A CN 102842574 A CN102842574 A CN 102842574A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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Abstract
The invention discloses a semiconductor packaging structure for stacking. An assembling angle of a chip relative to a substrate is regulated until a structure part of a chip body with the maximum length (diagonal) faces to various dies of the substrate, so that a maximum anti-warping structure is provided on various side directions of the substrate, and an upward warping degree of packaging glue on various side directions is relatively reduced; therefore, product reliability and service life of a lower packaging body of a package on package body (POP) are relatively improved indeed.
Description
Technical field
The invention relates to a kind of semiconductor packaging structure that is used to pile up, particularly relevant for a kind of semiconductor packaging structure that is used to pile up that utilizes adjustment chip assembling angle to reduce whole warpage degree.
Background technology
Now; The semiconductor packages industry is in order to satisfy the demand of various high-density packages; Develop the package design that various different types gradually, (system in package, SIP) design concept is usually used in framework high-density packages product to wherein various system in package.Generally speaking, system in package can be divided into multi-chip module (multi chip module, MCM), stacked package body in stacked package body (POP) and the packaging body (package in package, PIP) etc.Said multi-chip module (MCM) is meant lays several chips on same substrate; After chip is set; Utilize same all chips of packing colloid embedding again, and can be subdivided into stacked chips (stacked die) encapsulation or chip (side-by-side) encapsulation side by side again according to the arrangements of chips mode.Moreover; Said stacked package body (POP); Its structure is meant that completion one earlier has first packaging body of substrate; Then pile up another second complete packaging body in the upper surface of first packaging body again, second packaging body sees through suitable adapter assembly (like the tin ball) and is electrically connected on the substrate of first packaging body, thereby becomes a compound packaging structure.In comparison; The structure of stacked package body (PIP) then is to utilize another packing colloid that embedding such as the element of second packaging body, adapter assembly and first packaging body etc. together is fixed on the substrate of first packaging body in the said packaging body, thereby becomes a compound packaging structure.
In the structure of existing stacked package body (POP); The substrate of the following packaging body of its bottom is generally tellite; And packing colloid generally is the epoxy resin base material that is doped with solid filling, and is to utilize transfer casting (transfer molding) technology to make.In recent years, in order to satisfy the lightening requirement of electronic product, the thickness of the following packaging body of existing stacked package body (POP) encapsulating structure is gradually by slimming to 350 micron below (μ m), even slimming to 100 is micron below (μ m).Yet; Under the situation that the thickness of packaging body reduces gradually down; The overall construction intensity of following packaging body also can be weakened gradually; And (coefficient of thermal expansion CTE) there are differences and has the thermal stress effect to pull, thereby produces the phenomenon of warpage (warpage) more easily because the thermal coefficient of expansion between tellite and the packing colloid.Above-mentioned warping phenomenon normally forms warpage towards tellite (CTE about 16～20) at periphery by packing colloid (CTE about 40～80).Simultaneously; Because down the integral thickness attenuation of packaging body also can make the thermal diffusivity variation of chip; Therefore when the heat energy of chip can't be timely and effectively when derive the outside; It is more obvious that above-mentioned warping phenomenon can become, and when serious even can cause packing colloid or tellite to produce slight crack (crack), and then significantly influences the production reliability and the useful life of the following packaging body of stacked package body (POP).
So, be necessary to provide a kind of semiconductor packaging structure that is used to pile up, to solve the existing in prior technology problem.
Summary of the invention
In view of this, the present invention provides a kind of semiconductor packaging structure that is used to pile up, to solve the existing packaging body warpage issues down of existing stacked package body (POP) technology.
Main purpose of the present invention is to provide a kind of semiconductor packaging structure that is used to pile up; It utilizes the assembling angle of adjustment chip with respect to substrate; The structure that makes the own maximum length of chip (diagonal) is partly in the face of substrate side; So that maximum anti-warpage structure is provided on the substrate side direction; In order to the relative minimizing packing colloid upwards warpage degree that direction and second side direction cause in the first side, thereby can promote the production reliability and the useful life of the following packaging body of stacked package body (POP) really relatively.
For reaching aforementioned purpose of the present invention, one embodiment of the invention provides a kind of semiconductor packaging structure that is used to pile up, and it comprises: the chip of the substrate of a rectangle, a rectangle, several adapter assemblies and a packing colloid.The substrate of said rectangle has a upper surface, four substrate sides and four substrate corners, and said upper surface has several weld pads.The upper surface that is fixedly arranged on said substrate of the chip of said rectangle and said substrate concentric; Said chip has four sides of chip and four chip corners; Wherein each said sides of chip accompanies an angle theta with corresponding said substrate side, and said angle theta meets the condition of 0 °＜θ≤45 °.Several said adapter assemblies electrically connect and are incorporated on the said weld pad.Said packing colloid is positioned on the upper surface of said substrate, be centered around said chip around, and coat said adapter assembly, wherein said packing colloid has several fenestras and exposes said adapter assembly.
Moreover another embodiment of the present invention provides a kind of semiconductor packaging structure that is used to pile up, and it comprises: the chip of the substrate of a rectangle, a rectangle, several adapter assemblies and a packing colloid.The substrate of said rectangle has a upper surface, four substrate sides and four substrate corners, and said upper surface has several weld pads.The upper surface that is fixedly arranged on said substrate of the chip of said rectangle and said substrate concentric; Said chip has four sides of chip and four chip corners; Rotation that the said relatively substrate of wherein said chip is a concentric one assembling angle θ z to be being fixedly arranged on the upper surface of said substrate, and said assembling angle θ z meets the condition of 0 °＜θ z≤45 °.Said adapter assembly electrically connects and is incorporated on the said weld pad.Said packing colloid is positioned on the upper surface of said substrate, be centered around said chip around, and coat said adapter assembly, wherein said packing colloid has several fenestras and exposes said adapter assembly.
For letting the foregoing of the present invention can be more obviously understandable, hereinafter is special lifts preferred embodiment, and cooperates appended graphicly, elaborates as follows:
Description of drawings
Fig. 1 is the schematic perspective view of one embodiment of the invention semiconductor packaging structure of being used to pile up.
Figure 1A is the cutaway view of being done along the 1A-1A line of Fig. 1.
Figure 1B is the cutaway view of being done along the 1B-1B line of Fig. 1.
Fig. 2 is the top view of Fig. 1 embodiment of the present invention semiconductor packaging structure of being used to pile up.
Fig. 3 is another top view of Fig. 1 embodiment of the present invention semiconductor packaging structure of being used to pile up.
Fig. 4 is the top view of another embodiment of the present invention semiconductor packaging structure of being used to pile up.
Embodiment
Below the explanation of each embodiment be with reference to additional graphic, can be in order to illustration the present invention in order to the specific embodiment of implementing.Moreover, the direction term that the present invention mentioned, for example " on ", D score, " preceding ", " back ", " left side ", " right side ", " interior ", " outward " or " side " etc., only be direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to restriction the present invention.
Please with reference to shown in Figure 1, it discloses the semiconductor packaging structure that is used to pile up 100 of one embodiment of the invention, and it mainly comprises: the substrate 11 of a rectangle, the chip 12 of a rectangle, several adapter assemblies 13 and a packing colloid 14.Said semiconductor packaging structure 100 is mainly in order to the packaging body once as stacked type packaging body (POP), and can electrically connect packaging body (not illustrating) on through said adapter assembly 13.It is to comprise the square or rectangular with four vertical corners that the present invention reaches hereinafter indication " rectangle " here.
Please with reference to shown in Fig. 1 and the 1A; The substrate 11 of one embodiment of the invention is the rectangular organic tellite of multilayer; For example can be selected from additional layers (build-up) tellite or the pliability film substrate (flexible tape substrate) of the no core layer (coreless) of thickness between 50 to 200 μ m (micron), but be not limited to this.Said substrate 11 is not had a core layer and will be helped reducing relatively its substrate thickness.Said substrate 11 has the first parallel each other substrate side E1 of a upper surface, a lower surface, two, the two mutual parallel second substrate side E2 and four substrate corner C1 in addition, and the surface circuit of said upper surface exposes has several weld pads 111 and a chip bearing district 112.Said weld pad 111 is arranged in four leg-of-mutton pad zones of said upper surface usually; And said four pad zones lay respectively at four substrate corner C1 places near said substrate 11; Each said pad zone has several said weld pads 111; And said chip bearing district 112 is between said four leg-of-mutton pad zones, the shape in said chip bearing district 112 corresponding to and the shape of being a bit larger tham said chip 12.Said chip bearing district 112 is meant a middle section of said upper surface, in said chip bearing district 112, also is distributed with several weld pads 111 usually.The surface circuit of said lower surface is also exposed to have several weld pads (not indicating), and by the weld pad solder bond of these lower surfaces several metal ball 113 is arranged, with the electric terminal of using as said substrate 11 I/O.
Moreover; Said 2 first substrate side E1 reach against each other and are parallel to each other; Said 2 second substrate side E2 also reach against each other and are parallel to each other; The two ends system of each first substrate side E1 is connected with said 2 second substrate side E2 respectively, and forms a substrate corner C1 respectively, and said substrate corner C1 is all 90 ° right angle.If said substrate 11 is rectangles, the then said first substrate side E1 and the second substrate side E2 have different length; If said substrate 11 is squares, the then said first substrate side E1 and the second substrate side E2 have equal length.
Please with reference to shown in Fig. 1,1A and the 1B, the chip 12 of one embodiment of the invention can be various semiconductor chips, for example high frequency chip, CPU (CPU) chip or memory body chip (like DRAM or FLASH) etc., but do not limit.Said chip 12 can be the form of flip-chip (flip chip) or the form of routing chip (wire bonding chip).With the flip-chip is example, the active surface of said chip 12 down, and through several projection 121 solder bond and be fixedly arranged on the weld pad 111 in the chip bearing district 112 of said substrate 11.Can be filled with a underfill (underfill) 122 between the upper surface of said chip 12 and said substrate 10, but also can omit.The thickness of said chip 12 can be between 100 to 40 μ m.Said projection 121 can be selected from tin projection (bumps), golden projection or copper post projection (Cu pillar bumps) etc., and the height of said projection 121 is about 30 to 50 μ m.
Moreover; Said chip 12 is the chip bearing districts 112 with the upper surface that is fixedly arranged on said substrate 11 of said substrate 11 concentrics; Said chip 12 itself has the two each other parallel first sides of chip F1, the two mutual parallel second sides of chip F2 and four chip corner C2 in addition; Wherein said 2 first sides of chip F1 reach against each other and are parallel to each other, and said 2 second sides of chip F2 also reach against each other and are parallel to each other, and the two ends system of each first sides of chip F1 is connected with said 2 second sides of chip F2 respectively; And forming a chip corner C2 respectively, said chip corner C2 is all 90 ° right angle.Each said chip corner C2 is respectively in the face of one said first or the second substrate side E1, E2; Each said substrate corner C1 is also respectively in the face of one said first or the second sides of chip F1, F2.Have a bit of preset space length between the said first or second substrate side E1 that each said chip corner C2 and its are faced, the E2, said chip corner C2 does not directly contact with the said first or second substrate side E1, E2.If said chip 12 is rectangles, the then said first sides of chip F1 and the second sides of chip F2 have different length; If said chip 12 is squares, the then said first sides of chip F1 and the second sides of chip F2 have equal length.
Then; Please with reference to shown in Fig. 1 and 2; The said first sides of chip F1 is corresponding to the said first substrate side E1, and the said second sides of chip F2 is corresponding to the said second substrate side E2, and each said first sides of chip F1 accompanies one first angle theta 1 with the corresponding said first substrate side E1; Said first angle theta 1 meets the condition of 1≤45 ° of 0 °＜θ; Reach each said second sides of chip F2 and accompany one second angle theta 2 with the corresponding said second substrate side E2, said second angle theta 2 also meets the condition of 2≤45 ° of 0 °＜θ, and wherein said first and second angle theta 1, θ 2 are referred to as angle theta.Just, be fixedly arranged on the said substrate 11 behind the rotation one assembling angle θ z that also to can be considered the said relatively substrate 11 of said chip 12 are concentrics, said assembling angle θ z meets the condition of 0 °＜θ z≤45 ° again.Said first angle theta 1, second angle theta 2 and assembling angle θ z for example are 45 °, 36 °, 30 °, 15 °, 10 °, 5 ° or 1 ° etc. simultaneously, and in the present embodiment, this three is to be 45 ° simultaneously.Moreover the extension of the formed diagonal L2 of chip corner C2 at each two diagonal angle can be intersected with the said first or second substrate side E1, last other any point positions (not indicating) except said substrate corner C1 of E2.For example, when said first angle theta 1, second angle theta 2 and assembling angle θ z were 45 ° simultaneously, the extended line of said diagonal L 2 can intersect with the said first or second substrate side E1, the last center position (indicating) of E2.
In the present embodiment; The present invention's " correspondence " of indication here is meant that it is one group of sides of chip and substrate side with corresponding relation that each sides of chip substrate side immediate with it promptly can be considered if the not said relatively substrate 11 of said chip 12 rotates before the assembling angles.Moreover; " concentric " of above-mentioned indication reaches " the angle θ z that concentric rotates " and is meant that the two dimensional surface that said first and second substrate side E1, E2 are formed is regarded as an XY plane; With respect to said XY plane; Said chip 12 has same geometric center C0 with said substrate 11, makes said substrate 11 keep static, lets said chip 12 be said assembling angle θ z along the angle of the axis direction rotation (as clockwise rotating) of the Z axle of this geometric center C0.If the formed substrate diagonal L 1 of said substrate corner C1 with the formed chip diagonal L 2 of the said chip corner C2 at each two diagonal angle and each two diagonal angle is a benchmark; Said chip diagonal L 2 has identical axle center C0 with substrate diagonal L 1, and said assembling angle θ z is the angle between said chip diagonal L 2 and the substrate diagonal L 1.
Please refer again to shown in Fig. 1 and the 1A; Several adapter assemblies 13 of one embodiment of the invention electrically connect and are incorporated on the weld pad 111 in four leg-of-mutton pad zones of said substrate 11 upper surfaces, and said adapter assembly 13 can be selected from tin projection (solder bumps), golden projection (gold bumps), copper post projection (Cu pillar bumps) or wear glue via (through molding via).The height of said adapter assembly 13 is the height summations that are designed to be slightly less than said chip 12 and projection 121.
Please refer again to shown in Fig. 1,1A and the 1B; The packing colloid 14 of one embodiment of the invention for example is the epoxy resin base material that is doped with solid filling; And be to utilize transfer casting (transfer molding) technology to make, said solid filling can be silica dioxide granule or alumina particle etc.Said packing colloid 14 is positioned on the upper surface of said substrate 11; Be centered around said chip 12 around; And coating said adapter assembly 13, a upper surface of wherein said packing colloid 14 is punchinged via laser (laser) and is formed a part of surface that several fenestras 141 can supply to expose said adapter assembly 13.One upper surface of said packing colloid 14 also exposes the end face (back side) of said chip 12, with the radiating efficiency of the said chip 12 of relative raising.Moreover; Because the arrangement mode of said adapter assembly 13 and fenestra 141 is same as said weld pad 111; Therefore said adapter assembly 13 and fenestra 141 in fact also are positioned at four leg-of-mutton pad zones of said substrate 11; The chip 12 that also makes simultaneously said packing colloid 14 be provided with by skew is roughly distinguished and is divided into four triangle sealing sub-block, but in fact said four triangle sealing blocks be still and be connected with each other together, and just said chip 12 is centered on by said packing colloid 14 fully.
As shown in Figure 1, the thermal coefficient of expansion of said substrate 11 (CTE) about 16～20; The thermal coefficient of expansion of said chip 12 (CTE) about 2.3～2.5; The thermal coefficient of expansion of said packing colloid 14 (CTE) about 40～80; Therefore when said chip 12 runnings produced heat energy, said packing colloid 14 expanded by heating degree were maximum.With regard to prior art; Each respective side of chip and substrate is the alignment arrangements with the parallel mode concentric; But, therefore will cause bigger warpage radian (forming warpage towards substrate at periphery) at peripheral position by packing colloid because packing colloid all has bigger length and width in each side of chip periphery.Be head it off; This embodiment of the present invention promptly utilizes the assembling angle θ z that changes the less relatively said chip 12 of thermal coefficient of expansion to make it meet the condition (for example 45 °) of 0 °＜θ z≤45 °; The structure that so can make said chip 12 own maximum lengths (being diagonal L 2) is partly in the face of said first and second substrate side E1, E2; On this two substrate sides direction (being X, Y direction), maximum anti-warpage structure to be provided; So help said packing colloid 14 districts are divided into four triangle sealing sub-block; Relatively reduce the warpage degree that said packing colloid 14 each sealing sub-block cause in the first substrate side E1 direction and the second substrate side E2 direction respectively, thereby can promote the production reliability and the useful life of the following packaging body of stacked package body (POP) really relatively.
Please with reference to shown in Figure 3; The semiconductor packaging structure that is used to pile up of another embodiment of the present invention is similar in appearance to Fig. 1 embodiment of the present invention; And roughly continue to use similar elements title and figure number; But the difference characteristic of Fig. 3 embodiment is: first angle theta 1 of the semiconductor packaging structure 10 of present embodiment, second angle theta 2 and assembling angle θ z are also identical each other, but its numerical value is to be designed to less than 45 °, for example 36 °, 30 °, 15 °, 10 °, 5 ° or 1 ° etc.So; Present embodiment can make the structure of said chip 12 maximum lengths (being diagonal L 2) own partly in the face of said first and second substrate side E1, E2 equally; On this two substrate sides direction (being X, Y direction), maximum anti-warpage structure to be provided; Be beneficial to said packing colloid 14 districts are divided into four triangle sealing sub-block; Relatively reduce the warpage degree that each sealing sub-block causes in the first substrate side E1 direction and the second substrate side E2 direction respectively, thereby can promote the production reliability and the useful life of the following packaging body of stacked package body (POP) really relatively.
Please with reference to shown in Figure 4; The semiconductor packaging structure that is used to pile up of further embodiment of this invention is similar in appearance to Fig. 1 of the present invention or Fig. 2 embodiment; And roughly continue to use similar elements title and figure number; But the difference characteristic of Fig. 4 embodiment is: the chip 12 of the semiconductor packaging structure 10 of present embodiment is the form of routing chip (wire bonding chip), the active surface of said chip 12 up, and through several wires 123 solder bond and be fixedly arranged on the weld pad 111 around the chip bearing district 112 of said substrate 11; Weld pad 111 need be set in the said chip bearing district 112, said lead 123 can be gold thread, copper cash, aluminum steel or its alloy wire etc.Can be filled with a underfill or stickiness adhesive tape (not illustrating) between the upper surface of the back side of said chip 12 (being lower surface) and said substrate 10.The active surface of said chip 12 receives said packing colloid 14 and coats protection fully, but in case of necessity, the active surface of said chip 12 also can extraly be provided with a radiating fin (not illustrating) and make its convex reaching outside the said packing colloid 14, to increase radiating efficiency.So; Present embodiment can be divided into four triangle sealing sub-block with said packing colloid 14 districts equally; Relatively reduce the warpage degree that each sealing sub-block causes in the first substrate side E1 direction and the second substrate side E2 direction respectively, thereby can promote the production reliability and the useful life of the following packaging body of stacked package body (POP) really relatively.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is merely the example of embodiment of the present invention.Must be pointed out that disclosed embodiment does not limit scope of the present invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in scope of the present invention.
Claims (10)
1. semiconductor packaging structure that is used to pile up, it is characterized in that: the said semiconductor packaging structure that is used to pile up comprises:
The substrate of one rectangle has a upper surface, four substrate sides and four substrate corners, and said upper surface has several weld pads;
The chip of one rectangle; The upper surface that is fixedly arranged on said substrate with said substrate concentric; Said chip has four sides of chip and four chip corners; Wherein each said sides of chip accompanies an angle theta with corresponding said substrate side, and said angle theta meets the condition of 0 °＜θ≤45 °;
Several adapter assemblies electrically connect and are incorporated on the said weld pad; And
One packing colloid is positioned on the upper surface of said substrate, be centered around said chip around, and coat said adapter assembly, wherein said packing colloid has several fenestras and exposes said adapter assembly.
2. the semiconductor packaging structure that is used to pile up as claimed in claim 1; It is characterized in that: the upper surface of said substrate has the chip bearing district of four leg-of-mutton pad zones and a rectangle; Said four pad zones lay respectively at four substrate corner places of said substrate; Each said pad zone has several said weld pads, and said chip bearing district is positioned between said four pad zones, and said chip bearing district is corresponding to said chip.
3. the semiconductor packaging structure that is used to pile up as claimed in claim 2; It is characterized in that: said adapter assembly is positioned at four leg-of-mutton pad zones of said substrate; Said packing colloid is divided into four triangle sealing sub-block by said chip region; Said four triangle sealing blocks are connected with each other together, and said chip is centered on by said packing colloid fully.
4. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: each said chip corner is respectively in the face of a said substrate side; And each said substrate corner is respectively in the face of a said sides of chip.
5. the semiconductor packaging structure that is used to pile up as claimed in claim 4 is characterized in that: any point position on the chip corner cornerwise extension of a formed chip at each two diagonal angle of said chip and two the said substrate sides except said substrate corner is crossing.
6. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: said adapter assembly is selected from tin projection, golden projection, copper post projection or wears the glue via.
7. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: a upper surface of said packing colloid exposes an end face of said chip.
8. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: said semiconductor packaging structure is as the packaging body once of stacked type packaging body, and electrically connects packaging body on through said adapter assembly.
9. semiconductor packaging structure that is used to pile up, it is characterized in that: the said semiconductor packaging structure that is used to pile up comprises:
The substrate of one rectangle has a upper surface, four substrate sides and four substrate corners, and said upper surface has several weld pads;
The chip of one rectangle; The upper surface that is fixedly arranged on said substrate with said substrate concentric; Said chip has four sides of chip and four chip corners; Rotation that the said relatively substrate of wherein said chip is a concentric one assembling angle θ z to be being fixedly arranged on the upper surface of said substrate, and said assembling angle θ z meets the condition of 0 °＜θ z≤45 °;
Several adapter assemblies electrically connect and are incorporated on the said weld pad; And
One packing colloid is positioned on the upper surface of said substrate, be centered around said chip around, and coat said adapter assembly, wherein said packing colloid has several fenestras and exposes said adapter assembly.
10. the semiconductor packaging structure that is used to pile up as claimed in claim 9 is characterized in that: the formed chip diagonal of said chip corner at each two diagonal angle and the formed substrate diagonal concentric of said substrate corner at each two diagonal angle and accompany said angle θ z.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210228180XA CN102842574A (en) | 2012-07-03 | 2012-07-03 | Semiconductor packaging structure for stacking |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210228180XA CN102842574A (en) | 2012-07-03 | 2012-07-03 | Semiconductor packaging structure for stacking |
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| CN102842574A true CN102842574A (en) | 2012-12-26 |
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Application publication date: 20121226 |