CN102841856B - 将数据写入数据处理系统内的系统存储器的方法和系统 - Google Patents

将数据写入数据处理系统内的系统存储器的方法和系统 Download PDF

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Publication number
CN102841856B
CN102841856B CN201210188567.7A CN201210188567A CN102841856B CN 102841856 B CN102841856 B CN 102841856B CN 201210188567 A CN201210188567 A CN 201210188567A CN 102841856 B CN102841856 B CN 102841856B
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China
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cache lines
cache
stored
tracking
instruction
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CN201210188567.7A
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Chinese (zh)
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CN102841856A (zh
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B·C·格雷森
W·T·钱戈瓦柴
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NXP USA Inc
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Freescale Semiconductor Inc
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201210188567.7A 2011-06-10 2012-06-08 将数据写入数据处理系统内的系统存储器的方法和系统 Expired - Fee Related CN102841856B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/157,549 2011-06-10
US13/157,549 US8543766B2 (en) 2011-06-10 2011-06-10 Writing data to system memory in a data processing system in which cache line states are tracked

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CN102841856A CN102841856A (zh) 2012-12-26
CN102841856B true CN102841856B (zh) 2017-05-03

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US (1) US8543766B2 (https=)
JP (1) JP6008362B2 (https=)
CN (1) CN102841856B (https=)

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KR20150138211A (ko) 2013-03-28 2015-12-09 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 메모리 활성화 레이트의 조정
EP2992531B1 (en) 2013-04-30 2019-06-19 Hewlett-Packard Enterprise Development LP Memory access rate
US9552301B2 (en) * 2013-07-15 2017-01-24 Advanced Micro Devices, Inc. Method and apparatus related to cache memory
US10558569B2 (en) * 2013-10-31 2020-02-11 Hewlett Packard Enterprise Development Lp Cache controller for non-volatile memory
US9767041B2 (en) * 2015-05-26 2017-09-19 Intel Corporation Managing sectored cache
WO2017074416A1 (en) 2015-10-30 2017-05-04 Hewlett Packard Enterprise Development Lp Managing cache operations using epochs
USRE50518E1 (en) * 2016-03-24 2025-08-05 Samsung Electronics Co., Ltd. Method and device for controlling memory
KR102778454B1 (ko) * 2016-03-24 2025-03-11 삼성전자주식회사 메모리 제어 방법 및 장치
US10482033B2 (en) * 2016-03-24 2019-11-19 Samsung Electronics Co., Ltd Method and device for controlling memory
US9923562B1 (en) 2016-06-16 2018-03-20 Western Digital Technologies, Inc. Data storage device state detection on power loss
US11561906B2 (en) 2017-12-12 2023-01-24 Advanced Micro Devices, Inc. Rinsing cache lines from a common memory page to memory
US10713165B2 (en) * 2018-02-12 2020-07-14 Wisconsin Alumni Research Foundation Adaptive computer cache architecture
US11074188B2 (en) * 2019-02-18 2021-07-27 Intel Corporation Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory
WO2021103020A1 (zh) * 2019-11-29 2021-06-03 华为技术有限公司 缓存存储器和分配写操作的方法
CN114157621A (zh) * 2020-09-07 2022-03-08 华为技术有限公司 一种发送清除报文的方法及装置
US12380033B2 (en) * 2022-01-21 2025-08-05 Centaur Technology, Inc. Refreshing cache regions using a memory controller and multiple tables

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CN1425154A (zh) * 1999-12-30 2003-06-18 英特尔公司 高速缓冲存储器线清洗微结构执行方法和系统

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CN1425154A (zh) * 1999-12-30 2003-06-18 英特尔公司 高速缓冲存储器线清洗微结构执行方法和系统

Also Published As

Publication number Publication date
US8543766B2 (en) 2013-09-24
JP6008362B2 (ja) 2016-10-19
JP2013004091A (ja) 2013-01-07
US20120317367A1 (en) 2012-12-13
CN102841856A (zh) 2012-12-26

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